An integrated multi-pin overvoltage protection structure and a manufacturing method thereof

Abstract

The application discloses an integrated multi-pin overvoltage protection structure and a manufacturing method thereof, and relates to the technical field of semiconductor integrated circuits. The structure is sequentially provided with a buffer P-type epitaxial layer and a top P-type epitaxial layer upwards on a P-type heavily doped substrate. A P-type buried layer is located in the buffer P-type epitaxial layer, and P-type buried layers with different doping concentrations are represented as PUBLn. An N-type buried layer is located at the junction of the buffer P-type epitaxial layer and the top P-type epitaxial layer, and is represented as NBL. The P-type buried layer is located directly below the N-type buried layer. The NBL and the PUBLn with different doping concentrations form overvoltage clamping diodes with different avalanche breakdown voltages, and the overvoltage clamping diodes clamp and protect pins with different maximum voltage ratings. The application does not need to additionally increase the chip area, but can realize considerable system ESD and overvoltage and surge protection functions by only increasing the injection levels for each voltage grade, thereby saving the system board area and not increasing the chip area itself.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and more specifically to an integrated multi-pin overvoltage protection structure and its manufacturing method. Background Technology

[0002] Integrated circuits typically have multiple pins with their own permissible absolute maximum rated voltage values. If the voltage exceeds this absolute maximum rated voltage for a certain period, it may cause permanent functional or reliability damage to the internal circuitry. However, in practical system applications, especially with integrated circuits used in interfaces, pins inevitably encounter unexpected and uncontrollable transient high voltages exceeding their maximum rated voltage values. Examples include switching overshoot, electrostatic discharge (ESD), and system surge residual voltage. These can all cause sudden damage to the circuit. To protect the integrated circuit's normal operation, the transient voltage must be clamped to a safe voltage level. Currently, a common approach is to add a transient voltage suppressor (VTS) external to the pin. When encountering a transient overvoltage, the VTS can rapidly change its impedance from high to low, absorbing the instantaneous large current and clamping the voltage across it to a predetermined value, protecting the internal circuitry from transient high voltage spikes. When multiple pins of a chip require protection, multiple external VTSs are needed. Adding multiple protection devices increases system area, cost, and reliability risks, hindering the trend towards thinner and lighter devices. Integrating multiple protection devices into a single chip to achieve maximum integration has always been a challenge for interface chips. One existing approach is to utilize the chip's effective area to add a planar protection module, such as a surge detection circuit and a surge clamping high-voltage MOSFET. The surge detection circuit controls the surge protection MOSFET near the overvoltage clamping value to clamp and discharge transient overvoltage energy, thus protecting the internal circuitry. However, since the transient overvoltage energy levels to be protected are typically large, a very large chip area is required for the overvoltage protection module. When protecting multiple different voltage pins, this solution becomes extremely inefficient in terms of area. The protection devices occupy the majority of the chip area, while the actual integrated circuit functional modules occupy only a small portion, drastically reducing area efficiency and significantly increasing chip cost.

[0003] Therefore, how to achieve integrated overvoltage protection with high area efficiency in an economical and effective manner is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the present invention proposes a structure and manufacturing process method for integrated overvoltage clamping protection of multiple different voltage pins of an integrated circuit. Unlike the existing technology that uses surface-mount devices to achieve clamping protection by increasing chip area, the core of the present invention is to form overvoltage clamping diodes with different clamping voltages in a three-dimensional form, below the N-type buried layer under the surface of the integrated circuit, through multiple photolithography processes and different P-type doping injection conditions after photolithography, as well as diffusion processes. The common ground terminal of the anode of each diode is led out from the back side through a heavily doped P-type substrate. The cathodes of different overvoltage clamping diodes contact the N-type buried layer through the top N-well or heavily doped N-sinker and are led out from the surface.

[0005] Specifically, to achieve the above objectives, the present invention provides the following technical solution:

[0006] An integrated multi-pin overvoltage protection structure comprises a buffer P-type epitaxial layer and a top P-type epitaxial layer sequentially arranged from bottom to top on a heavily doped P-type substrate. A P-type buried layer is located within the buffer P-type epitaxial layer. P-type buried layers with different doping concentrations are denoted by PUBLn, where n is an integer from 1 to 5, representing the serial number of the overvoltage clamping diode formed by different P-type buried layers. An N-type buried layer is located at the junction of the buffer P-type epitaxial layer and the top P-type epitaxial layer, denoted by NBL. Part of the N-type buried layer is in the buffer P-type epitaxial layer, and part extends backward into the top P-type epitaxial layer. The P-type buried layer is located directly below the N-type buried layer.

[0007] Optionally, NBL and PUBLn with different doping concentrations can form overvoltage clamping diodes with different avalanche breakdown voltages to provide overvoltage clamping protection for pins with different rated maximum voltages.

[0008] Optionally, one or more overvoltage clamping diodes with the same avalanche breakdown voltage can be used to protect the same pin; when multiple overvoltage clamping diodes with the same avalanche breakdown voltage are selected to protect the same pin, the multiple overvoltage clamping diodes with the same avalanche breakdown voltage must be connected in parallel.

[0009] Optionally, the junction between the P-type buried layer PUBLn and the N-type buried layer NBL is the interface of different PN junctions of each overvoltage clamping diode.

[0010] Optionally, a deep N-well or heavily doped N-Sinker layer is located in the top P-type epitaxial layer and contacts the N-type buried layer in the top P-type epitaxial layer, leading the N-type buried layer that constitutes the cathode of the overvoltage clamping diode to the surface of the top P-type epitaxial layer, and then leading it out from the N+ active region on the surface.

[0011] Optionally, each P-type buried layer PUBLn constituting the anode of the overvoltage clamping diode is led out from the back gold layer formed by deposition on the back of the thinned P-type heavily doped substrate. The back gold material is Ti / Ni / Ag, and the thickness of the thinned substrate is 120um to 300um. The potential is connected to the common substrate ground terminal of the chip.

[0012] Optionally, the resistivity of the heavily doped P-type substrate ranges from 0.01 ohm*cm to 0.2 ohm*cm, the thickness of the buffer P-type epitaxial layer ranges from 3 μm to 20 μm, the resistivity of the top P-type epitaxial layer ranges from 5 ohm*cm to 20 ohm*cm, and the thickness of the top P-type epitaxial layer ranges from 3 μm to 10 μm.

[0013] Optionally, the doping concentration of PUBLn can be controlled by different implantation doses and energy conditions, with the implantation dose ranging from 1e... 13 / cm 2 ~5e 15 / cm 2 The thermal diffusion process ranges from 900℃ to 1100℃, with a high-temperature thermal diffusion time of 30 to 120 minutes. The final doping concentration at the PUBLn-NBL interface ranges from 2e⁻¹. 16 / cm 3 ~5e 18 / cm 3 .

[0014] A method for manufacturing an integrated multi-pin overvoltage protection structure, used to manufacture the integrated multi-pin overvoltage protection structure described in any of the preceding claims, the method comprising the following steps:

[0015] Step 1: Form a buffered P-type epitaxial layer on a heavily doped P-type substrate;

[0016] Step 2: Perform PUBLn pattern photolithography on the buffer P-type epitaxial layer, and then perform B doping implantation under PUBLn conditions;

[0017] Step 3: Grow a thin oxide layer and perform thermal diffusion;

[0018] Step 4: Perform NBL patterning using BCD process on the buffer P-type epitaxial layer, followed by NBL doping implantation and thermal diffusion propagation.

[0019] Step 5: Grow the top P-type epitaxial layer containing the BCD process surface device;

[0020] Step 6: Perform deep N-well photolithography and deep N-well implantation using the BCD process, and thermal propulsion to bring the deep N-well into contact with the NBL;

[0021] Step 7: Perform the pre-processing steps for surface device fabrication using the BCD process;

[0022] Step 8: Perform the post-processing metallization of the BCD process, using metal to lead the cathodes of each different overvoltage clamping diode to the silicon surface.

[0023] Step 9: After the BCD process is completed, perform back-side grinding.

[0024] Step 10: Perform Ti / Ni / Ag back gold process to form a P-type heavily doped back lead, and connect the anode of each overvoltage clamping diode to the back common ground terminal.

[0025] As can be seen from the above technical solution, the present invention provides an integrated multi-pin overvoltage protection structure and its manufacturing method, which has the following advantages compared with the prior art:

[0026] This invention proposes a pin clamping protection scheme for multiple voltage levels within a single chip. It achieves substantial system ESD, overvoltage, and surge protection without increasing chip area, simply by adding an injection layer for each voltage level. By addressing the pin clamping protection requirements of different voltage levels, this invention adds a process layer and corresponding injection conditions for each voltage level, forming an internal clamping protection diode embedded beneath the chip's N-type buried layer. This saves on external transient voltage suppression diodes, conserves system board area, and does not increase the chip's own area. It is an innovative, high-efficiency, and low-cost integrated protection solution for ESD, surge, and other overvoltage electrical stresses, suitable for current interface-type integrated circuit products. Furthermore, the area of ​​the structure itself can be easily adjusted, facilitating the achievement of high-level ESD protection capabilities. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of the integrated multi-pin overvoltage protection structure of the present invention;

[0029] Figure 2 This is a top view of the integrated multi-pin overvoltage protection structure of the present invention;

[0030] Figure 3 The integrated multi-pin overvoltage protection structure of this invention is along Figure 2 A schematic diagram of the A-A' section;

[0031] Where a is the first overvoltage clamping diode, b is the second overvoltage clamping diode, and c is the third overvoltage clamping diode;

[0032] 21 is the chip boundary, 22 is the graphic boundary of the first NBL of internal circuit A, 23 is the graphic boundary of the first PUBL1 of internal circuit A, 25 is the graphic boundary of the second NBL of internal circuit B, 26 is the graphic boundary of the second PUBL1 of internal circuit B, 24 is a schematic diagram of the parallel short-circuit relationship between the metal of the first NBL and the second NBL, 27 is the graphic boundary of the third NBL of internal circuit C, 28 is the graphic boundary of PUBL2 of internal circuit C, and 29 is internal circuit D.

[0033] 1 is a heavily doped P-type substrate, 8 is a back gold layer, 2 is a buffer P-type epitaxial layer, 3 is a top P-type epitaxial layer, 4 is a heavily doped N-type buried layer (NBL), 5 is PUBL2, 61 is the first PUBL1, 62 is the second PUBL1, 7 is a deep N-well or a heavily doped N-type N-Sinker layer, and 9 is... Figure 2 The schematic diagram of the components used in internal circuit A is shown, with 10 and 11 being... Figure 2 A schematic diagram of the components used in internal circuit B, number 12. Figure 2 The schematic diagram shows the components used in the internal circuit C. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] This invention uses an integrated circuit with two overvoltage clamping protection pins when n=2 as an example to explain the solution of this invention.

[0036] Figure 1 This is a schematic diagram of the integrated multi-pin overvoltage protection structure circuit proposed in this invention. The first overvoltage clamping diode formed by the isolation NBL of internal circuit A and its lower PUBL1 is labeled a. The second overvoltage clamping diode formed by the isolation NBL of internal circuit B and PUBL1 is labeled b. The first overvoltage clamping diode a and the second overvoltage clamping diode b are connected in parallel and are overvoltage clamping diodes with the same avalanche breakdown voltage, used to protect pin 1. The third overvoltage clamping diode formed by the isolation NBL of internal circuit C and PUBL2 is labeled c. The third overvoltage clamping diode c provides protection for pin 2. Internal circuit D represents other circuits in the chip.

[0037] Figure 2 This is a top view of the integrated multi-pin overvoltage protection structure proposed in this invention. Let NBL of internal circuit A be the first NBL, PUBL1 be the first PUBL1, NBL of internal circuit B be the second NBL, PUBL1 be the second PUBL1, and NBL of internal circuit C be the third NBL. Label 21 indicates the chip boundary, label 22 indicates the graphic boundary of the first NBL of internal circuit A, and label 23 indicates the graphic boundary of the first PUBL1 below the first NBL. The first NBL and the first PUBL1 form... Figure 1 The first overvoltage clamping diode a; label 25 indicates the graphic boundary of the second NBL in internal circuit B, and label 26 indicates the graphic boundary of the second PUBL1 below the second NBL. The second NBL and the second PUBL1 form... Figure 1 The second overvoltage clamping diode b; label 24 is a schematic diagram showing the metal parallel short-circuit relationship between the first NBL and the second NBL; label 27 is the graphic boundary of the third NBL in the internal circuit C; label 28 is the graphic boundary of PUBL2 below the third NBL. The third NBL and PUBL2 form Figure 1 The third overvoltage clamping diode c is shown in the diagram. Label 29 indicates internal circuitry D, representing other unrelated circuits in the chip layout.

[0038] Figure 3 The integrated multi-pin overvoltage protection structure proposed in this invention is along Figure 2 A schematic diagram of the A-A' cross-section, labeled 1 as a heavily doped P-type substrate; labeled 8 as the back gold layer led out from the back of the heavily doped P-type substrate; labeled 2 as a buffer P-type epitaxial layer; labeled 3 as the top P-type epitaxial layer; labeled 4 as a heavily doped N-type buried layer (NBL); labeled 5 as PUBL2; labeled 61 as the first PUBL1; labeled 62 as the second PUBL1. It can be seen that the first PUBL1 and the second PUBL1 are PUBLs with the same doping concentration; labeled 7 as a deep N-well or a heavily doped N-Sinker layer leading the NBL to the surface of the top P-type epitaxial layer 3; labeled 9 as... Figure 2 The schematic diagram of the components used in internal circuit A is shown in Figures 10 and 11. Figure 2 A schematic diagram of the components used in internal circuit B, labeled 12. Figure 2 A schematic diagram of the components used in the internal circuit C. In Figure 3 In the circuit, pin 1 is protected by two overvoltage clamping protection diodes a and b, which are formed by an N-type buried layer and PUBL1 and are located below the surface devices of internal circuit A and internal circuit B, respectively. Pin 2 is protected by a third overvoltage clamping diode c, which is formed by an N-type buried layer and PUBL2 and is located below the surface devices of internal circuit C.

[0039] There can be various combinations of specific implementation methods. A typical implementation uses multiple PUBL1 and PUBL2 pins with different doping concentrations formed beneath an N-type buried layer connected to pins with different rated maximum potentials. This creates overvoltage clamping diodes with different avalanche voltages. The N-type buried layer is led out from a deep N-well or a heavily doped N-Sinker layer to the surface of the top epitaxial layer, serving as the cathode. The PUBLs are led out from the back gold surface of a heavily doped P-type substrate, forming the anode connected to the parasitic clamping diode. This provides protection for multiple pins with different rated maximum potentials. Figure 3 This is a schematic diagram of a typical implementation scheme of the present invention in the BCD process. It uses two parallel overvoltage clamping diodes based on NBL and PUBL1 to clamp and protect pin 1, and overvoltage clamping diodes based on NBL and PUBL2 to protect pin 2.

[0040] Taking the integrated circuit with n=2 in the above embodiment as an example, its manufacturing method is as follows:

[0041] Step 1: Form a 10µm thick buffer P-type epitaxial layer on a heavily doped P-type substrate with a resistivity of 0.01 ohm*cm.

[0042] Step 2: Perform PUBL1 pattern photolithography on the buffer P-type epitaxial layer, and then perform B doping implantation under PUBL1 conditions;

[0043] Step 3: Perform PUBL2 pattern photolithography on the buffer P-type epitaxial layer, and then perform B doping implantation under PUBL2 conditions;

[0044] Step 4: Grow a thin oxide layer and perform thermal diffusion at 1050℃ for 60 minutes;

[0045] Step 5: Perform NBL patterning using BCD process on the buffer P-type epitaxial layer, then perform NBL doping implantation and thermal diffusion propagation.

[0046] Step 6: Grow the top epitaxial layer of 3-10µm containing the BCD process surface device;

[0047] Step 7: Perform deep N-well photolithography and deep N-well implantation using the BCD process, and thermal propulsion to bring the deep N-well into contact with the NBL, which can lead the NBL to the surface.

[0048] Step 8: Perform the pre-processing steps for surface device formation using BCD technology, where N-type implantation layers can be implanted into the deep N-wells from which NBLs are led out in order to reduce the parasitic resistance when leading out NBLs from the deep N-wells.

[0049] Step 9: Perform the post-processing metallization of the BCD process, using metal to bring out the cathodes of each different overvoltage clamping diode to the silicon surface.

[0050] Step 10: After the BCD process is completed, back-side grinding is performed, with a typical film thickness of 180µm.

[0051] Step 11: Perform Ti / Ni / Ag back gold process to form a P-type heavily doped back lead, and connect the anode of each clamping diode to the back common ground terminal.

[0052] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0053] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated multi-pin overvoltage protection structure, characterized in that, A buffer P-type epitaxial layer and a top P-type epitaxial layer are sequentially disposed on a heavily doped P-type substrate; a P-type buried layer is located in the buffer P-type epitaxial layer, and P-type buried layers with different doping concentrations are denoted as PUBLn; an N-type buried layer is located at the junction of the buffer P-type epitaxial layer and the top P-type epitaxial layer, and is denoted as NBL; NBL and PUBLn with different doping concentrations form overvoltage clamping diodes with different avalanche breakdown voltages, providing overvoltage clamping protection for pins with different rated maximum voltages; the P-type buried layer is located directly below the N-type buried layer.

2. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, In PUBLn, n is an integer from 1 to 5.

3. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, When multiple overvoltage clamping diodes with the same avalanche breakdown voltage protect the same pin, the multiple overvoltage clamping diodes with the same avalanche breakdown voltage are connected in parallel.

4. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, The junction between the P-type and N-type buried layers is the PN junction interface of the overvoltage clamping diode.

5. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, A deep N-well or heavily doped N-Sinker layer is located in the top P-type epitaxial layer and contacts the N-type buried layer in the top P-type epitaxial layer. The N-type buried layer that forms the cathode of the overvoltage clamping diode is led out to the surface of the top P-type epitaxial layer and then led out by the N+ active region on the surface.

6. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, Each P-type buried layer PUBLn constituting the anode of the overvoltage clamping diode is led out from the back gold layer formed by deposition on the back of the thinned P-type heavily doped substrate. The back gold material is Ti / Ni / Ag, and the thickness of the thinned substrate is 120um~300um. The potential is connected to the common substrate ground terminal of the chip.

7. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, The resistivity of the heavily doped P-type substrate ranges from 0.01 ohm*cm to 0.2 ohm*cm, the thickness of the buffer P-type epitaxial layer ranges from 3 μm to 20 μm, the resistivity of the top P-type epitaxial layer ranges from 5 ohm*cm to 20 ohm*cm, and the thickness of the top P-type epitaxial layer ranges from 3 μm to 10 μm.

8. The integrated multi-pin overvoltage protection structure according to claim 1, characterized in that, The doping concentration of PUBLn is controlled by different implantation doses and energy conditions, with the implantation dose range being 1e. 13 / cm 2 ~5e 15 / cm 2 The thermal diffusion process ranges from 900℃ to 1100℃, with a high-temperature thermal diffusion time of 30 to 120 minutes. The final doping concentration at the PUBLn-NBL interface ranges from 2e⁻¹. 16 / cm 3 ~5e 18 / cm 3 .

9. A method for manufacturing an integrated multi-pin overvoltage protection structure, characterized in that, The manufacturing method for producing an integrated multi-pin overvoltage protection structure according to any one of claims 1-8 includes the following steps: Step 1: Form a buffered P-type epitaxial layer on a heavily doped P-type substrate; Step 2: Perform PUBLn pattern photolithography on the buffer P-type epitaxial layer, and then perform B doping implantation under PUBLn conditions; Step 3: Grow a thin oxide layer and perform thermal diffusion; Step 4: Perform NBL patterning using BCD process on the buffer P-type epitaxial layer, followed by NBL doping implantation and thermal diffusion propagation. Step 5: Grow the top P-type epitaxial layer containing the BCD process surface device; Step 6: Perform deep N-well photolithography and deep N-well implantation using the BCD process, and thermal propulsion to bring the deep N-well into contact with the NBL; Step 7: Perform the pre-processing steps for surface device fabrication using the BCD process; Step 8: Perform the post-processing metallization of the BCD process, using metal to lead the cathodes of each different overvoltage clamping diode to the silicon surface. Step 9: After the BCD process is completed, perform back-side grinding. Step 10: Perform Ti / Ni / Ag back gold process to form a P-type heavily doped back lead, and connect the anode of each overvoltage clamping diode to the back common ground terminal.

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