Silicon-on-insulator substrate with enhanced charge trapping efficiency and high resistivity
By epitaxially depositing an epitaxial layer and a polycrystalline silicon charge trapping layer on a high resistivity single-crystal semiconductor substrate to form a multilayer structure, the problem of low charge trapping efficiency in the prior art is solved, and the performance and stability of radio frequency devices are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GLOBALWAFERS CO LTD
- Filing Date
- 2017-10-09
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies struggle to effectively trap charge reversal or accumulation layers when fabricating high resistivity silicon-on-insulator substrates, leading to parasitic power loss and device nonlinearity, which in turn affects the performance of radio frequency devices.
By epitaxially depositing an epitaxial layer on a high resistivity single-crystal semiconductor substrate and then depositing a polycrystalline silicon charge trapping layer thereon, followed by bonding it with a dielectric layer, a multilayer structure is formed to trap charges, thereby enhancing charge trapping efficiency.
It significantly improves the performance of radio frequency devices, reduces second and third harmonic distortion, solves the process and metrology challenges in the fabrication of high resistivity substrates, and avoids performance degradation caused by contaminant diffusion.
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Figure CN115763496B_ABST