Semiconductor structure and preparation method thereof

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductor, and aims to solve the technical problem of carrier mobility reduction in a transistor, which affects the performance of the transistor. The preparation method of the semiconductor structure comprises forming a gate dielectric layer on a substrate, the gate dielectric layer comprising an oxide layer and a high-K dielectric layer formed on the substrate in sequence; forming a gate stack on the high-K dielectric layer; etching part of the gate stack and the gate dielectric layer located outside the channel region to form a gate electrode opposite to the channel region. The preparation method of the semiconductor structure provided by the present disclosure forms an oxide layer between the high-K dielectric layer and the substrate. Since the interface state density between the oxide layer and the substrate is much smaller than the interface state density between the high-K dielectric layer and the substrate, the problem of carrier mobility degradation in the transistor can be solved, the carrier mobility of the transistor is improved, and the performance of the transistor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the size of transistors decreases, the overall size of the gate structure of the transistor also continues to decrease, causing the channel to become shorter and causing a strong short channel effect, which in turn leads to leakage current problems.

[0003] To this end, related technologies use high-K dielectrics instead of silicon oxide as the gate dielectric layer of the gate structure to reduce leakage current. However, the high interface state density between the high-K dielectric and the substrate reduces the carrier mobility in the transistor, affecting transistor performance. Summary of the Invention

[0004] In view of the above problems, embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure, which are used to improve carrier mobility in transistors and enhance transistor performance.

[0005] A first aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:

[0006] providing a substrate;

[0007] forming a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises an oxide layer and a high-K dielectric layer sequentially formed on the substrate;

[0008] forming a gate stack on the high-K dielectric layer;

[0009] Parts of the gate stack and the gate dielectric layer located outside the channel region are etched to form a gate opposite to the channel region.

[0010] The method for preparing a semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0011] The presently disclosed embodiment provides a method for preparing a semiconductor structure, in which a gate dielectric layer formed on a substrate includes an oxide layer and a high-K dielectric layer, i.e., an oxide layer is provided between the high-K dielectric layer and the substrate, and the oxide layer is used to isolate the high-K dielectric layer from the substrate. Since the interface state density between the oxide layer and the substrate is much lower than the interface state density between the high-K dielectric layer and the substrate, the method can solve the problem of carrier mobility degradation in transistors, improve the carrier mobility of transistors, and thereby improve the performance of transistors.

[0012] In the method for preparing the semiconductor structure as described above, providing a substrate includes: forming a first doping region and a second doping region in the substrate, wherein the first doping region and the second doping region have opposite doping types.

[0013] The method for preparing the semiconductor structure as described above, before the step of forming the gate dielectric layer on the substrate, further comprises: forming a silicon germanium layer on the surface of the first doped region.

[0014] In the method for preparing the semiconductor structure as described above, the step of forming the gate dielectric layer on the substrate includes:

[0015] forming a first oxide layer on a surface of the silicon germanium layer, wherein the first oxide layer covers a portion of the silicon germanium layer and is opposite to the channel region;

[0016] A second oxide layer is formed on the entire surface of the second doping region.

[0017] In the method for preparing the semiconductor structure as described above, the step of forming the first oxide layer on the surface of the silicon germanium layer comprises:

[0018] forming a first silicon-containing layer on a surface of the silicon germanium layer;

[0019] forming a first photoresist layer on a surface of the first silicon-containing layer outside the channel region, and exposing the first silicon-containing layer above the channel region;

[0020] Thermally oxidizing the exposed first silicon-containing layer to form the first oxide layer.

[0021] In the method for preparing the semiconductor structure as described above, the step of forming the second oxide layer on the surface of the second doped region includes:

[0022] forming a second silicon-containing layer on a surface of the second doped region;

[0023] The second silicon-containing layer is thermally oxidized to form the second oxide layer.

[0024] The method for preparing the semiconductor structure as described above, wherein the first silicon-containing layer is formed on the surface of the silicon-germanium layer, and the second silicon-containing layer is formed on the surface of the second doped region at the same time;

[0025] The exposed first silicon-containing layer is thermally oxidized while the second silicon-containing layer is thermally oxidized to form the second oxide layer.

[0026] In the above-mentioned method for preparing a semiconductor structure, the first silicon-containing layer and the second silicon-containing layer are made of the same material, and the material is at least one of amorphous silicon, single crystal silicon and polycrystalline silicon.

[0027] In the method for preparing the semiconductor structure as described above, the step of forming the gate stack on the high-K dielectric layer includes:

[0028] forming a first work function layer on the high-K dielectric layer in the first doped region;

[0029] forming a second work function layer on the high-K dielectric layer in the second doping region;

[0030] forming a third work function layer and a fourth work function layer on the first work function layer and the second work function layer, respectively, wherein the third work function layer is located on the first work function layer, and the fourth work function layer is located on the second work function layer;

[0031] A conductive metal layer and an isolation layer are sequentially formed on the third work function layer and the fourth work function layer respectively.

[0032] In the method for manufacturing the semiconductor structure as described above, the step of forming the gate opposite to the channel region includes:

[0033] forming a second photoresist layer on a surface of the gate stack corresponding to the first doping region and the second doping region, wherein the second photoresist layer is opposite to the channel region;

[0034] The gate stack, the high-K dielectric layer, the first silicon-containing layer, and the second oxide layer outside the channel region are removed by etching.

[0035] The method for preparing the semiconductor structure as described above controls the etching selectivity of the first silicon-containing layer and the second oxide layer to simultaneously complete the etching of the gate stack and the gate dielectric layer corresponding to the first doped region and the second doped region.

[0036] In this configuration, the etching rates of the first silicon-containing layer and the second oxide layer are balanced by controlling the etching selectivity of the first silicon-containing layer and the second oxide layer. For example, the first doped region is N-type doped to form a PMOS transistor, and the second doped region is P-type doped to form an NMOS transistor.

[0037] Since the overall thickness of the gate stack and gate dielectric layer corresponding to the PMOS transistor is greater than the overall thickness of the gate stack and gate dielectric layer corresponding to the NMOS transistor, the etching rate of the first silicon-containing layer can be controlled to be greater than the etching rate of the second oxide layer, so that when the etching of the gate dielectric layer corresponding to the PMOS transistor is completed, the etching of the gate dielectric layer corresponding to the NMOS transistor is also completed, thereby preventing the gate dielectric layer of the PMOS transistor from having a wide bottom, thereby affecting the threshold voltage of the PMOS transistor.

[0038] A second aspect of an embodiment of the present disclosure provides a semiconductor structure, comprising a substrate and a gate; the gate is located on the upper surface of the substrate and opposite to the channel region; the gate comprises a gate dielectric layer and a gate stack arranged in sequence, the gate dielectric layer comprises an oxide layer and a high-K dielectric layer, the oxide layer is arranged between the high-K dielectric layer and the substrate; the gate stack is located on the side of the high-K dielectric layer facing away from the substrate.

[0039] The advantages of the semiconductor structure provided by the embodiment of the present disclosure are the same as the advantages of the method for preparing the semiconductor structure described above, and will not be repeated here.

[0040] In the method for preparing the semiconductor structure as described above, the substrate includes a first doping region and a second doping region, and the doping type of the first doping region is opposite to the doping type of the second doping region.

[0041] The method for preparing the semiconductor structure as described above further includes: a silicon germanium layer located in the first doping region, wherein the silicon germanium layer is located between the oxide layer and the substrate.

[0042] In the above-described method for preparing a semiconductor structure, the thickness of the gate stack located above the first doping region is greater than the thickness of the gate stack located above the second doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 Schematic diagram of the process for preparing the semiconductor structure provided in the embodiment of the present disclosure Figure 1 ;

[0045] Figure 2-Figure 5 for Figure 1 Schematic diagram of the structure corresponding to each step shown;

[0046] Figure 6 Schematic diagram of the process for preparing the semiconductor structure provided in the embodiment of the present disclosure Figure 2 ;

[0047] Figure 7-Figure 15 for Figure 6 Schematic diagram of the structure corresponding to each step shown.

[0048] Description of reference numerals:

[0049] 10-substrate;

[0050] 10a-first doped region; 10b-second doped region; 10c-silicon germanium layer;

[0051] 20-gate dielectric layer;

[0052] 21- oxide layer; 21a- first oxide layer; 21b- second oxide layer;

[0053] 22-high-K dielectric layer;

[0054] 22a-first high-K dielectric layer; 22b-second high-K dielectric layer;

[0055] 30-gate stack;

[0056] 31a-first work function layer; 31b-second work function layer;

[0057] 32a-third work function layer; 32b-fourth work function layer;

[0058] 33a-first conductive metal layer; 33b-second conductive metal layer;

[0059] 34a-first isolation layer; 34b-second isolation layer;

[0060] 41-first silicon-containing layer; 42-second silicon-containing layer;

[0061] 50-first photoresist layer;

[0062] 60-Second photoresist layer. DETAILED DESCRIPTION

[0063] As the feature size of semiconductor devices shrinks, the various parameters of transistors should theoretically shrink exponentially. However, after the operating voltage is reduced to a certain extent, it cannot be further reduced. Since the physical thickness of the gate is still shrinking, the source-drain electric field penetrates the channel region, causing a strong short channel effect, serious degradation of device performance, and an increase in leakage current. The most widely used is the constant electric field rule. According to this rule, the electric field and the feature size decrease at the same ratio Y, while the charge density increases at the same ratio Y, keeping the electric field unchanged for small and large devices. This is a big reliability problem, which also leads to the use of high-K dielectrics as gate dielectrics to reduce leakage current after the device feature size reaches about 40nm. The biggest difficulty currently faced is the interface characteristics between the high-K dielectric and the substrate. The interface defect density between the high-K dielectric and the substrate should be low. The interface state density between SiO2 and the Si substrate is usually considered to be 2*10 10 cm -2 eV -1, while the interface state density between most high-K materials and Si substrates is around 10 11 ~10 12 cm -2 eV -1 , which is much larger than the interface state density between SiO2 and Si. These interface states not only cause the flat-band voltage to drift, but also degrade the carrier mobility in MOSFETs.

[0064] In traditional planar processes, to further enhance transistor performance, the use of substrate materials with higher mobility is a key research focus. Compared to traditional Si substrates, SiGe materials utilize bandgap engineering to tailor the semiconductor bandgap, enabling Si to improve device performance without requiring device size reduction. The introduction of a small amount of Ge into Si provides greater design freedom for SiGe devices, resulting in a significant improvement in mobility compared to pure Si, significantly enhancing SiGe device performance.

[0065] As described in the background technology, transistors often use high-K dielectrics as the gate dielectric layer of the gate structure to reduce the leakage current of the transistor; however, the carrier mobility of the above-mentioned transistors degrades, resulting in a decrease in the mobility of the transistor, affecting the performance of the transistor. The inventors have found that the reason for this problem is that the high-K dielectric is used as the gate dielectric layer, and the high-K dielectric layer is located in contact with the substrate surface. The interface state density between the two is large, which causes the carrier mobility in the transistor to decrease. Depositing high-K dielectrics on the SiGe interface will cause a high interface state density. The interface state density of traditional Si-based processes is between 2*10 10 cm -2 eV -1 The state density of the high-K / SiGe interface directly deposited with high-K dielectrics reaches 10 13 cm -2 eV -1 This results in a significant decrease in the carrier mobility in the channel.

[0066] In response to the above-mentioned problems when using high-K dielectrics, a feasible solution in the related art is to form an oxide layer rich in SiO2 at the interface to serve as the interface layer. However, when SiGe and high-K dielectrics are used in MOS tubes at the same time, firstly, since the contact interface between SiGe and SiO2 is not the contact interface between pure Si and SiO2, the stability of its interface properties is not as good as that of the contact interface between pure Si and SiO2; secondly, the Ge element will form an oxide GeO2 with very poor properties at the interface. x ,GeO x The dielectric constant of GeO is relatively small, and x The properties of GeO are unstable. xIt has a very low boiling point and will diffuse in high-K media when the temperature is higher than 400 degrees Celsius, thereby affecting the equivalent oxide layer thickness and interface state.

[0067] Furthermore, in actual device manufacturing, PMOS and NMOS are typically fabricated together for cost considerations. However, due to differences in the thickness of the corresponding stacks for PMOS and NMOS, the PMOS gate footing problem can occur due to loading effects during manufacturing. Gate footing changes the actual control width of the gate, causing a shift in the control gate threshold voltage and resulting in a loss in device performance.

[0068] To this end, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can not only effectively reduce the interface state density between the high-K material and the substrate, but also solve the gate footing problem that exists in the PMOS manufacturing process. By forming an oxide layer between the high-K dielectric layer and the substrate, for example, forming a silicon oxide layer between the substrate and the high-K dielectric layer, since the interface state density between the oxide layer and the substrate is much lower than the interface state density between the high-K dielectric layer and the substrate, it can solve the problem of carrier mobility degradation in the transistor, improve the carrier mobility of the transistor, and thus improve the performance of the transistor.

[0069] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0070] like Figure 1 As shown, the method for preparing a semiconductor provided by the embodiment of the present disclosure includes the following steps:

[0071] Step S100: providing a substrate 10 .

[0072] Specifically, the substrate 10 provided in the embodiments of the present disclosure may be a silicon substrate. For example, the substrate 10 is N-type doped to form an N-type substrate. The active region of the N-type substrate is further P-type doped to form a PMOS transistor having a source, a drain, and a P-type channel.

[0073] Alternatively, the substrate 10 is doped with P-type to form a P-type substrate, and the active region of the P-type substrate is further doped with N-type to form an NMOS transistor having a source, a drain, and an N-type channel.

[0074] Step S200 : forming a gate dielectric layer 20 on the substrate 10 . The gate dielectric layer 20 includes an oxide layer 21 and a high-K dielectric layer 22 sequentially formed on the substrate 10 .

[0075] Specifically, after the active region of the substrate 10 is doped to form a source and a drain, a gate dielectric layer 20 is formed on the surface of the substrate 10 , wherein the gate dielectric layer 20 includes an oxide layer 21 and a high-K dielectric layer 22 sequentially formed on the substrate 10 .

[0076] For example, the oxide layer 21 may be a silicon oxide layer, that is, a silicon-containing layer may be formed on the surface of the substrate 10. The silicon-containing layer may be at least one of polycrystalline silicon, single crystal silicon, or amorphous silicon. After the silicon-containing layer is formed on the surface of the substrate 10, the silicon-containing layer is thermally oxidized to form the oxide layer 21. Figure 2 As shown. Further, a high-K dielectric is deposited on the surface of the oxide layer 21 to form a high-K dielectric layer 22 covering the oxide layer 21. This structure is shown in FIG. Figure 3 shown.

[0077] Step S300: forming a gate stack 30 on the high-K dielectric layer. Figure 4 shown.

[0078] Specifically, the gate stack 30 in the embodiment of the present disclosure includes two work function layers, a conductive metal layer and an isolation layer stacked in sequence. Figure 15 In order to distinguish the two work function layers in the PMOS transistor from the two work function layers in the NMOS transistor, the two work function layers in the PMOS transistor can be defined as the first work function layer 31a and the third work function layer 32a, wherein the third work function layer 32a is formed on the first work function layer 31a; the two work function layers in the NMOS transistor are the second work function layer 31b and the fourth work function layer 32b, wherein the fourth work function layer 32b is formed on the second work function layer 31b.

[0079] In other words, a first work function layer 31a, a third work function layer 32a, a conductive metal layer, and an isolation layer are sequentially formed on the corresponding high-K dielectric layer 22 to form a gate stack 30 of a PMOS transistor. Alternatively, a second work function layer 31b, a fourth work function layer 32b, a conductive metal layer, and an isolation layer are sequentially formed on the corresponding high-K dielectric layer to form a gate stack 30 of an NMOS transistor.

[0080] Step S400: etching the gate stack 30 and the gate dielectric layer 20 located outside the channel region to form a gate opposite to the channel region. Figure 5 shown.

[0081] Specifically, after the above-mentioned gate stack 30 is formed on the gate dielectric layer 20, the gate stack 30 and the gate dielectric layer 20 located outside the channel region are etched and removed so that the gate stack 30 and the gate dielectric layer 20 remaining on the substrate 10 form a gate, and this gate is opposite to the channel region of the substrate 10, thereby forming a PMOS transistor or an NMOS transistor.

[0082] In the method for fabricating a semiconductor structure provided by the embodiments of the present disclosure, the gate dielectric layer 20 formed on the substrate 10 includes an oxide layer 21 and a high-K dielectric layer 22. Specifically, the oxide layer 21 is located between the high-K dielectric layer 22 and the substrate 10, and the oxide layer 21 is used to isolate the high-K dielectric layer 22 from the substrate 10. With this arrangement, because the interface state density between the oxide layer 21 and the substrate 10 is much lower than the interface state density between the high-K dielectric layer 22 and the substrate 10, the problem of carrier mobility degradation caused by the high interface state density between the substrate 10 and the high-K dielectric layer 22 can be solved, thereby improving the carrier mobility of the transistor and thereby enhancing the performance of the transistor.

[0083] In some embodiments, NMOS transistors and PMOS transistors are fabricated on the same substrate 10. Since the specific process steps required for NMOS transistors and PMOS transistors include the same process steps and different process steps, they can be fabricated simultaneously in the same process steps, thereby reducing the manufacturing process and time and saving costs.

[0084] PMOS transistors and NMOS transistors have structural differences, and these differences require different manufacturing processes. For example, the substrate 10 of the PMOS transistor has a silicon-germanium layer 10c to improve the carrier mobility of the PMOS transistor. Therefore, the substrate 10 of the PMOS transistor needs to be processed separately to form the silicon-germanium layer 10c inside or on the surface of the substrate 10 of the PMOS transistor.

[0085] Furthermore, the gate stack 30 of the PMOS transistor and the gate stack 30 of the NMOS transistor have different thicknesses. In the step of etching the portion of the gate stack 30 and the gate dielectric layer 20 located outside the channel region to form a gate opposite to the channel region, the etching rates of the two are different. Therefore, when the etching of the NMOS transistor is completed, the etching of the PMOS transistor is not completed, which results in a wide bottom of the gate dielectric layer 20 of the PMOS transistor and a gate footing problem, which affects the threshold voltage of the PMOS transistor.

[0086] To this end, in the method for preparing the semiconductor structure of the embodiment of the present disclosure, the structural layer of the gate dielectric layer 20 of the PMOS transistor located in the area outside the channel region is adjusted so that when the PMOS transistor and the NMOS transistor are etched simultaneously, the etching speeds of the two can be controlled so that the two can be completed synchronously.

[0087] like Figure 6 As shown, the embodiment of the present disclosure takes the manufacture of an NMOS transistor and a PMOS transistor on the same substrate 10 as an example to introduce the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure.

[0088] The substrate 10 provided by the embodiment of the present disclosure includes a first doping region 10a and a second doping region 10b, which are arranged at intervals, wherein the first doping region 10a and the second doping region 10b have different doping types to form different types of substrates 10 in the region.

[0089] The above step S100 includes: performing N-type doping on the first doping region 10a to form an N-type substrate 10, and the first doping region 10a is used to form the above PMOS transistor; performing P-type doping on the second doping region 10b to form a P-type substrate 10, and the second doping region 10b is used to form an NMOS transistor. Figure 7 shown.

[0090] Furthermore, before executing step S200, a silicon germanium layer 10c needs to be formed on the surface of the first doped region 10a. Specifically, the silicon germanium layer 10c is epitaxially grown on the surface of the first doped region 10a, that is, the silicon germanium layer 10c is epitaxially grown on the surface of the silicon substrate 10 in an atmosphere containing Si and Ge, and the silicon germanium layer 10c covers the first doped region 10a. This structure is as shown in FIG. Figure 7 shown.

[0091] Step S200 : forming a gate dielectric layer 20 on the substrate 10 . This step includes: step S210 : forming an oxide layer 21 on the substrate 10 ; and step S220 : forming a high-K dielectric layer 22 on the oxide layer.

[0092] Step S210 : forming a first oxide layer 21 a on the surface of the silicon germanium layer 10 c , the first oxide layer 21 a covering a portion of the silicon germanium layer 10 c and opposite to the channel region; and forming a second oxide layer 21 b on the entire surface of the second doped region 10 b .

[0093] The step of forming the first oxide layer 21a on the surface of the silicon germanium layer 10c includes: first, forming a first silicon-containing layer 41 on the surface of the silicon germanium layer 10c. For example, a polycrystalline silicon layer, a single crystal silicon layer or an amorphous silicon layer is formed on the surface of the silicon germanium layer 10c, and the thickness of the first silicon-containing layer 41 is in the range of 0.5nm-1nm. Figure 8 shown.

[0094] Furthermore, a first photoresist layer 50 is formed on the surface of the first silicon-containing layer 41 outside the channel region, exposing the first silicon-containing layer 41 above the channel region.

[0095] For example, a layer of photoresist is deposited on the upper surface of the first silicon-containing layer 41, and after exposure, development, and etching, a first photoresist layer 50 is formed on the surface of the first silicon-containing layer 41; the first photoresist layer 50 is located outside the channel region, and the opening formed by the first photoresist layer 50 is opposite to the channel region, and the first silicon-containing layer 41 is exposed through the opening; the exposed portion of the first silicon-containing layer 41 is opposite to the channel region. This structure is as shown in FIG. Figure 9 shown.

[0096] Furthermore, the exposed first silicon-containing layer 41 is thermally oxidized to form a first oxide layer 21a. Specifically, the first silicon-containing layer 41 is oxidized based on a thermal oxidation process to form the first oxide layer 21a. For example, oxygen is introduced into the chamber of the machine, and the first silicon-containing layer 41 is oxidized at a high temperature in an oxygen-containing atmosphere to oxidize the portion of the first silicon-containing layer 41 exposed in the opening to form the first oxide layer 21a. The first oxide layer 21a can be a silicon oxide layer. This structure is as shown in FIG. Figure 10 shown.

[0097] The step of forming the second oxide layer 21b on the entire surface of the second doped region 10b includes: first, forming a second silicon-containing layer 42 on the surface of the second doped region 10b. For example, a polycrystalline silicon layer, a single crystal silicon layer, or an amorphous silicon layer is formed on the surface of the second doped region 10b, and the thickness of the second silicon-containing layer 42 is in the range of 0.5 nm to 1 nm.

[0098] It should be noted that, while the second silicon-containing layer 42 is formed on the surface of the second doped region 10b, the first silicon-containing layer 41 can be formed on the surface of the silicon germanium layer 10c, that is, these two processes can be performed simultaneously. Figure 8 shown.

[0099] Furthermore, the second silicon-containing layer 42 is thermally oxidized to form a second oxide layer 21b. Specifically, the second silicon-containing layer 42 is oxidized based on a thermal oxidation process to form the second oxide layer 21b. For example, oxygen is introduced into the chamber of the machine, and the second silicon-containing layer 42 is oxidized at a high temperature in an oxygen-containing atmosphere to oxidize the second silicon-containing layer 42 to form the second oxide layer 21b. The structure formed in this step is as follows: Figure 10 shown.

[0100] It should be noted that while the first silicon-containing layer 41 is being thermally oxidized, the second silicon-containing layer 42 can be thermally oxidized to form the second oxide layer 21 b ; that is, these two processes can be performed simultaneously. Furthermore, after forming the first oxide layer 21 a and before forming the first high-k dielectric layer 22 a on the first oxide layer 21 a , the first photoresist layer 50 on the first silicon-containing layer 41 needs to be removed.

[0101] The step S220 of forming the high-K dielectric layer 22 on the oxide layer 21 includes: forming a first high-K dielectric layer 22 a on the first oxide layer 21 a , and forming a second high-K dielectric layer 22 b on the second oxide layer 21 b .

[0102] Specifically, in the embodiment of the present disclosure, the first high-K dielectric layer 22a and the second high-K dielectric layer 22b are made of the same material, and a high-K dielectric can be deposited simultaneously on the first oxide layer 21a and the second oxide layer 21b to form the high-K dielectric layer 22. For example, HfSiOx is deposited simultaneously on the first oxide layer 21a and the second oxide layer 21b to form the first high-K dielectric layer 22a and the second high-K dielectric layer 22b, respectively, and the first high-K dielectric layer 22a covers the first oxide layer 21a, and the second high-K dielectric layer 22b covers the second oxide layer 21b. This structure is as shown in FIG. Figure 11 shown.

[0103] On the basis of the above embodiments, in the method for preparing a semiconductor structure provided by the embodiment of the present disclosure, step S300: forming a gate stack 30 on the high-K dielectric layer 22. Figure 12 shown.

[0104] Specifically, step S310 includes forming a first work function layer 31a on the high-K dielectric layer of the first doped region 10a. For example, multiple coating layers of TIN / AL / TIN / AL / TIN are deposited on the first high-K dielectric layer 22a to form the first work function layer 31a, with the first work function layer 31a covering the first high-K dielectric layer 22a. In the disclosed embodiments, the gate turn-on voltage can be adjusted by adjusting the number and ratio of the above coating layers.

[0105] Step S320: Forming a second work function layer 31b on the high-K dielectric layer in the second doped region 10b. For example, a TIN / AL coating is deposited on the second high-K dielectric layer 22b to form the second work function layer 31b, with the second work function layer 31b covering the second high-K dielectric layer 22b. Because the first work function layer 31a and the second work function layer 31b have different coating amounts, the first work function layer 31a of the PMOS transistor and the second work function layer 31b of the NMOS transistor have different thicknesses.

[0106] Furthermore, step S300 also includes step S330: forming a third work function layer 32a and a fourth work function layer 32b on the first work function layer 31a and the second work function layer 31b respectively, and the third work function layer 32a is located on the first work function layer 31a, and the fourth work function layer 32b is located on the second work function layer 31b.

[0107] Specifically, the third work function layer 32a and the fourth work function layer 32b are simultaneously formed on the first work function layer 31a and the second work function layer 31b, wherein the third work function layer 32a covers the first work function layer 31a, and the fourth work function layer 32b covers the second work function layer 31b.

[0108] For example, the material of the third work function layer 32a and the fourth work function layer 32b is polysilicon, that is, polysilicon (Ploy) is deposited simultaneously on the first work function layer 31a and the second work function layer 31b to form a third work function layer 32a covering the first work function layer 31a and a fourth work function layer 32b covering the second work function layer 31b, respectively.

[0109] After the third work function layer 32 a and the fourth work function layer 32 b are formed, step S340 is performed: a conductive metal layer and an isolation layer are sequentially formed on the third work function layer 32 a and the fourth work function layer 32 b , respectively.

[0110] Specifically, a first conductive metal layer 33a and a second conductive metal layer 33b are simultaneously formed on the third work function layer 32a and the fourth work function layer 32b, wherein the first conductive metal layer 33a covers the third work function layer 32a, and the second conductive metal layer 33b covers the fourth work function layer 32b.

[0111] For example, the conductive metal layer may be made of metal tungsten (W), that is, metal tungsten is deposited simultaneously on the third work function layer 32a and the fourth work function layer 32b to form the first conductive metal layer 33a and the second conductive metal layer 33b.

[0112] Furthermore, a first isolation layer 34a and a second isolation layer 34b are simultaneously formed on the first conductive metal layer 33a and the second conductive metal layer 33b, wherein the first isolation layer 34a covers the first conductive metal layer 33a, and the second isolation layer 34b covers the second conductive metal layer 33b.

[0113] For example, the material of the isolation layer can be silicon nitride (SIN), that is, silicon nitride is deposited on the first conductive metal layer 33a and the second conductive metal layer 33b at the same time to form the first conductive metal layer 33a and the second conductive metal layer 33b. Figure 12 shown.

[0114] On the basis of the above embodiments, in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, step S400: forming a gate opposite to the channel region, includes:

[0115] Step S410 : forming a second photoresist layer 60 on the surface of the gate stack 30 corresponding to the first doping region 10 a and the second doping region 10 b , with the second photoresist layer 60 facing the channel region.

[0116] Specifically, a layer of photoresist is deposited on the upper surface of the first isolation layer 34a and the second isolation layer 34b, and after exposure, development, and etching, a second photoresist layer 60 is formed on the surface of the first isolation layer 34a and the second isolation layer 34b, respectively. The second photoresist layer 60 is opposite to the channel region, and the first isolation layer 34a and the second isolation layer 34b located outside the channel region are exposed. This structure is as shown in FIG. Figure 13 shown.

[0117] Step S420 : etching and removing the gate stack 30 , the high-K dielectric layer, the first silicon-containing layer 41 and the second oxide layer 21 b outside the channel region.

[0118] Specifically, the second photoresist layer 60 is used to block the gate stack 30, the first high-K dielectric layer 22a, and the first oxide layer 21a, and the gate stack 30, the first high-K dielectric layer 22a, and the first silicon-containing layer 41 outside the channel region are vertically etched to remove the gate stack 30, the first high-K dielectric layer 22a, and the first silicon-containing layer 41 outside the channel region, and form a gate on the first doped region 10a.

[0119] Furthermore, the second photoresist layer 60 is used to shield the gate stack 30, the second high-K dielectric layer 22b, and the second oxide layer 21b, and the gate stack 30, the second high-K dielectric layer 22b, and the second oxide layer 21b located outside the channel region are vertically etched to remove the gate stack 30, the second high-K dielectric layer 22b, and the second oxide layer 21b located outside the channel region, and form a gate on the second doped region 10b.

[0120] Preferably, in the embodiment of the present disclosure, the gate stack 30 and the gate dielectric layer 20 located on the first doped region 10 a are etched while the gate stack 30 and the gate dielectric layer 20 located on the second doped region 10 b are also etched, that is, both are etched simultaneously.

[0121] Since the overall thickness of the gate stack 30 and the gate dielectric layer 20 on the first doped region 10a is greater than the overall thickness of the gate stack 30 and the gate dielectric layer 20 on the second doped region 10b, under the same etching conditions, after the gate dielectric layer 20 on the second doped region 10b has been completely etched, the gate dielectric layer 20 on the first doped region 10a is not completely etched.

[0122] Therefore, in the embodiment of the present disclosure, during the etching process, the etching selection ratio of the first silicon-containing layer 41 to the second oxide layer 21b is controlled to simultaneously complete the etching of the gate stack 30 and the gate dielectric layer 20 corresponding to the first doped region 10a and the second doped region 10b. Figure 14 shown.

[0123] For example, the etching rate of the first silicon-containing layer 41 in the embodiment of the present disclosure is greater than the etching rate of the second oxide layer 21b, so as to balance the etching rates of the gate dielectric layer 20 corresponding to the first doped region 10a and the second doped region 10b, so that when the etching of the gate dielectric layer 20 corresponding to the first doped region 10a is completed, the etching of the gate dielectric layer 20 corresponding to the second doped region 10b is also completed, thereby preventing the gate dielectric layer 20 of the first doped region 10a from being incompletely etched and having a wide bottom, thereby affecting the threshold voltage of the PMOS transistor.

[0124] It should be noted that after etching away the gate stack 30, the high-K dielectric layer, the first silicon-containing layer 41 and the second oxide layer 21b outside the channel region, the second photoresist layer 60 needs to be removed. Figure 15 shown.

[0125] like Figure 5 As shown, the semiconductor structure provided by the embodiment of the present disclosure includes a substrate 10 and a gate arranged on the substrate 10, the substrate 10 includes an active area, the active area is provided with a source and a drain, and a channel area is provided between the source and the drain.

[0126] The gate is disposed above the active region of the substrate 10, and is opposite the channel region. The gate comprises a gate dielectric layer 20 and a gate stack 30, which are sequentially disposed. The gate dielectric layer 20 comprises an oxide layer 21 and a high-K dielectric layer 22, with the oxide layer 21 located between the high-K dielectric layer 22 and the substrate 10. Furthermore, the gate stack 30 is disposed on the side of the high-K dielectric layer 22 away from the substrate 10, i.e., the gate stack 30 is disposed above the high-K dielectric layer.

[0127] In this configuration, the semiconductor structure provided by the embodiment of the present disclosure has an oxide layer 21 between the high-K dielectric layer 22 and the substrate 10. The oxide layer 21 is used to isolate the high-K dielectric layer 22 from the substrate 10. Since the interface state density between the oxide layer 21 and the substrate 10 is much smaller than the interface state density between the high-K dielectric layer 22 and the substrate 10, it can solve the problem of carrier mobility degradation in the transistor, improve the carrier mobility of the transistor, and thus improve the performance of the transistor.

[0128] Further, if Figure 15 As shown, the semiconductor structure provided by the embodiment of the present disclosure has a substrate 10 including a first doping region 10a and a second doping region 10b, the first doping region 10a and the second doping region 10b are arranged at intervals, and the doping types of the first doping region 10a and the second doping region 10b are opposite.

[0129] For example, the first doped region 10a is N-type doped to form an N-type substrate 10, and a gate is set on the N-type substrate 10 to form a PMOS transistor; the second doped region 10b is P-type doped to form a P-type substrate 10, and a gate is set on the P-type substrate 10 to form an NMOS transistor.

[0130] Furthermore, in order to improve the carrier mobility of the PMOS transistor, a silicon germanium layer 10c is provided in the first doped region 10a in the embodiment of the present disclosure, wherein the silicon germanium layer 10c can be provided in the first doped region 10a, or the silicon germanium layer 10c can be provided on the upper surface of the first doped region 10a, that is, the surface of the above-mentioned N-type substrate 10 is provided with the silicon germanium layer 10c, and the silicon germanium layer 10c covers the N-type substrate 10, or the silicon germanium layer 10c is provided in the N-type substrate 10, which is located below the channel region.

[0131] Based on the above embodiment, in the disclosed embodiment, the thickness of the gate stack 30 above the first doped region 10a is greater than the thickness of the gate stack 30 above the second doped region 10b. The gate stack 30 above the first doped region 10a includes a first work function layer 31a, a third work function layer 32a, a first conductive metal layer 33a, and a first isolation layer 34a, which are sequentially stacked on the first high-K dielectric layer 22a. The gate stack 30 above the second doped region 10b includes a second work function layer 31b, a fourth work function layer 32b, a second conductive metal layer 33b, and a second isolation layer 34b, which are sequentially stacked on the second high-K dielectric layer 22b.

[0132] The first work function layer 31a comprises a plurality of coating layers of TIN / AL / TIN / AL / TIN, and the second work function layer 31b comprises a TIN / AL coating. Therefore, the gate stack 30 of the PMOS transistor and the gate stack 30 of the NMOS transistor have different thicknesses. With this arrangement, the gate threshold voltage can be adjusted, for example, lowered, by adjusting the number and ratio of the coating layers in the embodiments of the present disclosure.

[0133] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0134] Throughout this specification, references to "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: providing a substrate, forming a first doped region and a second doped region in the substrate; forming a silicon germanium layer on a surface of the first doped region; forming a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises an oxide layer and a high-K dielectric layer sequentially formed on the substrate; forming a gate stack on the high-K dielectric layer; Etching portions of the gate stack and the gate dielectric layer outside the channel region to form a gate opposite to the channel region; The step of forming the gate dielectric layer on the substrate includes forming a first oxide layer on the surface of the silicon germanium layer and forming a second oxide layer on the entire surface of the second doped region; the step of forming the first oxide layer on the surface of the silicon germanium layer includes: forming a first silicon-containing layer on the surface of the silicon germanium layer; forming a first photoresist layer on the surface of the first silicon-containing layer outside the channel region and exposing the first silicon-containing layer above the channel region; and thermally oxidizing the exposed first silicon-containing layer to form the first oxide layer; In the step of forming a gate opposite to the channel region, the etching selection ratio of the first silicon-containing layer and the second oxide layer is controlled to simultaneously complete the etching of the gate stack and the gate dielectric layer corresponding to the first doped region and the second doped region.

2. The preparation method according to claim 1, characterized in that The first doping region and the second doping region have opposite doping types.

3. The preparation method according to claim 1, characterized in that The step of forming the gate dielectric layer on the substrate comprises: forming a first oxide layer on a surface of the silicon germanium layer, wherein the first oxide layer covers a portion of the silicon germanium layer and is opposite to the channel region; A second oxide layer is formed on the entire surface of the second doping region.

4. The preparation method according to claim 1, characterized in that The step of forming the second oxide layer on the surface of the second doped region comprises: forming a second silicon-containing layer on a surface of the second doped region; The second silicon-containing layer is thermally oxidized to form the second oxide layer.

5. The preparation method according to claim 4, characterized in that while forming the first silicon-containing layer on the surface of the silicon-germanium layer, forming the second silicon-containing layer on the surface of the second doped region; The exposed first silicon-containing layer is thermally oxidized while the second silicon-containing layer is thermally oxidized to form the second oxide layer.

6. The preparation method according to claim 5, characterized in that The first silicon-containing layer and the second silicon-containing layer are made of the same material, and the material is at least one of amorphous silicon, single crystal silicon and polycrystalline silicon.

7. The preparation method according to any one of claims 1 to 6, characterized in that The step of forming the gate stack on the high-K dielectric layer comprises: forming a first work function layer on the high-K dielectric layer in the first doped region; forming a second work function layer on the high-K dielectric layer in the second doping region; forming a third work function layer and a fourth work function layer on the first work function layer and the second work function layer, respectively, wherein the third work function layer is located on the first work function layer, and the fourth work function layer is located on the second work function layer; A conductive metal layer and an isolation layer are sequentially formed on the third work function layer and the fourth work function layer respectively.

8. The preparation method according to claim 7, characterized in that The step of forming the gate opposite to the channel region includes: forming a second photoresist layer on a surface of the gate stack corresponding to the first doping region and the second doping region, wherein the second photoresist layer is opposite to the channel region; The gate stack, the high-K dielectric layer, the first silicon-containing layer, and the second oxide layer outside the channel region are removed by etching.

9. A semiconductor structure, characterized in that including a substrate and a gate; The gate is located on the upper surface of the substrate and is opposite to the channel region; The gate includes a gate dielectric layer and a gate stack arranged in sequence, the gate dielectric layer includes an oxide layer and a high-K dielectric layer, and the oxide layer is arranged between the high-K dielectric layer and the substrate; The gate stack is located on a side of the high-K dielectric layer facing away from the substrate, and the semiconductor structure is prepared by the preparation method according to claim 1.

10. The semiconductor structure according to claim 9, wherein: The substrate includes a first doping region and a second doping region, wherein a doping type of the first doping region is opposite to a doping type of the second doping region.

11. The semiconductor structure according to claim 9, wherein: Also includes: A silicon germanium layer is located in the first doping region, and the silicon germanium layer is located between the oxide layer and the substrate.

12. The semiconductor structure according to claim 9, wherein: The thickness of the gate stack located above the first doping region is greater than the thickness of the gate stack located above the second doping region.

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