Embedded germanium silicon device and method of fabrication thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CENT CO LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-07-24
Smart Images
Figure CN115763564B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and to an integrated circuit manufacturing technology based on SiGe. Background Technology
[0002] With the miniaturization of Complementary Metal Oxide Semiconductor (CMOS) technology, down to nodes below 65 / 45nm, component sizes are becoming increasingly smaller. Transistor gate lengths are shorter than ever before, leading to reduced carrier mobility and consequently, decreased on-state current and performance degradation. Improving CMOS device performance solely by proportionally shrinking the gate dielectric layer is increasingly limited by physical and technological constraints. After reaching 45nm and below, numerous new processes and technologies have been applied to integrated circuit manufacturing to enhance semiconductor device performance. Among these, embedded germanium-silicon technology is an effective mechanism for improving carrier mobility and is widely used to enhance PMOS device performance. It increases hole mobility in PMOS by generating uniaxial compressive stress in the channel, thereby improving the transistor's current drive capability.
[0003] Typically, the formation process of embedded germanium-silicon source / drain regions involves etching grooves on a silicon substrate, selectively epitaxially growing SiGe layers within the grooves as source / drain regions, and utilizing the lattice constant mismatch between SiGe and Si to generate lateral compressive stress in the channel, thereby improving hole mobility in the channel. However, since the SiGe layer is formed through heteroepitaxial processes, the quality of the epitaxial layer is affected as the thickness of the heteroepitaxial layer increases, which can lead to instability issues in the resulting device. On the other hand, as device feature sizes advance to 45 / 40nm or even 32 / 28nm, the distance between channels becomes increasingly shorter, and the excessive diffusion of dopants in the germanium-silicon layers of the source / drain regions between channels is gradually becoming a challenging problem.
[0004] Therefore, how to improve the quality of embedded germanium-silicon devices has become one of the important problems that urgently need to be solved by those skilled in the art. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an embedded germanium-silicon device and its fabrication method, which solves the problems of device stability caused by the application of embedded germanium-silicon technology to CMOS devices with technology nodes of 45nm and below, and the impact of source / drain region dopant diffusion into the channel region on device switching characteristics.
[0006] To achieve the above and other related objectives, the present invention provides an embedded germanium-silicon device, comprising:
[0007] A semiconductor substrate, on which a gate structure is disposed, and trenches are disposed on both sides of the semiconductor substrate adjacent to the gate structure;
[0008] A germanium-silicon epitaxial structure is disposed within the trench to form a source region and a drain region. The germanium-silicon epitaxial structure includes a buffer layer, an intermediate layer, and a capping layer stacked sequentially. The buffer layer includes an undoped germanium-silicon layer and a doped germanium-silicon layer stacked sequentially from the inner surface of the trench. The undoped germanium-silicon layer and the doped germanium-silicon layer are stacked alternately in two or more cycles.
[0009] Optionally, the total thickness of the buffer layer is between Between these layers, the thickness ratio of the undoped germanium-silicon layer to the doped germanium-silicon layer is not less than 2:1.
[0010] Optionally, the semiconductor substrate is an N-type silicon substrate, the intermediate layer includes a heavily doped germanium-silicon epitaxial layer, and the capping layer is a silicon capping layer.
[0011] Optionally, the buffer layer has a germanium content of 15% to 30% by mass.
[0012] Optionally, the doped germanium-silicon layer and the heavily doped germanium-silicon epitaxial layer contain boron doping, and the average doping concentration of all doped germanium-silicon layers in the buffer layer is between 1E19cm⁻¹. -3 ~1E20 cm -3 between.
[0013] This invention also provides a method for fabricating an embedded germanium-silicon device, comprising the following steps:
[0014] A semiconductor substrate is provided, wherein a gate structure is formed on the surface of the semiconductor substrate, and trenches are provided on both sides of the semiconductor substrate adjacent to the gate structure.
[0015] A buffer layer is formed on the inner surface of the trench. The step of forming the buffer layer includes selectively epitaxially growing an undoped germanium-silicon layer and a doped germanium-silicon layer, wherein the undoped germanium-silicon layer and the doped germanium-silicon layer are stacked alternately in two or more cycles.
[0016] An intermediate layer and a capping layer are epitaxially grown sequentially on the surface of the buffer layer within the trench. The buffer layer, the intermediate layer, and the capping layer are stacked sequentially to form a germanium-silicon epitaxial structure to be formed as the source region and the drain region.
[0017] Optionally, the step of forming the buffer layer includes: selectively epitaxially growing a first germanium-silicon epitaxial layer at the bottom of the trench to form an undoped germanium-silicon layer; subsequently, selectively epitaxially growing a second germanium-silicon epitaxial layer while in-situ doping the second germanium-silicon epitaxial layer to form a doped germanium-silicon layer.
[0018] Optionally, the trench is selected as a sigma trench, which is formed by selective etching to create a recess extending downward toward the gate structure.
[0019] Optionally, during the selective epitaxial growth of the buffer layer, the undoped germanium-silicon layer and the doped germanium-silicon layer are also alternately grown in the recesses of the sigma trench, so that the buffer layer has a gradient increasing germanium content in the direction in which the distance between the recess and the gate structure decreases.
[0020] Optionally, the step of forming the buffer layer further includes: performing the epitaxial growth of the undoped germanium-silicon layer and the doped germanium-silicon layer up to N times, wherein the doped germanium-silicon layer contains boron doping, wherein the doped germanium-silicon layer formed in the Nth time has a greater boron doping concentration than the doped germanium-silicon layer formed in the (N-1)th time, and N is a natural number not less than 2.
[0021] Optionally, the fabrication method further includes: in-situ doping of the buffer layer while simultaneously activating the doped germanium-silicon layer in situ, wherein a portion of the dopant in the doped germanium-silicon layer diffuses to both sides and enters the undoped germanium-silicon layer.
[0022] As described above, the embedded germanium-silicon device and its fabrication method of the present invention have the following beneficial effects:
[0023] This invention relates to embedded germanium-silicon technology. By setting a germanium-silicon epitaxial structure in the source and drain regions, the germanium-silicon epitaxial structure includes alternating layers of undoped and doped germanium-silicon layers as a buffer layer. This multi-layered germanium-silicon epitaxial layer significantly increases the stress on the channel and enables high-quality SiGe crystals in the source and drain regions. Simultaneously, it prevents dopant diffusion from the source and drain regions into the channel, thus affecting the device's switching characteristics. Furthermore, by configuring the buffer layer as a multi-layered germanium-silicon epitaxial layer, the number of stacking cycles can be increased or decreased as needed to ensure that the thickness of the intermediate layer remains below a critical thickness, greatly reducing the probability of defect generation. In particular, it avoids stacking fault accumulation in the germanium-silicon epitaxial layer caused by increased Ge content in the intermediate layer, thereby improving device performance. Attached Figure Description
[0024] Figure 1 The graph shows the change in boron concentration before and after heat treatment in an existing embedded germanium-silicon epitaxial structure.
[0025] Figure 2 The diagram shown is a structural schematic obtained from step S1 of the method for fabricating an embedded germanium-silicon device according to an embodiment of the present invention.
[0026] Figures 3A-3BThe diagram shown is a structural schematic obtained from step S2 of the method for fabricating an embedded germanium-silicon device according to an embodiment of the present invention; wherein, Figure 3B Displayed as Figure 3A A magnified view of a portion of the buffer layer shown.
[0027] Figures 4A-4B The diagram shown is a structural schematic obtained in step S3 of the fabrication method of the embedded germanium-silicon device according to an embodiment of the present invention; wherein, Figure 4B Displayed as Figure 4A A magnified view of a portion of the buffer layer shown.
[0028] Figure 5 The graph shown is a curve illustrating the change in boron concentration after activation in the germanium-silicon epitaxial structure of the embedded germanium-silicon device according to an embodiment of the present invention.
[0029] Component designation explanation
[0030] Steps S1 to S2 100 Semiconductor Substrate
[0031] 200 grid structure
[0032] 300 groove
[0033] L1 liner layer
[0034] L2 Intermediate Layer
[0035] L3 cap layer
[0036] L1a Undoped germanium-silicon layer
[0037] L1b-doped germanium-silicon layer
[0038] 232 First side wall
[0039] 234 Second side wall
[0040] 236 Hard mask layer Detailed Implementation
[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0043] Typically, in germanium-silicon embedded source / drain structures, the probability of defects in the thicker epitaxial host layer increases dramatically due to germanium's higher lattice constant than silicon. Defects such as dislocations can lead to stress relaxation, reduced compressive stress on the channel, decreased hole mobility, and deteriorated device performance. This invention addresses this by placing a germanium-silicon epitaxial structure within a trench in a semiconductor substrate and using alternating layers of undoped and doped germanium-silicon layers as buffer layers. This multilayered germanium-silicon epitaxial structure can achieve high-quality SiGe crystals in the source / drain regions.
[0044] On the other hand, to reduce the resistance of the source and drain regions, the germanium-silicon epitaxial layer needs to be doped. However, dopants such as boron have a higher diffusion rate in pure silicon than in the germanium-silicon epitaxial layer. Therefore, the reduction in gate size makes the excessive diffusion problem of the germanium-silicon epitaxial layer into the channel in the source and drain regions more significant, affecting the switching characteristics of the device and even exacerbating the short-channel effect. Figure 1 As shown, the boron concentration change curve of existing source / drain germanium-silicon epitaxial structures becomes steep after heat treatment, which easily leads to lateral diffusion of boron between channels. This invention uses alternating layers of undoped and doped germanium-silicon layers as buffer layers. Pre-growing undoped germanium-silicon layers on the sidewalls of the trench can prevent dopant from diffusing downwards towards the gate structure. Undoped germanium-silicon layers inserted between adjacent doped germanium-silicon layers can impede interlayer diffusion of dopant, further reducing the risk of dopant diffusion between channels.
[0045] Subsequently, in combination Figures 2-5 The embedded germanium-silicon device and its fabrication method of the present invention are described in detail.
[0046] First, please refer to Figures 4A-4B This embodiment provides an embedded germanium-silicon device, including: a semiconductor substrate 100, a gate structure 200 disposed on the semiconductor substrate 100, trenches 300 and germanium-silicon epitaxial structures formed on both sides of the gate structure 200 in the semiconductor substrate 100, the germanium-silicon epitaxial structures disposed in the trenches 300 to form source and drain regions, the germanium-silicon epitaxial structures including a buffer layer L1, an intermediate layer L2 and a capping layer L3, the buffer layer L1 including an undoped germanium-silicon layer L1a and a doped germanium-silicon layer L1b sequentially stacked from the inner surface of the trench, the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b being stacked alternately in two or more cycles.
[0047] Specifically, the semiconductor substrate 100 may be a silicon substrate, for example, an N-type silicon substrate with a surface crystal orientation of (110). Specifically, the gate structure 200 includes a gate electrode layer disposed on the semiconductor substrate 100 and a gate dielectric layer located between the semiconductor substrate 100 and the gate electrode layer. The material of the gate electrode layer is polycrystalline silicon, and the material of the gate dielectric layer is silicon oxide, hafnium oxide, aluminum oxide, silicon oxynitride, or a high-K dielectric material.
[0048] As an example, the trench 300 can be a sigma trench, a U-shaped trench, or a trench of similar shape. In this embodiment, the trench 300 is sigma-shaped and has a recess formed in the semiconductor substrate 100 below the gate structure 200.
[0049] like Figures 4A-4B As shown, the buffer layer L1 is selectively grown in the recess and bottom of the trench 300, and the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b are stacked alternately in two or more cycles in the recess and bottom of the trench 300.
[0050] As an example, the buffer layer has a germanium content between 15% and 30% by molar amount. In some examples, each undoped germanium-silicon layer L1a within the recess of the trench 300 has a fixed germanium content, and each doped germanium-silicon layer L1b has a fixed germanium content, while adjacent undoped germanium-silicon layers L1a and doped germanium-silicon layers L1b may have the same or different germanium contents. In other examples, the undoped germanium-silicon layers L1a and doped germanium-silicon layers L1b alternately arranged in sequence within the recess of the trench 300 have germanium contents that increase or decrease in a gradient, such that the doped germanium-silicon layer L1b adjacent to the intermediate layer L2 has a germanium content close to that of the intermediate layer L2, thereby avoiding abrupt changes in germanium concentration at the interface between the buffer layer L1 and the intermediate layer L2. In particular, the intermediate layer L2 is selected as a germanium-silicon epitaxial layer with high Ge content. The undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b are alternately arranged in sequence, with the germanium concentration increasing in a gradient to close to that of the intermediate layer L2. This can increase the lateral stress of the source-drain region embedded germanium-silicon structure on the channel, which is beneficial to improving the quality of the germanium-silicon epitaxial structure.
[0051] As an example, the total thickness of the buffer layer L1 is between In this embodiment, the average doping concentration of all doped germanium-silicon layers in the buffer layer is between 1E19cm⁻¹. -3 ~1E20cm -3 Between these layers, the doping concentration of each doped germanium-silicon layer can be adjusted according to the alternating stacking period of undoped and doped germanium-silicon layers and the required device performance.
[0052] like Figure 4A As shown, the germanium-silicon epitaxial structure includes a buffer layer L1, an intermediate layer L2, and a capping layer L3 stacked sequentially. Specifically, the intermediate layer L2 may include a heavily doped germanium-silicon epitaxial layer, and the capping layer L3 is selected as a silicon capping layer. The doped germanium-silicon layer L1b and the heavily doped germanium-silicon epitaxial layer contain boron doping. Compared to the conventionally used germanium-silicon capping layer, the silicon capping layer can increase the critical thickness of the germanium-silicon intermediate layer, increase the process window of the buffer layer, and simplify the subsequent process of forming metal silicides on the substrate surface.
[0053] This embodiment also provides a method for fabricating an embedded germanium-silicon device, including the following steps:
[0054] S1: A semiconductor substrate is provided, wherein a gate structure and trenches located on both sides of the gate structure are formed on the surface of the semiconductor substrate;
[0055] S2: A buffer layer is formed on the inner surface of the trench;
[0056] S3: An intermediate layer and a capping layer are sequentially grown on the surface of the buffer layer within the trench.
[0057] The embedded germanium-silicon device of the present invention can be fabricated using the fabrication method described herein. The specific structure of the fabrication method, as well as the features and positional relationships of each structure, can be referred to the description of the embedded germanium-silicon device in this embodiment.
[0058] It should be noted that the order of each step in the preparation method described in the claims is not specifically defined, and those skilled in the art can adjust the order of each process step according to the actual situation.
[0059] Please see Figure 2 The fabrication method of the embedded germanium-silicon device begins in step S1: a semiconductor substrate 100 is provided, on which a gate structure 200 is formed. The gate structure 200 includes a gate electrode layer disposed on the semiconductor substrate 100 and a gate dielectric layer located between the semiconductor substrate 100 and the gate electrode layer. Specifically, the semiconductor substrate 100 may be a silicon substrate, for example, an N-type silicon substrate with a surface crystal orientation of (110). The material of the gate electrode layer is polycrystalline silicon, and the material of the gate dielectric layer is silicon oxide, hafnium oxide, aluminum oxide, silicon oxynitride, or a high-k dielectric material.
[0060] As an example, the gate structure 200 further includes: a hard mask layer 236 covering the top of the gate electrode layer 220, a first sidewall 232, and a second sidewall 234 surrounding the first sidewall 232, the first sidewall 232 and the second sidewall 234 being located on the surface of the semiconductor substrate 100, and the first sidewall 232 being formed around both sides of the gate structure 200. For example, the material of the hard mask layer 236 is silicon nitride.
[0061] See also Figure 2 Step S1 further includes forming a trench 300 in the semiconductor substrate 100, the trench 300 being located on both sides of the gate structure 200.
[0062] As an example, the trench 300 can be a sigma trench, a U-shaped trench, or a trench of similar shape. In this embodiment, a sigma trench is used. The steps for forming the sigma trench include: performing dry etching using the first sidewall 232, the second sidewall 234, and the hard mask layer 236 as a pattern mask to form an opening in the semiconductor substrate 100; subsequently, using the first sidewall 232, the second sidewall 234, and the hard mask layer 236 as a pattern mask, selectively etching the opening using wet etching to form a recess in the semiconductor substrate 100 below the second sidewall 234, thereby forming a sigma trench. Specifically, the selective etching process can be anisotropic wet etching, wherein the anisotropic wet etching has a faster etching rate in directions perpendicular to and parallel to the surface of the semiconductor substrate 100, while the etching rate is higher in directions perpendicular to and parallel to the surface of the semiconductor substrate 100. <111> The etching rate at the crystal plane is slower, causing the opening to expand into a sigma-type trench. For example, an alkaline etchant, such as tetramethylammonium hydroxide (TMAH), can be used to perform the selective etching process.
[0063] Then, see Figures 3A-3B Step S2: A buffer layer L1 is formed on the inner surface of the groove 300.
[0064] As an example, such as Figure 3B As shown, step S2 includes: selectively epitaxially growing an undoped germanium-silicon layer L1a and a doped germanium-silicon layer L1b on the inner surface of the trench 300, wherein the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b are stacked alternately in two or more cycles. That is, the step of selectively epitaxially growing the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b is performed N times, where N is a natural number not less than 2, so that the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b are arranged in multiple alternating cycles. This can significantly increase the stress on the channel and also help maintain the thickness of the subsequently formed intermediate layer below the critical thickness, thereby reducing the probability of defects caused by stacking fault accumulation.
[0065] As an example, the step of forming the buffer layer L1 further includes: selectively epitaxially growing a first germanium-silicon epitaxial layer at the bottom of the trench 300 to form an undoped germanium-silicon layer L1a; subsequently, selectively epitaxially growing a second germanium-silicon epitaxial layer while in-situ doping the second germanium-silicon epitaxial layer to form a doped germanium-silicon layer L1b.
[0066] In this embodiment, the trench 300 is a sigma-type trench, and during the selective epitaxial growth process, the undoped germanium-silicon layer and the doped germanium-silicon layer are alternately grown in the recesses of the sigma-type trench.
[0067] As an example, the buffer layer L1 has a germanium content between 15% and 30% by molar amount. In some examples, each undoped germanium-silicon layer L1a in the buffer layer L1 has a fixed germanium content, and each doped germanium-silicon layer L1b has a fixed germanium content, while the germanium content of the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b subsequently formed thereon may be the same or different. In other examples, the buffer layer L1 has a germanium content that increases or decreases in a gradient; that is, the undoped germanium-silicon layer formed in the Nth iteration has a germanium content greater than or less than that of the undoped germanium-silicon layer formed in the (N-1)th iteration, and the doped germanium-silicon layer formed in the Nth iteration has a germanium content greater than or less than that of the doped germanium-silicon layer formed in the (N-1)th iteration; preferably, the buffer layer L1 has a gradient increasing germanium content, such that the buffer layer L1 has a gradient increasing germanium content in the direction in which the spacing between the recess and the gate structure decreases, which is beneficial for further increasing the lateral stress on the channel.
[0068] As an example, the doped germanium-silicon layer L1b contains boron doping. The second germanium-silicon epitaxial layer can be selectively epitaxially grown using a precursor gas containing the doping gas, while simultaneously doping the second germanium-silicon epitaxial layer in situ. In this embodiment, the doping gas is borane (BH3). Specifically, the doped germanium-silicon layer formed in the Nth iteration has a higher boron doping concentration than the doped germanium-silicon layer formed in the (N-1)th iteration, where N is a natural number not less than 2. This results in a boron concentration distribution in each doped germanium-silicon layer L1b of the buffer layer L1 that gradually increases from the bottom of the trench 300 upwards and from the sidewalls inwards, to a desired concentration.
[0069] As an example, the total thickness of the buffer layer L1 is between Between them, the thicknesses of the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b can be adjusted according to actual needs.
[0070] Then, see Figures 4A-4B Step S3: An intermediate layer L2 and a capping layer L3 are sequentially epitaxially grown from the surface of the buffer layer L1 within the trench 300.
[0071] like Figure 4A As shown, the buffer layer L1, the intermediate layer L2, and the capping layer L3 are sequentially stacked to form a germanium-silicon epitaxial structure to be formed as the source and drain regions. Specifically, the intermediate layer L2 may include a heavily doped germanium-silicon epitaxial layer, and the capping layer L3 is selected as a silicon capping layer. Compared with the conventionally used germanium-silicon capping layer, the silicon capping layer can increase the critical thickness of the germanium-silicon intermediate layer, increase the process window of the buffer layer, and simplify the subsequent process of forming metal silicides on the substrate surface.
[0072] As an example, the intermediate layer L2 can be formed using a selective epitaxial process, whereby the intermediate layer L2 is selectively epitaxially grown from the surface of the buffer layer L1. The intermediate layer L2 is formed above the surface of the semiconductor substrate 100, or substantially flush with the surface of the semiconductor substrate 100. The buffer layer L1 can be configured to have a gradient increasing germanium content along the bottom of the trench 300 upwards and inwards along the sidewalls, to avoid abrupt changes in germanium concentration at the interface between the intermediate layer and the buffer layer, thereby obtaining a high-quality germanium-silicon embedded epitaxial layer.
[0073] As an example, the selective epitaxial process can be performed using a precursor gas containing a dopant gas, allowing in-situ doping to occur simultaneously with the selective epitaxial growth of the intermediate layer L2. For instance, the dopant gas can be borane (BH3). In this embodiment, the average doping concentration of all doped germanium-silicon layers in the buffer layer is between 1E19 cm⁻¹. -3 ~1E20cm -3 between.
[0074] As an example, the capping layer L3 can be selectively epitaxially grown on the intermediate layer L2, wherein the capping layer L3 can be a silicon capping layer L3, and in subsequent processes, the silicon capping layer L3 can form metal silicide to reduce the resulting source / drain resistance.
[0075] The fabrication method further includes: simultaneously in-situ doping the buffer layer L1 and in-situ activating the doped germanium-silicon layer L1b, wherein a portion of the dopant in the doped germanium-silicon layer L1b diffuses to both sides and crosses the interface into the undoped germanium-silicon layer L1a, thereby expanding the boundary of individual doped regions in the activated buffer layer, and each doped region has a thickness greater than that of the initially doped germanium-silicon layer L1b. Considering the diffusion effect of the dopant in the doped germanium-silicon layer L1b during the activation process, the undoped germanium-silicon layer L1a can have sufficient thickness to prevent the dopant from crossing the undoped germanium-silicon layer after heat treatment and / or activation, thus preventing the buffer layer L1 from becoming entirely doped, thereby preventing the dopant in the source / drain regions from diffusing into the channels and affecting the switching characteristics of the device. In this embodiment, the undoped germanium-silicon layer L1a and the doped germanium-silicon layer L1b are configured to have a thickness ratio of not less than 2:1. For example, the thickness ratio of the undoped germanium-silicon layer L1a to the doped germanium-silicon layer L1b is 2:1, 3:1 or 4:1.
[0076] Figure 5 The graph shows the boron concentration change of the germanium-silicon epitaxial structure in the embedded germanium-silicon device according to an embodiment of the present invention after activation. As can be seen from the graph, the buffer layer L1 exhibits a boron concentration distribution that decreases with increasing depth, and the boron concentration at the maximum depth of the buffer layer L1 is almost zero. This indicates that boron diffusion has not entered the undoped germanium-silicon layer adjacent to the recessed end face of the trench. Furthermore, the germanium-silicon layer at several locations in the buffer layer L1 has a boron concentration close to zero, indicating that boron has not made the buffer layer L1 entirely doped, resulting in undoped regions interspersed between adjacent doped germanium-silicon layers, further reducing the risk of dopant diffusion into the channels.
[0077] In summary, the embedded germanium-silicon device and its fabrication method of the present invention, by setting a germanium-silicon epitaxial structure in the source and drain regions, wherein the germanium-silicon epitaxial structure comprises alternating layers of undoped and doped germanium-silicon layers, the multilayer germanium-silicon epitaxial layer can significantly increase the stress on the channel and achieve high-quality SiGe crystals in the source and drain regions, while preventing dopants in the source and drain regions from diffusing into the channels and affecting the switching characteristics of the device. Furthermore, by configuring the buffer layer as a multilayer germanium-silicon epitaxial layer, the present invention can increase or decrease the number of stacking cycles as needed to ensure that the thickness of the intermediate layer is maintained below the critical thickness, greatly reducing the probability of defect generation, especially avoiding stacking fault accumulation in the germanium-silicon epitaxial layer caused by increased Ge content in the intermediate layer, thereby improving device performance.
[0078] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An embedded germanium-silicon device, characterized in that, include: A semiconductor substrate, on which a gate structure is disposed, and trenches are disposed on both sides of the semiconductor substrate adjacent to the gate structure; A germanium-silicon epitaxial structure is disposed within the trench to form source and drain regions. The germanium-silicon epitaxial structure includes a buffer layer, an intermediate layer, and a capping layer stacked sequentially. The buffer layer includes undoped germanium-silicon layers and doped germanium-silicon layers stacked sequentially from the inner surface of the trench, with the undoped germanium-silicon layer closest to the inner surface of the trench. The undoped and doped germanium-silicon layers are stacked alternately in two or more cycles. The total thickness of the buffer layer is between 100 Å and 250 Å, the germanium content of the buffer layer is between 15% and 30% by molar weight, the thickness ratio of the undoped to the doped germanium-silicon layers is not less than 2:1, and the doping concentration in each doped germanium-silicon layer of the buffer layer increases gradually upward from the bottom of the trench and inward from the sidewalls.
2. The embedded germanium-silicon device according to claim 1, characterized in that, The semiconductor substrate is an N-type silicon substrate, the intermediate layer includes a heavily doped germanium-silicon epitaxial layer, and the capping layer is a silicon capping layer.
3. The embedded germanium-silicon device according to claim 2, characterized in that, The doped germanium-silicon layer and the heavily doped germanium-silicon epitaxial layer contain boron doping, and the average doping concentration of all doped germanium-silicon layers in the buffer layer is between 1E19cm⁻¹. -3 ~1E20 cm -3 between.
4. A method for fabricating an embedded germanium-silicon device, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein a gate structure is formed on the surface of the semiconductor substrate, and trenches are provided on both sides of the semiconductor substrate adjacent to the gate structure. A buffer layer is formed on the inner surface of the trench. The step of forming the buffer layer includes selectively epitaxially growing an undoped germanium-silicon layer and a doped germanium-silicon layer. The undoped germanium-silicon layer is closest to the inner surface of the trench. The undoped germanium-silicon layer and the doped germanium-silicon layer are stacked alternately in two or more cycles. The doping concentration in each doped germanium-silicon layer of the buffer layer increases gradually from the bottom of the trench upwards and from the sidewalls inwards. The total thickness of the buffer layer is between 100 Å and 250 Å, and the thickness ratio of the undoped germanium-silicon layer to the doped germanium-silicon layer is not less than 2:
1. An intermediate layer and a capping layer are epitaxially grown sequentially on the surface of the buffer layer within the trench. The buffer layer, the intermediate layer, and the capping layer are stacked sequentially to form a germanium-silicon epitaxial structure to be formed as the source region and the drain region.
5. The manufacturing method according to claim 4, characterized in that, The steps of forming the buffer layer include: selectively epitaxially growing a first germanium-silicon epitaxial layer at the bottom of the trench to form an undoped germanium-silicon layer; subsequently, selectively epitaxially growing a second germanium-silicon epitaxial layer while in-situ doping the second germanium-silicon epitaxial layer to form a doped germanium-silicon layer.
6. The manufacturing method according to claim 5, characterized in that, The trench is selected as a sigma trench, and the sigma trench is formed by selective etching process to create a recess extending downward toward the gate structure.
7. The manufacturing method according to claim 6, characterized in that, During the selective epitaxial growth of the buffer layer, the undoped germanium-silicon layer and the doped germanium-silicon layer are also alternately grown in the recesses of the sigma-type trench, so that the buffer layer has a gradient increasing germanium content in the direction in which the distance between the recess and the gate structure decreases.
8. The manufacturing method according to claim 4, characterized in that, The step of forming the buffer layer further includes performing the epitaxial growth of the undoped germanium-silicon layer and the doped germanium-silicon layer up to N times, wherein the doped germanium-silicon layer contains boron doping and N is a natural number not less than 2.
9. The manufacturing method according to claim 5, characterized in that, Also includes: In situ doping of the buffer layer simultaneously activates the doped germanium-silicon layer, wherein a portion of the dopant in the doped germanium-silicon layer diffuses to both sides and enters the undoped germanium-silicon layer.