Driving circuit and switching power supply

Abstract

The application provides a driving circuit and a switching power supply, and relates to the technical field of power supply circuits.The driving circuit and the switching power supply provided by the embodiment of the application comprise a first branch, a second branch and a third branch which are arranged in a superimposed manner to form a three-section driving circuit.Through the three-section driving circuit, the first signal that an upper bridge power tube enters a Miller platform and the second signal that the upper bridge power tube exits the Miller platform during the off period of the upper bridge power tube of a logic control circuit in the switching power supply can be obtained, the accurate detection of the Miller platform voltage is realized, then the signals output by the three-section driving circuit are superimposed at the gate of the upper bridge power tube to generate a driving signal of the upper bridge power tube, and the upper bridge power tube is driven, so that the switching loss, EMI and breakdown problem of the power tube of the switching power supply can be effectively alleviated, and the efficiency of the switching power supply is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply circuit, and particularly relates to a driving circuit and a switching power supply. BACKGROUND

[0002] Generally, the switching power supply is widely applied to various electronic devices due to its advantages of high efficiency and low power consumption.

[0003] In actual use, the loss of the switching power supply mainly includes control stage loss and power stage loss. The control stage loss can be usually ignored due to small static current. The power stage loss commonly includes power tube conduction resistance loss, switching loss, dead zone loss and parasitic resistance loss. The design of the driving circuit mainly affects the switching loss and the dead zone loss, and the switching speed of the switching is improved to help improve the loss introduced by the driving circuit. However, the large current change rate di / dt will cause EMC (Electro Magnetic Compatibility) and EMI (Electromagnetic Interference) problems; meanwhile, the large voltage drop caused by the parasitic inductance of the bonding line will also cause the drain voltage vds of the power tube to be large, and the power tube will be broken down in serious cases.

[0004] At present, there is no effective solution to the problems of the above driving circuit. SUMMARY

[0005] Therefore, the present application aims to provide a driving circuit and a switching power supply to alleviate the above technical problems.

[0006] In a first aspect, an embodiment of the present application provides a driving circuit, which is arranged in a switching power supply, the switching power supply comprising a control stage and a power stage, the control stage comprising a logic control circuit and the driving circuit, the power stage comprising a power switch circuit and an output circuit connected in sequence, the power switch circuit being provided with an upper bridge power tube and a lower bridge power tube, the driving circuit being used for driving the upper bridge power tube; the driving circuit comprising: a first branch, a second branch and a third branch arranged in superposition, and an output interface connected with the output ends of the first branch, the second branch and the third branch, the output interface being connected to the gate of the upper bridge power tube; wherein the first branch is used for acquiring a duty cycle signal output by the logic control circuit and an off signal of the lower bridge power tube; generating a first control signal according to the duty cycle signal and the off signal; the second branch is used for acquiring a first signal in which the upper bridge power tube enters a Miller platform during the off period of the upper bridge power tube and a second signal in which the upper bridge power tube exits the Miller platform; generating a second control signal according to the first signal, the second signal and the first control signal of the first branch; the third branch is used for acquiring the second signal and the first control signal, and generating a third control signal according to the second signal and the first control signal; the first control signal, the second control signal and the third control signal are connected to the gate of the upper bridge power tube through the output interface and are superimposed at the gate of the upper bridge power tube to generate a driving signal of the upper bridge power tube, so as to drive the upper bridge power tube.

[0007] In combination with the first aspect, an embodiment of the present application provides a first possible implementation manner of the first aspect, wherein the first branch comprises a first logic gate circuit and a first inverter chain connected in sequence; the input end of the first logic gate circuit is used for acquiring the duty cycle signal and the off signal of the lower bridge power tube, and outputs a first control signal according to the duty cycle signal and the off signal of the lower bridge power tube; the first control signal is enhanced to a first driving signal through the first inverter chain.

[0008] In combination with the first possible implementation manner of the first aspect, an embodiment of the present application provides a second possible implementation manner of the first aspect, wherein the second branch comprises a second logic gate circuit and a second inverter chain connected in sequence; the second logic gate circuit comprises a first input end, a second input end and a third input end; the first input end and the second input end are used for acquiring the first signal and the second signal, and the third input end is connected with the output end of the first logic gate circuit and is used for acquiring the first control signal; the second logic gate circuit is used for generating a second control signal according to the first signal, the second signal and the first control signal; the second control signal is enhanced to a second driving signal through the second inverter chain.

[0009] With reference to the second possible implementation manner of the first aspect, the third possible implementation manner of the first aspect is provided in the embodiments of the present application, and the third branch includes a third logic gate circuit and a third inverter chain connected in sequence; one input terminal of the third logic gate circuit is connected with the output terminal of the first logic gate circuit, and is used for acquiring the first control signal; another input terminal of the third logic gate circuit is used for acquiring the second signal; the third logic gate circuit is used for generating a third control signal according to the first control signal and the second signal; the third control signal is enhanced into a third driving signal through the third inverter chain; and the first to third driving signals generate the driving signal of the upper bridge power tube through the output interface, so as to drive the upper bridge power tube.

[0010] With reference to the third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect is provided in the embodiments of the present application, and the first inverter chain, the second inverter chain and the third inverter chain include an inverter chain and a MOS tube connected in sequence; the output terminal of the inverter chain is connected to the gate of the MOS tube; the source of the MOS tube is connected to a preset high level, and the drain of the MOS tube is used for outputting the corresponding driving signal.

[0011] With reference to the first possible implementation manner of the first aspect, the fifth possible implementation manner of the first aspect is provided in the embodiments of the present application, and the driving circuit further includes a Miller platform detection circuit; the Miller platform detection circuit includes a first MOS tube and a second MOS tube connected in sequence, wherein the first MOS tube is a P-type MOS tube, the second MOS tube is an N-type MOS tube, the drain of the first MOS tube is connected with the drain of the second MOS tube; the gate of the first MOS tube is connected with the output interface of the driving circuit, and is used for acquiring the driving signal; the gate of the second MOS tube is connected with the output terminal of the first logic gate circuit, and is used for acquiring the first control signal; the output terminal of the Miller platform detection circuit is connected to the connection path of the first MOS tube and the second MOS tube, and is used for outputting the second signal according to the driving signal and the first control signal; wherein the gate of the second MOS tube is provided with an enhancement circuit, and the output terminal of the Miller platform detection circuit is provided with a hysteresis circuit; and the enhancement circuit and the hysteresis circuit are used for improving the driving capability of the Miller platform detection circuit.

[0012] With the first possible implementation manner of the first aspect, the present embodiment provides a sixth possible implementation manner of the first aspect, wherein the first logic gate circuit comprises a NAND gate; the duty cycle signal and the off signal of the lower bridge power tube are input to the first logic gate circuit through input pins of the NAND gate, and an output end of the NAND gate outputs the first control signal.

[0013] With the second possible implementation manner of the first aspect, the present embodiment provides a seventh possible implementation manner of the first aspect, wherein the second logic gate circuit comprises a NAND gate, an OR gate and a NAND gate connected in sequence; the first input end is an input end of the NAND gate, and an output end of the NAND gate is connected to one input end of the OR gate; the other input end of the OR gate is the second input end; an output end of the OR gate is connected to one input end of the NAND gate, and the other input end of the NAND gate is the third input end.

[0014] With the third possible implementation manner of the first aspect, the present embodiment provides an eighth possible implementation manner of the first aspect, wherein the third logic gate circuit comprises a NAND gate, one input end of the NAND gate is connected to an output end of the first logic gate circuit; and the other input end of the NAND gate is used to obtain the second signal.

[0015] In the second aspect, the present embodiment also provides a switching power supply, which comprises a control stage and a power stage; the control stage comprises a logic control circuit and the driving circuit of the first aspect connected in sequence; the power stage comprises a power supply body, a power switching circuit and an output circuit connected in sequence, the power switching circuit is provided with an upper bridge power tube and a lower bridge power tube, and the driving circuit is used to drive the upper bridge power tube.

[0016] The present embodiment brings the following beneficial effects:

[0017] The driving circuit and the switching power supply provided by the present embodiment comprise a first branch, a second branch and a third branch arranged in layers to form a three-section driving circuit, so that the first signal that the upper bridge power tube enters the Miller platform and the second signal that the upper bridge power tube exits the Miller platform during the off period of the upper bridge power tube in the logic control circuit of the switching power supply can be obtained through the three-section driving circuit, the accurate detection of the Miller platform voltage is realized, then the signals output by the three-section driving circuit are superimposed at the gate of the upper bridge power tube to generate the driving signal of the upper bridge power tube, so that the upper bridge power tube can be driven, and the switching loss, EMI and breakdown problem of the power tube of the switching power supply can be effectively alleviated, so that the efficiency of the switching power supply is improved.

[0018] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The purposes and other advantages of the application will be realized and attained by the structure particularly pointed out in the description, claims and drawings.

[0019] In order to make the above objectives, features and advantages of the present application more apparent, the following will describe a preferred embodiment in detail, and the accompanying drawings will be referred to, as follows. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0021] Figure 1 A working principle schematic diagram of a switching power supply provided by the embodiment of the present application;

[0022] Figure 2 A structure schematic diagram of a driving circuit provided by the embodiment of the present application;

[0023] Figure 3 A circuit principle schematic diagram of a driving circuit provided by the embodiment of the present application;

[0024] Figure 4 A detection principle schematic diagram of a Miller platform detection circuit provided by the embodiment of the present application;

[0025] Figure 5 A working waveform schematic diagram of a driving circuit provided by the embodiment of the present application;

[0026] Figure 6 A working waveform diagram of a Miller platform detection circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the present application will be described clearly and completely in the following with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0028] Generally, the loss of the switching power supply mainly includes the control stage loss and the power stage loss. The control stage loss can be usually ignored due to the small static current. The power stage loss commonly includes the power tube conduction resistance loss, the switching loss, the dead zone loss and the parasitic resistance loss. In the prior art, in order to solve the loss of the driving stage and the EMI and the power tube withstand voltage problem, the driving circuit used can not accurately detect the Miller platform, but can only approximately preset a platform voltage value, and it is difficult to accurately track the voltage value of the Miller platform, which can easily cause a large current change rate, and can even cause the power tube breakdown problem.

[0029] Based on this, the driving circuit and the switching power supply provided by the embodiment of the present application can accurately detect the voltage of the Miller platform, and can alleviate the above technical problems by effectively controlling the driving circuit.

[0030] In order to facilitate the understanding of the present embodiment, first, a driving circuit disclosed by the present embodiment is introduced in detail.

[0031] In a possible implementation, the present embodiment provides a driving circuit, which is arranged in a switching power supply. The switching power supply usually includes a control stage and a power stage. The control stage includes a logic control circuit and the driving circuit in the present embodiment. Further, the power stage includes a power switching circuit and an output circuit connected in sequence. The input end of the power switching circuit is connected to a power body.

[0032] Generally, the power switching circuit is provided with an upper bridge power tube and a lower bridge power tube. The driving circuit provided by the present embodiment is used to drive the upper bridge power tube.

[0033] In order to facilitate the understanding, Figure 1 A working principle schematic diagram of a switching power supply is shown, wherein, Figure 1 For example, a Buck DC-DC switching circuit in a step-down type is taken as an example for illustration, as shown in Figure 1 The switching power supply includes two modules of a control stage and a power stage. S1 and S2 are an upper bridge power tube S1 and a lower bridge power tube S2 arranged in the power switching circuit. The output voltage of the power body Vg is controlled by switching the conduction state. The logic control circuit of the control stage mainly includes a compensation circuit (such as Z1 and Z2), a comparison circuit (EA), a logic circuit and a driving circuit.

[0034] Based on Figure 1The switching power supply shown typically sends a certain percentage of its output voltage to the compensation circuit. Specifically, the output voltage is divided by a voltage divider circuit composed of Rf1 and Rf2 to output a certain percentage of the output voltage, which is then input as Vfb to the compensation circuit Z1. A comparison circuit and logic circuit then generate a duty cycle, which serves as the control logic Duty for switching the operating states of the upper-bridge power transistor S1 and the lower-bridge power transistor S2. Because the upper-bridge power transistors S1 and S2 are relatively large and have significant parasitic capacitance, Duty cannot be directly used as the gate drive signal for the power transistors. Therefore, the drive circuit provided in this embodiment is needed to drive the gate of the upper-bridge power transistor S1, while the gate of the lower-bridge power transistor S2 is typically driven and controlled by the main controller of the switching power supply.

[0035] Specifically, such as Figure 2 The schematic diagram of a driving circuit shown in the present invention includes: a first branch 10, a second branch 20 and a third branch 30 stacked together, and an output interface 40 connected to the output terminals of the first branch 10, the second branch 20 and the third branch 30, wherein the output interface 40 is connected to the gate of the upper bridge power transistor.

[0036] The first branch 10 is used to acquire the duty cycle signal output by the logic control circuit (e.g., Figure 1 The duty cycle signal and the turn-off signal of the lower bridge power transistor are used to generate the first control signal based on the duty cycle signal and the turn-off signal.

[0037] The second branch 20 is used to acquire the first signal when the upper bridge power transistor enters the Miller platform and the second signal when the upper bridge power transistor exits the Miller platform during the turn-off period of the logic control circuit; and to generate the second control signal based on the first signal, the second signal and the first control signal of the first branch 10.

[0038] The third branch 30 is used to acquire the second signal and the first control signal mentioned above, and to generate a third control signal based on the second signal and the first control signal.

[0039] The first control signal, the second control signal, and the third control signal are connected to the upper bridge power transistor through the output interface 40. Figure 2 The gate of the transistor (not shown) is superimposed on the gate of the upper bridge power transistor to generate a drive signal for the upper bridge power transistor, so as to drive the upper bridge power transistor.

[0040] The driving circuit provided by the embodiment of the present application comprises a first branch, a second branch and a third branch arranged in a superimposed manner to form a three-stage driving circuit. Through the three-stage driving circuit, the first signal of the upper bridge power tube entering the Miller platform and the second signal of the upper bridge power tube exiting the Miller platform during the off period of the upper bridge power tube of the logic control circuit in the switching power supply can be obtained, the accurate detection of the Miller platform voltage is realized, and then the signals output by the three-stage driving circuit are superimposed at the gate of the upper bridge power tube to generate a driving signal of the upper bridge power tube, so that the upper bridge power tube can be driven, the switching loss, EMI and breakdown of the power tube of the switching power supply can be effectively alleviated, and the efficiency of the switching power supply is improved.

[0041] In actual use, the first branch comprises a first logic gate circuit and a first inverter chain connected in sequence; the input end of the first logic gate circuit is used to obtain the duty cycle signal and the off signal of the lower bridge power tube, and outputs a first control signal according to the duty cycle signal and the off signal of the lower bridge power tube; and the first control signal is enhanced to a first driving signal through the first inverter chain.

[0042] Further, the second branch comprises a second logic gate circuit and a second inverter chain connected in sequence; the second logic gate circuit comprises a first input end, a second input end and a third input end; the first input end and the second input end are used to obtain the first signal and the second signal; and the third input end is connected with the output end of the first logic gate circuit and is used to obtain the first control signal.

[0043] The second logic gate circuit is used to generate a second control signal according to the first signal, the second signal and the first control signal; and the second control signal is enhanced to a second driving signal through the second inverter chain.

[0044] Further, the third branch comprises a third logic gate circuit and a third inverter chain connected in sequence; one of the input ends of the third logic gate circuit is connected with the output end of the first logic gate circuit and is used to obtain the first control signal; and the other input end of the third logic gate circuit is used to obtain the second signal.

[0045] The third logic gate circuit is used to generate a third control signal according to the first control signal and the second signal; and the third control signal is enhanced to a third driving signal through the third inverter chain.

[0046] The first driving signal to the third driving signal are used to act on the upper bridge power tube through the output interface 40 to drive the upper bridge power tube.

[0047] In order to facilitate understanding, Figure 3 a circuit principle schematic diagram of a driving circuit is shown, as Figure 3 It is shown that the dashed part respectively represents the first branch, the second branch and the third branch.

[0048] Specifically, in this embodiment of the invention, the first logic gate circuit includes a NAND gate; the duty cycle signal and the turn-off signal of the lower bridge power transistor are input to the first logic gate circuit through the input pin of the NAND gate, so that the output terminal of the NAND gate outputs a first control signal.

[0049] Furthermore, such as Figure 3 As shown in the embodiment of the present invention, the second logic gate circuit includes a NOT gate, an OR gate, and a NAND gate connected in sequence.

[0050] The first input of the second logic gate circuit is the input of the NOT gate, and the output of the NOT gate is connected to one of the inputs of the OR gate; the other input of the OR gate is the second input; the output of the OR gate is connected to one of the inputs of the NAND gate, and the other input of the NAND gate is the third input.

[0051] and Figure 3 In this embodiment of the invention, the third logic gate circuit includes a NAND gate, one of the input terminals of which is connected to the output terminal of the NAND gate of the first logic gate circuit; the other input terminal of the NAND gate of the third logic gate circuit is used to acquire the aforementioned second signal.

[0052] Furthermore, such as Figure 3 As shown, the first inverter chain, second inverter chain, and second inverter chain in this embodiment of the invention include inverter chains and MOSFETs connected in sequence; the first inverter chain of the first branch is used as an example for illustration, as follows... Figure 3 As shown, a MOSFET P1 and an inverter chain F1 are illustrated. The inverter chain F1 consists of multiple NOT gates connected in series, which is used to improve the driving capability of the inverter chain and enhance the input control signal. The output of the inverter chain is connected to the gate of the MOSFET P1; the source of the MOSFET P1 is connected to a preset high level, and the drain of the MOSFET P1 is used to output the first, second, or third driving signal of the corresponding branch.

[0053] Furthermore, the driving circuit in this embodiment of the invention also includes a Miller platform detection circuit; specifically, Figure 4 A schematic diagram of the detection principle of a Miller platform detection circuit is shown, as follows. Figure 4 As shown, the Miller platform detection circuit includes a first MOSFET MP1 and a second MOSFET MN1 connected in sequence. MP1 is a P-type MOSFET, and MN1 is an N-type MOSFET. The drains of the first and second MOSFETs are connected, and the gate of the first MOSFET is connected to the output interface of the driving circuit to acquire the driving signal. Figure 3 The driving signal PG is the superposition of PG1, PG2 and PG3 in the signal.

[0054] Further, the gate of the second MOS transistor is connected with the output terminal of the first logic gate, for obtaining the first control signal;

[0055] The output terminal of the Miller platform detection circuit is connected to the connection path of the first MOS transistor and the second MOS transistor, for outputting the second signal according to the driving signal and the first control signal.

[0056] Wherein, the gate of the second MOS transistor is provided with an enhancement circuit, and the output terminal of the Miller platform detection circuit is provided with a hysteresis circuit; the enhancement circuit and the hysteresis circuit are used for improving the driving capability of the Miller platform detection circuit. Figure 4 Wherein, the enhancement circuit is composed of two series non-gates, and the hysteresis circuit usually includes a hysteresis comparator circuit, and it should be understood that Figure 4 The enhancement circuit and the hysteresis circuit shown in the figure are only one possible implementation, and in other embodiments, the enhancement circuit and the hysteresis circuit can also have other connection conditions, which can be set according to actual use, and the embodiments of the present application do not limit this.

[0057] For the convenience of understanding, based on the driving circuit shown in Figure 3 and the Miller platform detection circuit shown in Figure 4 , the driving process of the upper bridge power transistor is described:

[0058] Specifically, the driving signal of the gate of the upper bridge power transistor is denoted as PG, which is superimposed by the driving signals PG1, PG2 and PG3 generated by the three branches in Figure 3 .

[0059] Wherein, Figure 3 In the figure, the first branch is controlled by the duty cycle signal Duty generated by the control stage shown in Figure 1 and the off signal LS_off generated when the lower bridge power transistor is off, and the first control signal OFF_pre generated by the non-gate controls; when the duty cycle signal Duty and the off signal LS_off are all 1, PG1 is 0, at this time the upper bridge power transistor is opened; when the duty cycle signal Duty and the off signal LS_off exist one is 0 or both are 0, the upper bridge power transistor enters the off state, at this time OFF_pre is 1, OFF1 is 0, and the first driving signal PG1 of the first branch is continuously 1.

[0060] In the three working stages during the off period of the upper bridge power tube, the first driving signal PG1 generated by the first branch is always 1; the second branch is controlled by the signal OFF2 generated by the logical combination of the first control signal OFF_pre and PG_r_off1, PG_r_off2 through the second logic gate circuit, wherein PG_r_off1 is the signal for judging that the upper bridge power tube enters the Miller plateau during the off period of the upper bridge power tube, i.e. the first signal mentioned above, which is usually generated by the Schmidt trigger in Figure 1 . PG_r_off2 is the signal for judging that the upper bridge power tube exits the Miller plateau during the off period of the upper bridge power tube, i.e. the second signal mentioned above, which is generated by the Miller plateau detection circuit shown in Figure 4 .

[0061] When the upper bridge power tube is to be transitioned from the on state to the off state, it will first experience the linear region, i.e. the first stage; when it is transitioned from the linear region to the saturation region, i.e. VPG=VIN-VTH, it starts to enter the second stage, at which time the first signal PG_r_off1 is 1, announcing the entry into the second stage; at this time, OFF2 will change from 0 to 1, and the second branch will no longer work; until the second signal PG_r_off2 for judging that the upper bridge power tube exits the Miller plateau is high, announcing the entry into the third stage, at which time the working state of the upper bridge power tube is changed from the saturation region to the sub-threshold region; OFF2 changes from 1 to 0, and the second branch starts to work; at the same time, the third branch also starts to work, accelerating the off rate of the upper bridge power tube in the Miller plateau.

[0062] In order to facilitate understanding, Figure 5 a working waveform diagram of the driving circuit is also shown, which includes the duty cycle signal Duty, the off signal LS_off, the first control signal OFF_pre, the driving signal PG when entering the Miller plateau, the driving signal VIN-PG when exiting the Miller plateau, the first signal PG_r_off1, the second signal PG_r_off2, and Figure 3 the signals OFF1, OFF2 and OFF3 generated by the logical combination of each of them.

[0063] As can be seen from the above Figure 5 , the Miller voltage of the Miller plateau will change significantly with PVT (power-voltage-temperature). If the upper bridge power tube exits the Miller plateau too early during the off period, the vds will be very large at this time in order to maintain the current, which will seriously cause the withstand voltage problem, leading to the breakdown of the upper bridge power tube, and even damaging the power management chip; but if the time for the upper bridge power tube to exit the Miller plateau is delayed, the change rate of the vds of the upper bridge power tube will be reduced, the overlap loss will be increased, and the efficiency will be reduced, while the embodiment of the present application provides a brand-new method for judging that the upper bridge power tube exits the Miller plateau, as shown in Figure 4As shown, when either the duty cycle signal Duty or the turn-off signal LS_off is 0, or both are 0, the upper bridge power transistor turn-off signal arrives. At this time, OFF_pre is 1, MN1 is normally turned on, and the drive signal PG starts to change from 0 to 1. MP1 remains on as long as the voltage of the drive signal PG is less than VIN-VTH, where VIN represents the power supply voltage and VTH represents the threshold voltage of the upper bridge power transistor. The Miller platform detection signal PG_miller is 1. When the drive signal PG is equal to or greater than VIN-VTH, MP1 is turned off, and the drive signal PG is 0. Since the VTH of MP1 and the upper bridge power transistor changes in the same way with PVT, this... Figure 4 The Miller plateau detection circuit shown generates a signal that can accurately detect changes in VTH, i.e., changes in the Miller plateau voltage, and produces a Miller plateau detection signal PG_miller. This signal is sent to the hysteresis comparator to generate the PG_r_OFF2 signal as the Miller plateau exit signal, i.e., the second signal mentioned above. Figure 4 The operating waveform diagram of the Miller platform detection circuit shown is as follows: Figure 6 As shown, the first control signal OFF_pre, the drive signal PG, the VGS voltage of the upper bridge power transistor at this time are represented as VGS=VIN-PG, and the Miller plateau detection signal PG_miller and the second signal PG_r_OFF2 are shown respectively.

[0064] Based on the above analysis, the driving circuit provided in this embodiment of the invention implements a novel technology for detecting Miller plateau voltage and provides a better way to exit the Miller plateau. It solves the problem of inaccurate Miller voltage detection caused by the variation of the Miller plateau voltage value of the upper bridge power transistor with PVT, and can obtain a precisely detected Miller voltage. Its advantages lie in its simple structure. Furthermore, the PVT change of the Miller voltage detection transistor maps to the PVT change of the upper bridge power transistor, resulting in a precise Miller voltage value. This allows for more precise control of di / dt of the upper bridge power transistor during the transition between the second and third stages, thereby solving problems such as switching losses, EMI, and power transistor breakdown.

[0065] Furthermore, embodiments of the present invention also provide a switching power supply, which includes a control stage and a power stage; the control stage includes a logic control circuit and the aforementioned drive circuit connected in sequence; to Figure 1 The switching power supply shown may include a logic control circuit such as a compensation circuit, a comparator circuit, a clock circuit, and a Schmitt trigger circuit. The power stage includes a power supply body, a power switching circuit, and an output circuit connected in sequence. The power switching circuit has an upper-bridge power transistor and a lower-bridge power transistor. The driving circuit described in this embodiment is used to drive the upper-bridge power transistor.

[0066] The switching power supply provided by the embodiment of the present application has the same technical features as the driving circuit provided by the above embodiment, and can solve the same technical problem and achieve the same technical effect.

[0067] The computer program product of the driving circuit and the switching power supply provided by the embodiment of the present application comprises a computer readable storage medium storing program codes, the program codes comprise instructions for executing the method described in the foregoing method embodiments, and the specific implementation can be referred to the method embodiments, which will not be described here.

[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the switching power supply described above can refer to the corresponding process in the foregoing embodiments, which will not be described here.

[0069] In addition, in the description of the embodiment of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0070] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application which essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of software products, which are stored in a storage medium and include a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0071] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0072] Finally, it should be noted that the above embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical scope disclosed by the present application, or make equivalent substitutions for some technical features; and these modifications, changes or substitutions do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A drive circuit characterized by comprising: The drive circuit is arranged in a switching power supply, the switching power supply comprises a control stage and a power stage, the control stage comprises a logic control circuit and the drive circuit, the power stage comprises a power switch circuit and an output circuit connected in sequence, the power switch circuit is provided with upper bridge power tubes and lower bridge power tubes, and the drive circuit is used for driving the upper bridge power tubes; The drive circuit comprises: a first branch, a second branch and a third branch arranged in superposition, and an output interface connected with the output ends of the first branch, the second branch and the third branch, and the output interface is connected to the gate of the upper bridge power tube; The first branch is used for acquiring the duty cycle signal output by the logic control circuit and the off signal of the lower bridge power tube; and a first control signal is generated according to the duty cycle signal and the off signal; The second branch is used for acquiring the first signal that the upper bridge power tube enters the Miller platform during the off period of the upper bridge power tube and the second signal that the upper bridge power tube exits the Miller platform; and a second control signal is generated according to the first signal, the second signal and the first control signal of the first branch; The third branch is used for acquiring the second signal and the first control signal, and a third control signal is generated according to the second signal and the first control signal; The first control signal, the second control signal and the third control signal are connected to the gate of the upper bridge power tube through the output interface and are superimposed at the gate of the upper bridge power tube to generate a drive signal of the upper bridge power tube, so as to drive the upper bridge power tube.

2. The drive circuit according to claim 1, characterized in that, The first branch comprises a first logic gate circuit and a first inverter chain connected in sequence; The input end of the first logic gate circuit is used for acquiring the duty cycle signal and the off signal of the lower bridge power tube, and a first control signal is output according to the duty cycle signal and the off signal of the lower bridge power tube; The first control signal is enhanced to a first drive signal through the first inverter chain.

3. The drive circuit according to claim 2, characterized in that, The second branch comprises a second logic gate circuit and a second inverter chain connected in sequence; The second logic gate circuit comprises a first input end, a second input end and a third input end; the first input end and the second input end are used for acquiring the first signal and the second signal, and the third input end is connected with the output end of the first logic gate circuit and is used for acquiring the first control signal; The second logic gate circuit is used for generating a second control signal according to the first signal, the second signal and the first control signal; The second control signal is enhanced to a second drive signal through the second inverter chain.

4. The drive circuit according to claim 3, characterized in that, The third branch comprises a third logic gate circuit and a third inverter chain connected in sequence; One of the input ends of the third logic gate circuit is connected with the output end of the first logic gate circuit and is used for acquiring the first control signal; and the other input end of the third logic gate circuit is used for acquiring the second signal; The third logic gate circuit is used for generating a third control signal according to the first control signal and the second signal; The third control signal is enhanced to a third drive signal through the third inverter chain. The third control signal is enhanced into a third driving signal by the third inverter chain; and the first to third driving signals generate a driving signal of the upper bridge power tube through an output interface to drive the upper bridge power tube.

5. The drive circuit according to claim 4, characterized in that, The first inverter chain, the second inverter chain and the third inverter chain comprise an inverter chain and a MOS tube connected in sequence; and an output end of the inverter chain is connected to a gate of the MOS tube. A source of the MOS tube is connected to a preset high level, and a drain of the MOS tube is used to output a corresponding driving signal.

6. The drive circuit according to claim 2, characterized by The driving circuit further comprises a Miller platform detection circuit. The Miller platform detection circuit comprises a first MOS tube and a second MOS tube connected in sequence, wherein the first MOS tube is a P-type MOS tube, the second MOS tube is an N-type MOS tube, and a drain of the first MOS tube is connected to a drain of the second MOS tube. Further, a gate of the first MOS tube is connected to the output interface of the driving circuit to obtain the driving signal. A gate of the second MOS tube is connected to an output end of the first logic gate circuit to obtain the first control signal. An output end of the Miller platform detection circuit is connected to a connection path of the first MOS tube and the second MOS tube to output the second signal according to the driving signal and the first control signal. Further, the gate of the second MOS tube is provided with an enhancement circuit, and the output end of the Miller platform detection circuit is provided with a hysteresis circuit. The enhancement circuit and the hysteresis circuit are used to improve the driving capability of the Miller platform detection circuit.

7. The drive circuit according to claim 2, characterized by The first logic gate circuit comprises a NAND gate. The duty cycle signal and an off signal of the lower bridge power tube are input to the first logic gate circuit through input pins of the NAND gate, and an output end of the NAND gate outputs the first control signal.

8. The drive circuit according to claim 3, characterized by The second logic gate circuit comprises a NAND gate, an OR gate and a NAND gate connected in sequence. The first input end is an input end of the NAND gate, and an output end of the NAND gate is connected to one of input ends of the OR gate. The other input end of the OR gate is the second input end. An output end of the OR gate is connected to one of input ends of the NAND gate, and the other input end of the NAND gate is used as the third input end.

9. The drive circuit of claim 4, wherein, The third logic gate circuit comprises a NAND gate, one of input ends of the NAND gate is connected to an output end of the first logic gate circuit, and the other input end of the NAND gate is used to obtain the second signal.

10. A switching power supply, characterized by comprising: The switching power supply comprises a control stage and a power stage. The control stage comprises a logic control circuit and the driving circuit according to any one of claims 1-9 connected in sequence. The power stage comprises a power supply body, a power switching circuit and an output circuit connected in sequence, the power switching circuit is provided with an upper bridge power tube and a lower bridge power tube, and the driving circuit is used to drive the upper bridge power tube.

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