Power mosfet gate driver and power mosfet gate driving system

Abstract

The application relates to the technical field of circuits, and particularly discloses a power MOS tube gate driver and a power MOS tube gate driving system, wherein a pull-up driving stage PMOS tube and a pull-up driving stage NMOS tube are arranged between a first direct current power supply and a driving signal output end of a power MOS tube gate, a pull-down driving stage NMOS tube is arranged between the driving signal output end and the ground, a gate pull-up pre-driving circuit is used to pre-drive and control the pull-up driving stage PMOS tube and the pull-up driving stage NMOS tube to open the pull-up driving stage PMOS tube and the pull-up driving stage NMOS tube, the current size that can be provided in the moment when the power MOS needs to be opened is effectively increased, a gate pull-down pre-driving circuit is used to open the pull-down driving stage NMOS tube to quickly pull down the power MOS tube gate, the output driving signal can be quickly raised and lowered without a large-area circuit, the switching loss is reduced, and the efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a power MOS gate driver and a power MOS gate driving system. BACKGROUND

[0002] Power MOS is widely used in power supply, motor, automotive electronics and other devices. The voltage of the gate driver of the power MOS needs to be designed to be above 10V, so that the power MOS can be fully opened and the performance of the power MOS can be better. In application, the gate driver needs to provide fast rising and falling time, so as to reduce the switching loss of the power MOS when it is opened and closed. However, due to the large gate capacitance of the power MOS and the influence of the drain capacitance (also known as Miller capacitance) of the power MOS, there is a Miller platform in the opening process of the power MOS, which makes the opening time of the power MOS longer and the loss increases dramatically. In order to solve the problem of Miller platform, the gate driver needs to have the ability to provide large current, and when the power MOS is opened, the gate of the power MOS does not need to absorb large current, at this time the gate driver only needs to maintain voltage. Therefore, the gate driver is required to be designed to convert the logic signal into a driving signal with a magnitude of 10V or more, and to have the ability of instantaneous large current drive.

[0003] Figure 1 The existing structure of the gate driver is shown in the figure.

[0004] As shown in Figure 1 , the gate driver mainly consists of a gate pull-up circuit for controlling the opening of the power MOS Q and a gate pull-down circuit for controlling the closing of the power MOS. The gate pull-down circuit usually adopts NMOS tube to build. The gate pull-up circuit mainly has two design schemes, the first one is to adopt PMOS tube to build, but the ability of PMOS tube to provide large current is poor, in order to realize the ability of instantaneous large current drive, the area cost is high; the second one is to adopt NMOS tube to build, but it needs to provide voltage higher than the power supply to ensure the rail-to-rail output range (i.e. the output range is consistent with the input range to ensure accurate control), which also needs high area cost. SUMMARY

[0005] The purpose of the present application is to provide a power MOS gate driver and a power MOS gate driving system, which realizes gate driving by adopting the combination of PMOS tube and NMOS tube in the gate pull-up circuit, effectively increases the size of the current that can be provided when the power MOS needs to be opened, and does not need to lay a large area of circuit, so as to realize the rapid rising and falling of the output driving signal, reduce the switching loss and improve the efficiency.

[0006] To solve the above technical problems, the application provides a power MOS tube gate driver, which comprises a gate pull-up pre-driver circuit, a gate pull-down pre-driver circuit, an upper pull driving stage PMOS tube, an upper pull driving stage NMOS tube and a lower pull driving stage NMOS tube.

[0007] The input end of the gate pull-up pre-driver circuit is connected with the upper pull signal output end of the controller, the first output end of the gate pull-up pre-driver circuit is connected with the gate of the upper pull driving stage PMOS tube, the second output end of the gate pull-up pre-driver circuit is connected with the gate of the upper pull driving stage NMOS tube, and the drain of the upper pull driving stage PMOS tube and the drain of the upper pull driving stage NMOS tube are connected with a first direct current power supply.

[0008] The input end of the gate pull-down pre-driver circuit is connected with the lower pull signal output end of the controller, and the output end of the gate pull-down pre-driver circuit is connected with the gate of the lower pull driving stage NMOS tube.

[0009] The source of the upper pull driving stage PMOS tube, the source of the upper pull driving stage NMOS tube and the drain of the lower pull driving stage NMOS tube are connected as a driving signal output end for the gate of the power MOS tube, and the source of the lower pull driving stage NMOS tube is connected with the ground.

[0010] Optionally, the signal non-overlapping processing module is further included.

[0011] The signal input end of the signal non-overlapping processing module is connected with the control signal output end of the controller, the first output end of the signal non-overlapping processing module is connected with the input end of the gate pull-up pre-driver circuit, and the second output end of the signal non-overlapping processing module is connected with the input end of the gate pull-down pre-driver circuit.

[0012] Optionally, the enable end of the signal non-overlapping processing module is connected with the enable signal output end of the controller.

[0013] Optionally, the gate pull-up pre-driver circuit specifically comprises a first inverter, a level conversion module, a PMOS tube pre-driver circuit and a first NMOS tube pre-driver circuit.

[0014] The input end of the first inverter is connected with the upper pull signal output end of the controller, the output end of the first inverter is connected with the input end of the level conversion module, the output end of the level conversion module is connected with the input end of the PMOS tube pre-driver circuit and the input end of the first NMOS tube pre-driver circuit, the output end of the PMOS tube pre-driver circuit is connected with the gate of the upper pull driving stage PMOS tube, and the output end of the first NMOS tube pre-driver circuit is connected with the gate of the upper pull driving stage NMOS tube.

[0015] The level conversion module is used for converting the pull-up control signal into a pull-up pre-drive signal with a floating ground voltage value to a first DC power voltage value.

[0016] The floating ground voltage value is determined according to the first DC power voltage value and parameters of the pull-up drive stage PMOS tube.

[0017] Optionally, the first NMOS tube pre-drive circuit specifically comprises a second inverter, a first capacitor, a first diode, a first PMOS tube and a first resistor.

[0018] The input end of the second inverter is connected with the output end of the level conversion module, the output end of the second inverter is connected with the first end of the first capacitor, the power supply pin of the second inverter is connected with a second DC power supply, the ground pin of the second inverter is connected with a floating ground signal source, the anode of the first diode and the gate of the first PMOS tube are connected with the first DC power supply, the second end of the first capacitor and the cathode of the first diode are connected with the drain of the first PMOS tube, the drain of the first PMOS tube and the first end of the first resistor are connected with the gate of the pull-up drive stage NMOS tube, and the second end of the first resistor is grounded.

[0019] Optionally, the first NMOS tube pre-drive circuit further comprises a second PMOS tube and a second diode.

[0020] The drain of the second PMOS tube is connected with the first DC power supply, the gate of the second PMOS tube is connected with the output end of the level conversion module, and the source of the second PMOS tube is connected with the anode of the second diode. The cathode of the second diode is connected with the source of the first PMOS tube.

[0021] Optionally, the first NMOS tube pre-drive circuit further comprises a first NMOS tube.

[0022] The gate of the first NMOS tube is connected with the output end of the first inverter, the drain of the first NMOS tube is connected with the source of the first PMOS tube, and the source of the first NMOS tube is grounded.

[0023] Optionally, the PMOS tube pre-drive circuit is a third buffer.

[0024] The input end of the third buffer is connected with the output end of the level conversion module, the output end of the third buffer is connected with the gate of the pull-up drive stage PMOS tube, the power supply pin of the third buffer is connected with the first DC power supply, and the ground pin of the third buffer is connected with a floating ground signal source.

[0025] Optionally, the gate pull-down pre-driver circuit is a fourth buffer;

[0026] The input end of the fourth buffer is connected with the pull-down signal output end, and the output end of the fourth buffer is connected with the gate of the pull-down driving stage NMOS tube.

[0027] To solve the above technical problems, the application further provides a power MOS tube gate driving system, comprising the power MOS tube gate driver described in any one of the above, and further comprising a controller.

[0028] The pull-up signal output end of the controller is connected with the input end of the gate pull-up pre-driver circuit of the power MOS tube gate driver, and the pull-down signal output end of the controller is connected with the input end of the gate pull-down pre-driver circuit.

[0029] The power MOS tube gate driver provided by the application sets the pull-up driving stage PMOS tube and the pull-up driving stage NMOS tube between the first direct current power supply and the driving signal output end of the power MOS tube gate, sets the pull-down driving stage NMOS tube between the driving signal output end and the ground, pre-drives and controls the pull-up driving stage PMOS tube and the pull-up driving stage NMOS tube by the gate pull-up pre-driver circuit to open the pull-up driving stage PMOS tube and the pull-up driving stage NMOS tube, effectively increases the current size that can be provided at the moment when the power MOS needs to be opened, opens the pull-down driving stage NMOS tube by the gate pull-down pre-driver circuit to quickly pull down the power MOS tube gate, and the large-area circuit is not needed to realize the rapid rising and falling of the output driving signal, reduces the switching loss, and improves the efficiency.

[0030] The application further provides a power MOS tube gate driving system, which has the above beneficial effects, and details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0032] Figure 1 It is a structural schematic diagram of the existing gate driver;

[0033] Figure 2 It is a structural schematic diagram of the power MOS tube gate driver provided by the embodiment of the application;

[0034] Figure 3A circuit diagram of a power MOS tube gate driver provided by an embodiment of the present application is provided.

[0035] The 201 is a gate pull-up pre-driver circuit, the 202 is a gate pull-down pre-driver circuit, and the 203 is a signal non-overlapping processing module. DETAILED DESCRIPTION

[0036] The core of the present application is to provide a power MOS tube gate driver and a power MOS tube gate driving system. The gate driving is realized by using the combination of PMOS tubes and NMOS tubes in the gate pull-up circuit, which effectively increases the current that can be provided at the moment when the power MOS tube needs to be turned on. Without laying a large area of circuit, the fast rising and falling of the output driving signal can be realized, the switching loss is reduced, and the efficiency is improved.

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0038] Embodiment one

[0039] Figure 2 A structural schematic diagram of a power MOS tube gate driver provided by an embodiment of the present application is provided.

[0040] As shown in Figure 2 The power MOS tube gate driver provided by the embodiment of the present application includes: a gate pull-up pre-driver circuit 201, a gate pull-down pre-driver circuit 202, a pull-up driving stage PMOS tube M1, a pull-up driving stage NMOS tube M2, and a pull-down driving stage NMOS tube M3.

[0041] The input end of the gate pull-up pre-driver circuit 201 is connected with the pull-up signal output end of the controller, the first output end of the gate pull-up pre-driver circuit 201 is connected with the gate of the pull-up driving stage PMOS tube M1, the second output end of the gate pull-up pre-driver circuit 201 is connected with the gate of the pull-up driving stage NMOS tube M2, and the drain of the pull-up driving stage PMOS tube M1 and the drain of the pull-up driving stage NMOS tube M2 are both connected with a first direct current power supply VBB.

[0042] The input end of the gate pull-down pre-driver circuit 202 is connected with the pull-down signal output end of the controller, and the output end of the gate pull-down pre-driver circuit 202 is connected with the gate of the pull-down driving stage NMOS tube M3.

[0043] The source of the pull-up drive stage PMOS transistor M1, the source of the pull-up drive stage NMOS transistor M2, and the drain of the pull-down drive stage NMOS transistor M3 are connected to the drive signal output terminal OUT of the power MOS transistor gate, and the source of the pull-down drive stage NMOS transistor M3 is grounded.

[0044] In a specific implementation, the power MOS transistor gate driver provided in this application embodiment has a pull-up driving stage PMOS transistor M1 and a pull-up driving stage NMOS transistor M2 between the first DC power supply VBB and the drive signal output terminal OUT of the power MOS transistor gate, and a pull-down driving stage NMOS transistor M3 between the drive signal output terminal OUT and ground.

[0045] The gate pull-up pre-drive circuit 201 needs to include a PMOS pre-drive circuit for the pull-up drive stage PMOS transistor M1 and a first NMOS transistor M6 pre-drive circuit for the pull-up drive stage NMOS transistor M2. This is necessary when the power MOS transistor (e.g., Figure 1 When the power MOSFET Q is turned on, the controller outputs a pull-up control signal. The PMOS transistor pre-drive circuit of the gate pull-up pre-drive circuit 201 converts the pull-up control signal into a pre-drive signal HS_PG for the pull-up drive stage PMOS transistor M1. The first NMOS transistor M6 pre-drive circuit of the gate pull-up pre-drive circuit 201 outputs a pre-drive signal HS_NG for the pull-up drive stage NMOS transistor M2. After both the pull-up drive stage PMOS transistor M1 and the pull-up drive stage NMOS transistor M2 are turned on, the drive current provided to the drive signal output terminal OUT is the source current I of the pull-up drive stage PMOS transistor M1. P and the source current I of the pull-up driver NMOS transistor M2 N Compared to existing technologies that only use PMOS transistors or NMOS transistors to build pull-up drive circuits, this technology can provide a large current that enables the power MOSFET to turn on quickly without requiring a large area of ​​circuitry (mainly large capacitors).

[0046] The gate pull-down pre-drive circuit 202 is designed as a second NMOS pre-drive circuit for the pull-down drive stage NMOS transistor M3. When it is necessary to turn off the power MOS transistor, the controller outputs a pull-down control signal. The second NMOS pre-drive circuit converts the pull-down control signal into a pre-drive signal LS_NG for the pull-down drive stage NMOS transistor M3. After the pull-down drive stage NMOS transistor M3 is turned on, the voltage at the drive signal output terminal OUT is quickly pulled to ground, thereby achieving rapid turn-off of the power MOS transistor.

[0047] Among them, the pull-up control signal and the pull-down control signal are the logic level signals output by the controller, which can be designed to be active high and inactive low.

[0048] In addition, in the power supply design, the gate driver of the power MOS tube provided in the embodiment of the application needs to provide a first direct current power supply VBB, a second direct current power supply AVDD and a floating ground signal source FGND. The first direct current power supply VBB is used as a power supply for providing a large current required for turning on the components. The second direct current power supply AVDD is used for providing a logic power supply for inverters and other components in the circuit. The floating ground signal source FGND is used for providing a floating ground signal for the pre-driver circuit of the PMOS tube. The floating ground voltage value of the floating ground signal source FGND is determined according to the voltage value of the first direct current power supply VBB and the parameters of the pull-up driving stage PMOS tube M1. For example, if a PMOS tube with a 5V gate voltage is used, the floating ground voltage value is designed as VBB-5V.

[0049] Embodiment two

[0050] In actual application, if the MOS tube in the gate pull-up pre-driver circuit 201 and the MOS tube in the gate pull-down pre-driver circuit 202 are turned on at the same time, a large current will be generated in the circuit and the components will be damaged. In order to avoid this problem, the pull-up control signal and the pull-down control signal need to be processed by non-overlapping. Specifically, the pull-up control signal and the pull-down control signal can be processed by non-overlapping in the controller, or can be realized by hardware.

[0051] Based on the above embodiment, as shown in Figure 2 the gate driver of the power MOS tube provided in the embodiment of the application can further include a signal non-overlapping processing module 203.

[0052] The signal input end of the signal non-overlapping processing module 203 is connected with the control signal output end of the controller. The first output end of the signal non-overlapping processing module 203 is connected with the input end of the gate pull-up pre-driver circuit 201. The second output end of the signal non-overlapping processing module 203 is connected with the input end of the gate pull-down pre-driver circuit 202.

[0053] In specific implementation, in order to facilitate control, the pull-up control signal and the pull-down control signal are provided by one control signal output end of the controller. For example, a high-level signal input to the signal input end of the signal non-overlapping processing module 203 can be designed as the pull-up control signal, and a low-level signal input to the signal input end of the signal non-overlapping processing module 203 can be designed as the pull-down control signal.

[0054] In order to increase the driving capability, as shown in Figure 2 the gate driver of the power MOS tube provided in the embodiment of the application can further include a first buffer B1. The input end of the first buffer B1 is connected with the control signal output end of the controller. The output end of the first buffer B1 is connected with the signal input end of the signal non-overlapping processing module 203. The power supply pin of the first buffer B1 is connected with the first direct current power supply VBB. The ground pin of the first buffer B1 is grounded.

[0055] Further, in order to realize the complete turn-off of the power MOS tube, the turn-off signal non-overlapping processing module 203 can be adopted, and in the power MOS tube gate driver provided in the embodiment of the present application, the enable end of the signal non-overlapping processing module 203 is connected with the enable signal output end of the controller.

[0056] Specifically, the enable signal non-overlapping processing module 203 is enabled by the high-level signal output from the enable signal output end of the controller, and the turn-off signal non-overlapping processing module 203 is disabled by the low-level signal output from the enable signal output end of the controller.

[0057] Embodiment three

[0058] Figure 3 A circuit diagram of the power MOS tube gate driver provided in the embodiment of the present application.

[0059] On the basis of the above-mentioned embodiment, in order to realize the output of the pre-drive signal HS_PG and the pre-drive signal HS_NG of the gate pull-up pre-drive circuit 201, in the power MOS tube gate driver provided in the embodiment of the present application, as shown in FIG. 2, the gate pull-up pre-drive circuit 201 specifically includes: a first inverter N1, a level conversion module U1, a PMOS tube pre-drive circuit and a first NMOS tube M6 pre-drive circuit. Figure 3

[0060] The input end of the first inverter N1 is connected with the pull-up signal output end of the controller, the output end of the first inverter N1 is connected with the input end of the level conversion module U1, the output end of the level conversion module U1 is connected with the input end of the PMOS tube pre-drive circuit and the input end of the first NMOS tube M6 pre-drive circuit, the output end of the PMOS tube pre-drive circuit is connected with the gate of the pull-up drive stage PMOS tube M1, and the output end of the first NMOS tube M6 pre-drive circuit is connected with the gate of the pull-up drive stage NMOS tube M2.

[0061] The level conversion module U1 is used to convert the pull-up control signal into the pull-up pre-drive signal with the amplitude varying from the floating ground voltage value to the first direct current source VBB voltage value.

[0062] The floating ground voltage value is determined according to the first direct current source VBB voltage value and the parameters of the pull-up drive stage PMOS tube M1.

[0063] In the specific implementation, the power pin of the first inverter N1 is connected with the second direct current source AVDD, and the ground pin of the first inverter N1 is grounded. The level conversion module U1 is used to convert the pull-up control signal into the pull-up pre-drive signal HS_IN_AFT with the amplitude varying from the floating ground voltage value to the first direct current source VBB voltage value. The design of the floating ground voltage value can refer to the first embodiment of the present application.​

[0064] To enhance the driving capability, the gate pull-up pre-drive circuit 201 may further include a second buffer B2. The input terminal of the second buffer B2 is connected to the output terminal of the level conversion module U1, the output terminal of the second buffer B2 is connected to the input terminal of the PMOS transistor pre-drive circuit and the input terminal of the first NMOS transistor M6 pre-drive circuit, the power supply pin of the second buffer B2 is connected to the first DC power supply VBB, and the ground pin of the second buffer B2 is connected to the floating ground signal source FGND.

[0065] The output signal HS_INN_AFT of the second buffer B2 is input to the PMOS transistor pre-drive circuit and the first NMOS transistor M6 pre-drive circuit, so as to be converted into the drive signal HS_PG and the pre-drive signal HS_NG, respectively.

[0066] Then as Figure 3 As shown, the PMOS transistor pre-drive circuit can be directly constructed using a third buffer B3 to enhance the driving capability. The input terminal of the third buffer B3 is connected to the output terminal of the level conversion module U1, and the output terminal of the third buffer B3 is connected to the gate of the pull-up drive stage PMOS transistor M1. The power supply pin of the third buffer B3 is connected to the first DC power supply VBB, and the ground pin of the third buffer B3 is connected to the floating ground signal source FGND. The PMOS transistor pre-drive circuit is activated when the pull-up control signal is high, and the pull-up current it can provide at this time is the source current I of the pull-up drive stage PMOS transistor M1. P .

[0067] Furthermore, the pre-drive circuit of the first NMOS transistor M6 may specifically include: a second inverter N2, a first capacitor C1, a first diode D1, a first PMOS transistor M4, and a first resistor R1;

[0068] The input terminal of the second inverter N2 is connected to the output terminal of the level conversion module U1, the output terminal of the second inverter N2 is connected to the first terminal of the first capacitor C1, the power supply pin of the second inverter N2 is connected to the second DC power supply AVDD, the ground pin of the second inverter N2 is connected to the floating ground signal source FGND, the anode of the first diode D1 and the gate of the first PMOS transistor M4 are connected to the first DC power supply VBB, the second terminal of the first capacitor C1 and the cathode of the first diode D1 are connected to the drain of the first PMOS transistor M4, the drain of the first PMOS transistor M4 and the first terminal of the first resistor R1 are connected to the gate of the pull-up driver stage NMOS transistor M2, and the second terminal of the first resistor R1 is grounded.

[0069] The first NMOS tube M6 pre-driver circuit is built by using a bootstrap circuit, and functions in the short time when the output HS_INP of the second inverter N2 is switched from the floating ground FGND to VBB. Assuming that the voltage change of HS_INP is ΔV, due to the existence of the first capacitor C1, the gate voltage of the pull-up driving stage NMOS tube M2 is pulled up to the potential of VBB+ΔV at this time, so that the pull-up driving stage NMOS tube M2 is opened in a short time and is close to the power supply rail. At this time, the pull-up current that can be provided by the pull-up driving stage NMOS tube M2 is the source current I N .

[0070] Based on this, at the moment when the pull-up control signal is converted to high level, the current that can be provided by the gate pull-up pre-driver circuit 201 to the driving signal output end OUT is I P +I N , which can shorten the Miller plateau caused by the Miller capacitor after the power MOS tube is opened.

[0071] Optionally, as shown in Figure 3 , the gate pull-down pre-driver circuit 202 can be directly built by using a fourth buffer B4; the input end of the fourth buffer B4 is connected with the pull-down signal output end, and the output end of the fourth buffer B4 is connected with the gate of the pull-down driving stage NMOS tube M3. The power supply pin of the fourth buffer B4 is connected with the second direct current power supply AVDD, and the grounding pin of the fourth buffer B4 is grounded. At the moment when the pull-down control signal is converted to high level, the pre-driver signal LS_NG after the driving enhancement by the fourth buffer B4 makes the pull-down driving stage NMOS tube M3 open, so as to realize the fast turn-off of the power MOS tube.

[0072] Embodiment Four

[0073] On the basis of the above-mentioned embodiments, since the bootstrap circuit is only used to pull up the gate voltage of the pull-up driving stage NMOS tube M2 from 0 to the potential of VBB+ΔV, a larger first capacitor C1 needs to be used. In order to further reduce the area occupied, in the power MOS tube gate driver provided in the embodiments of the present application, as shown in Figure 3 , the first NMOS tube M6 pre-driver circuit further includes a second PMOS tube M5 and a second diode D2.

[0074] The drain of the second PMOS tube M5 is connected with the first direct current power supply VBB, the gate of the second PMOS tube M5 is connected with the output end of the level conversion module U1, the source of the second PMOS tube M5 is connected with the anode of the second diode D2, and the cathode of the second diode D2 is connected with the source of the first PMOS tube M4.

[0075] In a specific implementation, the first NMOS transistor M6 pre-driver pull-up circuit is composed of the second PMOS transistor M5 and the second diode D2, the second NMOS transistor pre-driver pull-up circuit is composed of the second inverter N2, the first capacitor C1, the first diode D1 and the first PMOS transistor M4, so as to gradually pull up the gate voltage of the pull-up driving stage NMOS transistor M2. The first diode D1 is used to ensure that the drain voltage HS_BST of the first PMOS transistor M4 is not lower than VBB-V D , and at the same time, will not be back-irrigated to the first DC power supply VBB when being higher than VBB. The second diode D2 is used to avoid back-irrigation of the gate voltage HS_NG of the pull-up driving stage NMOS transistor M2 to the first DC power supply VBB when the gate voltage HS_NG of the pull-up driving stage NMOS transistor M2 is higher than VBB.

[0076] The power MOS transistor gate driver provided by the embodiment of the present application is used in the moment of the jump-up of the pull-up control signal, the second PMOS transistor M5 is turned on, and the gate voltage of the pull-up driving stage NMOS transistor M2 is pulled up from 0 to VBB-V D , V D , that is, the voltage drop of the diode (usually 0.7V). At this time, the second NMOS transistor pre-driver pull-up circuit only needs to pull up the gate voltage of the pull-up driving stage NMOS transistor M2 from VBB-V D to VBB+△V, which greatly reduces the size of the required first capacitor C1, and further reduces the area cost of the power MOS transistor gate driver.

[0077] When the gate voltage of the pull-up driving stage NMOS transistor M2 is higher than VBB-V D2 , the first NMOS transistor M6 pre-driver pull-up circuit no longer works, the drain voltage HS_BST of the first PMOS transistor M4 is charged to VBB+△V, and the power MOS transistor is quickly turned on. At this time, if the output voltage HS_INP of the second inverter N2 no longer changes, the gate voltage of the pull-up driving stage NMOS transistor M2 will be slowly discharged through the first resistor R1, and the discharge speed depends on the parasitic capacitance of the gate of the pull-up driving stage NMOS transistor M2 and the resistance value of the first resistor R1, until the gate voltage of the pull-up driving stage NMOS transistor M2 is reduced to VBB-V D . At this time, the gate voltage of the pull-up driving stage NMOS transistor M2 is maintained by the first NMOS transistor M6 pre-driver pull-up circuit, the pull-up driving stage NMOS transistor M2 is turned off, and the output current of the drive signal output end OUT becomes I P . At this time, only the output level needs to be maintained at the power supply rail VBB.

[0078] Further, the first NMOS transistor M6 pre-driver circuit can further include: the first NMOS transistor M6; a gate of the first NMOS transistor M6 is connected with an output end of the first inverter N1, a drain of the first NMOS transistor M6 is connected with a source of the first PMOS transistor M4, and a source of the first NMOS transistor M6 is grounded. When the pull-up control signal changes from high level to low level, the first NMOS transistor M6 is turned on and quickly releases the current of the first NMOS transistor M6 pre-driver circuit, thereby reducing the circuit loss of the first NMOS transistor M6 pre-driver circuit.

[0079] Embodiment five

[0080] The above describes various embodiments of the power MOS transistor gate driver, and on this basis, the application further discloses a power MOS transistor gate driving system corresponding to the power MOS transistor gate driver.

[0081] The power MOS transistor gate driving system provided by the embodiment of the application can include the power MOS transistor gate driver provided by any one of the above embodiments, and further include a controller.

[0082] The pull-up signal output end of the controller is connected with the input end of the gate pull-up pre-driver circuit of the power MOS transistor gate driver, and the pull-down signal output end of the controller is connected with the input end of the gate pull-down pre-driver circuit.

[0083] Since the embodiments of the power MOS transistor gate driving system part correspond to the embodiments of the power MOS transistor gate driver part, the embodiments of the power MOS transistor gate driving system part are described in the description of the embodiments of the power MOS transistor gate driver part, and are not described here.

[0084] The power MOS transistor gate driver and the power MOS transistor gate driving system provided by the application are described in detail above. The embodiments in the specification are described in a progressive manner, and each embodiment mainly describes the differences from other embodiments. The same or similar parts of each embodiment can be referred to. For the power MOS transistor gate driving system disclosed by the embodiments, since it corresponds to the power MOS transistor gate driver disclosed by the embodiments, the description is relatively simple, and the relevant parts are described in the power MOS transistor gate driver part. It should be pointed out that, for those skilled in the art, without departing from the principle of the application, the application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the application.

[0085] It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A power MOSFET gate driver, characterized by, The application relates to a gate pull-up pre-driver circuit, a gate pull-down pre-driver circuit, a pull-up driving stage PMOS tube, a pull-up driving stage NMOS tube and a pull-down driving stage NMOS tube. The input end of the gate pull-up pre-driver circuit is connected with the pull-up signal output end of a controller, the first output end of the gate pull-up pre-driver circuit is connected with the gate of the pull-up driving stage PMOS tube, the second output end of the gate pull-up pre-driver circuit is connected with the gate of the pull-up driving stage NMOS tube, and the drain of the pull-up driving stage PMOS tube and the drain of the pull-up driving stage NMOS tube are connected with a first direct current power supply. The input end of the gate pull-down pre-driver circuit is connected with the pull-down signal output end of the controller, and the output end of the gate pull-down pre-driver circuit is connected with the gate of the pull-down driving stage NMOS tube. The source of the pull-up driving stage PMOS tube, the source of the pull-up driving stage NMOS tube and the drain of the pull-down driving stage NMOS tube are connected to form a driving signal output end for the gate of a power MOS tube, and the source of the pull-down driving stage NMOS tube is connected with the ground. The gate pull-up pre-driver circuit specifically comprises a first inverter, a level conversion module, a PMOS tube pre-driver circuit and a first NMOS tube pre-driver circuit. The input end of the first inverter is connected with the pull-up signal output end of the controller, the output end of the first inverter is connected with the input end of the level conversion module, the output end of the level conversion module is connected with the input end of the PMOS tube pre-driver circuit and the input end of the first NMOS tube pre-driver circuit, the output end of the PMOS tube pre-driver circuit is connected with the gate of the pull-up driving stage PMOS tube, and the output end of the first NMOS tube pre-driver circuit is connected with the gate of the pull-up driving stage NMOS tube. The level conversion module is used for converting a pull-up control signal into a pull-up pre-driving signal with a floating ground voltage value to a first direct current power supply voltage value. The floating ground voltage value is determined according to the first direct current power supply voltage value and the parameters of the pull-up driving stage PMOS tube. The application further comprises a signal non-overlapping processing module.

2. The power MOS gate driver of claim 1, wherein, The signal input end of the signal non-overlapping processing module is connected with the control signal output end of the controller, the first output end of the signal non-overlapping processing module is connected with the input end of the gate pull-up pre-driver circuit, and the second output end of the signal non-overlapping processing module is connected with the input end of the gate pull-down pre-driver circuit. The enable end of the signal non-overlapping processing module is connected with the enable signal output end of the controller.

3. The power MOS gate driver of claim 2, wherein, The first NMOS tube pre-driver circuit specifically comprises a second inverter, a first capacitor, a first diode, a first PMOS tube and a first resistor.

4. The power MOS gate driver of claim 1, wherein, ​ The input end of the second inverter is connected with the output end of the level conversion module, the output end of the second inverter is connected with the first end of the first capacitor, the power supply pin of the second inverter is connected with the second DC power supply, the ground pin of the second inverter is connected with the floating ground signal source, the anode of the first diode and the gate of the first PMOS tube are connected with the first DC power supply, the second end of the first capacitor and the cathode of the first diode are connected with the drain of the first PMOS tube, the drain of the first PMOS tube and the first end of the first resistor are connected with the gate of the pull-up driving stage NMOS tube, and the second end of the first resistor is grounded.

5. The power MOS gate driver of claim 4, wherein, The first NMOS tube pre-driver circuit further comprises a second PMOS tube and a second diode. The drain of the second PMOS tube is connected with the first DC power supply, the gate of the second PMOS tube is connected with the output end of the level conversion module, and the source of the second PMOS tube is connected with the anode of the second diode.

6. The power MOS gate driver of claim 4, wherein, The first NMOS tube pre-driver circuit further comprises a first NMOS tube. The gate of the first NMOS tube is connected with the output end of the first inverter, the drain of the first NMOS tube is connected with the source of the first PMOS tube, and the source of the first NMOS tube is grounded.

7. The power MOS gate driver of claim 1, wherein, The PMOS tube pre-driver circuit is specifically a third buffer; The input end of the third buffer is connected with the output end of the level conversion module, the output end of the third buffer is connected with the gate of the pull-up driving stage PMOS tube, the power supply pin of the third buffer is connected with the first DC power supply, and the ground pin of the third buffer is connected with the floating ground signal source.

8. The power MOS gate driver of claim 1, wherein, The gate pull-down pre-driver circuit is specifically a fourth buffer; The input end of the fourth buffer is connected with the pull-down signal output end, and the output end of the fourth buffer is connected with the gate of the pull-down driving stage NMOS tube.

9. A power MOSFET gate drive system, comprising: The power MOS tube gate driver comprises the controller. The pull-up signal output end of the controller is connected with the input end of the gate pull-up pre-driver circuit of the power MOS tube gate driver, and the pull-down signal output end of the controller is connected with the input end of the gate pull-down pre-driver circuit.

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