Gate driver circuit, chip and electronic device

Abstract

The application provides a gate driver circuit, a chip and an electronic device, comprising: a high-side transmission sub-circuit, a low-side transmission sub-circuit and a logic transmission unit, the logic transmission unit is connected with the high-side transmission sub-circuit and the low-side transmission sub-circuit respectively, the low-side transmission sub-circuit comprises a low-side delay matching unit; the low-side delay matching unit comprises a first pulse generator, a delay submodule and a low-side pulse recovery module; the high-side transmission sub-circuit comprises a high-side pulse recovery module and a second pulse generator; the first pulse generator is connected with the low-side pulse recovery module through the delay submodule; the circuit structure of the low-side pulse recovery module is the same as that of the high-side pulse recovery module; the functional parameters of the first pulse generator and the second pulse generator are the same; and the low-side delay matching unit is used for matching the phase of the output signal of the low-side transmission sub-circuit with that of the high-side transmission sub-circuit. The application can make the high and low side output signals of the circuit have good delay matching.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more particularly to a gate driver circuit, chip, and electronic device. Background Technology

[0002] Gate driver chips enable smaller size, improved reliability, and enhanced stability in electronic products. With the advancements in power device technology and the rapid development of gate driver chip technology, the application areas of gate driver chips are gradually expanding. Gate driver chips can be widely used in fields such as power electronics, industrial control, defense, and automotive electronics, making it an important area of ​​research in the industry. Based on application scenarios, high-voltage gate driver chips can be divided into two categories: one category is used in motor control systems, primarily represented by industrial robots, industrial control equipment, home appliances, drones, and new energy transportation; the other category is used in power management systems, such as the gate driving of switching devices in DC-DC converters, primarily represented by display drivers, automotive charging equipment, and analog-to-digital (AC-DC) adapters.

[0003] Currently, in the classic circuit structure of gate driver chips, the gate driver chip includes a ground reference channel (LO) and a floating channel (HO). Because the signal in HO undergoes waveform changes after passing through a high-voltage level shifting circuit, a certain delay is generated. Therefore, a delay circuit needs to be introduced in the LO transmission path to ensure phase matching between the LO signal output from the low-side transmission path and the HO signal output from the high-side transmission path. The traditional method for achieving delay matching is to add an RC delay circuit to the low-side transmission path to compensate for the delay caused by the additional pulse generator, high-voltage level shifter, pulse width filter, and RS flip-flop in the high-side transmission path. RC delay achieves the delay effect by charging and discharging a capacitor, and its delay effect can be adjusted by changing the value of R or C. However, due to the simple structure of this RC delay circuit, it suffers from drawbacks such as short delay time and low accuracy. Furthermore, it is limited by the capacitor's storage capacity, and changes in manufacturing process, operating temperature, or circuit voltage can easily affect the delay matching accuracy. Simultaneously, the delay at voltage abrupt changes (rising and falling edges) will differ, causing a delay mismatch between the LO and HO signals, leading to circuit performance instability. Summary of the Invention

[0004] This invention provides a gate driver circuit, chip, and electronic device to solve the defect in the prior art where the delay mismatch between the low-side output LO signal and the high-side output HO signal caused by changes in manufacturing process, operating temperature, or circuit voltage leads to unstable circuit performance.

[0005] This invention provides a gate driver circuit, comprising:

[0006] A high-side transmission sub-circuit, a low-side transmission sub-circuit, and a logic transmission unit, wherein the logic transmission unit is connected to the high-side transmission sub-circuit and the low-side transmission sub-circuit, respectively;

[0007] The high-side transmission sub-circuit includes a high-side pulse recovery module and a second pulse generator;

[0008] The low-side transmission sub-circuit includes a low-side delay matching unit; the low-side delay matching unit includes a first pulse generator, a delay sub-module, and a low-side pulse recovery module;

[0009] The first pulse generator is connected to the low-side pulse recovery module through the delay submodule; the low-side pulse recovery module and the high-side pulse recovery module have the same circuit structure; the first pulse generator and the second pulse generator have the same functional parameters.

[0010] The low-side delay matching unit is used to delay the input signal of the low-side transmission sub-circuit so that the output signal of the low-side transmission sub-circuit is phase-matched with the output signal of the high-side transmission sub-circuit.

[0011] According to a gate driver circuit provided by the present invention, the high-side transmission sub-circuit further includes a level conversion module and a high-side gate driving module, and the low-side transmission sub-circuit further includes a low-side gate driving module.

[0012] The first input terminal of the logic transmission unit serves as the external high-side signal input terminal, and the second input terminal of the logic transmission unit serves as the external low-side signal input terminal.

[0013] The first output terminal of the logic transmission unit is connected to the input terminal of the second pulse generator, and is used to convert the first square wave signal output by the first output terminal of the logic transmission unit into a first rising edge narrow pulse signal and a first falling edge narrow pulse signal; the output terminal of the second pulse generator is connected to the high-side pulse recovery module through the level conversion module, and is used to convert the first rising edge narrow pulse signal and the first falling edge narrow pulse signal into a low-level narrow pulse signal, and to filter and restore the low-level narrow pulse signal to obtain the first square wave signal;

[0014] The output terminal of the high-side pulse recovery module is connected to the input terminal of the high-side gate drive module. The first output terminal of the high-side gate drive module serves as an external high-side signal output terminal, used to convert the first square wave signal into a high-side gate drive signal and output the high-side gate drive signal through the external high-side signal output terminal.

[0015] The second output terminal of the logic transmission unit is connected to the first input terminal of the first pulse generator, and is used to convert the second square wave signal output by the second output terminal of the logic transmission unit into a second rising edge narrow pulse signal and a second falling edge narrow pulse signal.

[0016] The first output terminal of the first pulse generator is connected to the first input terminal of the delay submodule, the second output terminal of the first pulse generator is connected to the second input terminal of the delay submodule, the first output terminal of the delay submodule is connected to the first input terminal of the low-side pulse recovery module, and the second output terminal of the delay submodule is connected to the second input terminal of the low-side pulse recovery module. This is used to delay the second rising edge narrow pulse signal and the second falling edge narrow pulse signal, and to filter and restore the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal to obtain the second square wave signal.

[0017] The first output terminal of the low-side pulse recovery module is connected to the first input terminal of the low-side gate drive module. The output terminal of the low-side gate drive module serves as an external low-side signal output terminal, used to convert the second square wave signal into a low-side gate drive signal and output the low-side gate drive signal through the external low-side signal output terminal.

[0018] The second input terminal of the first pulse generator, the third input terminal and the fourth input terminal of the low-side pulse recovery module are simultaneously connected to an external high-level input terminal;

[0019] The third output terminal of the first pulse generator, the third output terminal of the delay submodule, and the second and third output terminals of the low-side pulse recovery module are all connected to the external ground pin.

[0020] According to a gate driver circuit provided by the present invention, the low-side pulse recovery module includes a first pulse width filter and a first RS flip-flop; the first pulse width filter is used to filter out noise interference signals of the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal; the first RS flip-flop is used to restore the filtered second rising edge narrow pulse signal and the second falling edge narrow pulse signal into the second square wave signal;

[0021] The first output terminal of the first pulse width filter is connected to the first input terminal of the first RS flip-flop, and the second output terminal of the first pulse width filter is connected to the second input terminal of the first RS flip-flop.

[0022] The first input terminal of the low-side pulse recovery module is the first input terminal of the first pulse width filter, the second input terminal of the low-side pulse recovery module is the second input terminal of the first pulse width filter, and the third and fourth input terminals of the low-side pulse recovery module are the third input terminals of the first pulse width filter and the third input terminals of the first RS flip-flop, respectively.

[0023] The second output terminal of the low-side pulse recovery module is the third output terminal of the first pulse width filter, and the third output terminal of the low-side pulse recovery module is the second output terminal of the first RS flip-flop.

[0024] The first input terminal of the first pulse width filter is connected to the first output terminal of the delay submodule, and the second input terminal of the first pulse width filter is connected to the second output terminal of the delay submodule;

[0025] The third input terminal of the first pulse width filter is simultaneously connected to the third input terminal of the first RS flip-flop to the external high-level input terminal;

[0026] The third output terminal of the first pulse width filter and the second output terminal of the first RS flip-flop are connected to the external ground pin.

[0027] According to a gate driver circuit provided by the present invention, the first input terminal of the low-side gate driver module is connected to the first output terminal of the first RS flip-flop, and the second input terminal of the low-side gate driver module is simultaneously connected to the third input terminal of the first pulse width filter and the third input terminal of the first RS flip-flop to the external high-level input terminal.

[0028] According to a gate driver circuit provided by the present invention, the level conversion module includes a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor;

[0029] The source of the first NMOS transistor is connected to one end of the first resistor, the source of the second NMOS transistor is connected to one end of the second resistor, and the other ends of the first resistor and the other ends of the second resistor are both connected to an external high-voltage floating power supply terminal.

[0030] The drains of the first NMOS transistor and the second NMOS transistor are both grounded. The gate of the first NMOS transistor is connected to the first output terminal of the second pulse generator, and the gate of the second NMOS transistor is connected to the second output terminal of the second pulse generator.

[0031] According to a gate driver circuit provided by the present invention, the high-side pulse recovery module includes a second pulse width filter and a second RS flip-flop; the second pulse width filter is used to filter out noise interference signals in the low-level narrow pulse signal; the second RS flip-flop is used to restore the filtered low-level narrow pulse signal into the first square wave signal.

[0032] The first input terminal of the second pulse width filter is simultaneously connected to the source of the first NMOS transistor and one end of the first resistor; the second input terminal of the second pulse width filter is simultaneously connected to the source of the second NMOS transistor and one end of the second resistor.

[0033] The first output terminal of the second pulse width filter is connected to the first input terminal of the second RS flip-flop, and the second output terminal of the second pulse width filter is connected to the second input terminal of the second RS flip-flop.

[0034] The third output terminal of the second pulse width filter and the first output terminal of the second RS flip-flop are simultaneously connected to the external high-voltage floating power supply terminal.

[0035] The fourth output terminal of the second pulse width filter and the second output terminal of the second RS flip-flop are both connected to the external high-measurement floating ground terminal.

[0036] According to a gate driver circuit provided by the present invention, the input terminal of the high-side gate driving module is connected to the third output terminal of the second RS flip-flop, and the second output terminal of the high-side gate driving module is simultaneously connected to the third output terminal of the second pulse width filter, the first output terminal of the second RS flip-flop, the other end of the first resistor, and the other end of the second resistor to the external high-side floating power supply terminal.

[0037] The third output terminal of the high-side gate drive module is simultaneously connected to the fourth output terminal of the second pulse width filter and the second output terminal of the second RS flip-flop to the external high-side floating ground terminal.

[0038] According to a gate driver circuit provided by the present invention, the logic transmission unit includes a logic control module, a high-side NOR gate, a low-side NOR gate, a low-voltage lockout module, a high-side level shift circuit, a low-side level shift circuit, a high-side grounding resistor, and a low-side grounding resistor.

[0039] The input terminal of the high-side level shift circuit is connected to both the external high-side signal input terminal and one end of the high-side grounding resistor, while the other end of the high-side grounding resistor is grounded; the output terminal of the high-side level shift circuit is connected to the first input terminal of the logic control module.

[0040] The input terminal of the low-side level shift circuit is connected to both the external low-side signal input terminal and one end of the low-side grounding resistor, with the other end of the low-side grounding resistor grounded; the output terminal of the low-side level shift circuit is connected to the second input terminal of the logic control module; the first output terminal of the logic control module is connected to the first input terminal of the high-side NOR gate, and the second output terminal of the logic control module is connected to the first input terminal of the low-side NOR gate.

[0041] The input terminal of the low voltage lockout module is connected to an external high-level input terminal, and the output terminal of the low voltage lockout module is connected to the second input terminal of the high-side NOR gate and the second input terminal of the low-side NOR gate respectively. The output terminal of the high-side NOR gate serves as the first output terminal of the logic transmission unit, and the output terminal of the low-side NOR gate serves as the second output terminal of the logic transmission unit.

[0042] The present invention also provides a chip comprising the gate driver circuit described in any of the preceding claims.

[0043] The present invention also provides an electronic device comprising the chip described above.

[0044] The gate driver circuit, chip, and electronic device provided by this invention employ the same functional module in the low-side delay matching unit as in the high-side transmission sub-circuit, enabling the low-side delay matching unit to generate the same rising and falling edge transmission delays as the high-side output signal. This allows the output signal of the low-side transmission sub-circuit to be phase-matched with the output signal of the high-side transmission sub-circuit, effectively avoiding the inaccurate and unstable delay matching in the low-side transmission path of existing technologies. Furthermore, it ensures that the designed gate driver chip maintains good delay matching between the high and low-side output signals even when encountering changes in chip manufacturing process, operating temperature, or circuit voltage, greatly enhancing the stability of the chip. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a typical high-voltage half-bridge bootstrap gate driver chip in the existing technology.

[0047] Figure 2 This is a schematic diagram of a typical low-side path delay matching block in existing technology;

[0048] Figure 3 This is a schematic diagram of the transmission delay signal of a typical low-side path delay matching block in existing technology;

[0049] Figure 4 This is a schematic diagram of the high and low side transmission delay signals in a typical gate driver chip in existing technology;

[0050] Figure 5 This is a schematic block diagram of the gate driver circuit of the present invention;

[0051] Figure 6 yes Figure 5 The circuit diagram of the gate driver circuit of the present invention is shown below;

[0052] Figure 7 This is a schematic diagram of the high and low side transmission delay signals in the gate driver circuit of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0054] In the description of the invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0055] The following is combined Figures 1-7 This invention describes the gate driver circuit, chip, and electronic device.

[0056] Figure 1 This is a schematic diagram of a typical high-voltage half-bridge bootstrap gate driver chip in existing technology, such as... Figure 1 As shown, two NMOS devices are connected in series to form a typical half-bridge connection. The NMOS transistor whose drain is connected to a 600V high voltage is a high-side power device, and the NMOS transistor whose source is connected to ground is a low-side power device. The corresponding gate drive signals are the high-side drive HO signal and the low-side drive LO signal, respectively. The paths through which the signals pass are the high-side channel and the low-side channel, respectively. Figure 1The gate driver chip shown has 8 pins. VCC is the low-side power supply pin, which is the high-level input pin. VSS is the ground pin. HS is the high-side floating ground pin. HB is the high-side floating power supply pin. LIN and HIN are connected to the input signals of the control circuit and are the high-side and low-side input pins of the driver chip, respectively. HO and LO are connected to the gates of the high-side and low-side power devices, respectively, and are the high-side and low-side signal output pins of the driver chip.

[0057] The HS terminal is connected to the drain of the low-side power device. The high-voltage diode and the bootstrap capacitor form a bootstrap structure to achieve bootstrap power supply for the high-side circuit. In the initial transition state, the LO terminal outputs a high level, the HO terminal outputs a low level, the low-side power transistor is turned on, and the high-side power transistor is turned off. The HS terminal is pulled low. At this time, the VCC terminal charges the bootstrap capacitor through the high-voltage diode. Finally, the voltage difference HB-HS across the bootstrap capacitor is VCC voltage minus the diode forward voltage drop. In the second stage, the low-side power transistor is turned off, and then the high-side power transistor is turned on. At this time, the HS terminal floats to above 600V. Since the voltage across the capacitor cannot change abruptly, the voltage difference HB-HS across the bootstrap capacitor maintains VCC voltage minus the diode forward voltage drop. The HB terminal is the HS terminal plus VCC voltage minus the diode forward voltage drop. At this time, the current in the high-side region is provided by the charge stored across the bootstrap capacitor.

[0058] The gate driver chip includes a ground reference channel, led out from the LO terminal, and a floating channel, led out from the HO terminal. The LO is a fairly simple buffer, typically with the same ground point as the control input, while the HO is carefully designed and referenced to the switching node of a half-bridge, allowing the use of two N-channel MOSFETs or two IGBTs, dedicated to bootstrap or isolated power supply operation.

[0059] In the high-side transmission path, because the signal output from the HO terminal undergoes waveform changes via a high-voltage level shifting circuit, a certain delay is introduced. Therefore, a delay circuit needs to be introduced in the low-side transmission path where the LO terminal is located to ensure phase matching between the output signal from the LO terminal and the output signal from the HO terminal. Generally speaking, the smaller the delay, the better the circuit performance.

[0060] Figure 2 This is a schematic diagram of a typical low-side path delay matching block in existing technology, such as... Figure 2 As shown, existing methods for achieving delay matching compensate for the delay caused by the signal passing through the high-side path by adding an RC delay in the low-side transmission path. The RC delay is achieved by charging and discharging a capacitor, and its delay effect can be adjusted by changing the value of the resistor R or the capacitor C.

[0061] Figure 3This is a schematic diagram of the transmission delay signal of a typical low-side path delay matching block in existing technology, such as... Figure 3 As shown, by observing the input signal l0 and the output signal l1, it can be seen that the signal has a certain delay. However, due to the simple structure of this delay circuit, it has disadvantages such as short delay time and low accuracy, which can easily cause a delay mismatch between the output signal at the LO terminal and the output signal at the HO terminal, resulting in unstable circuit performance.

[0062] Figure 4 This is a schematic diagram of the high-side and low-side propagation delay signals in a typical gate driver chip in existing technology, such as... Figure 4 As shown, HIN is the high-side input signal terminal and LIN is the low-side input signal terminal. The HIN and LIN terminals are delayed after passing through the gate driver circuit. Among them, tpdr_h(l) is the delay generated by the signal at the rising edge of the voltage, and tpdf_h(l) is the delay generated by the signal at the falling edge of the voltage. It can be seen that the delay generated by the signal at the rising edge and the falling edge is different, and the output signal of the LO terminal is not matched with the output signal of the HO terminal.

[0063] Therefore, the present invention provides a gate driver circuit to solve the technical defects mentioned in the prior art.

[0064] Figure 5 This is a schematic block diagram of the gate driver circuit of the present invention, as shown below. Figure 5 As shown, the gate driver circuit 4 includes:

[0065] The system comprises a high-side transmission sub-circuit 1, a low-side transmission sub-circuit 2, and a logic transmission unit 3. The logic transmission unit 3 is connected to both the high-side transmission sub-circuit 1 and the low-side transmission sub-circuit 2. The low-side transmission sub-circuit 2 includes a low-side delay matching unit 21. The low-side delay matching unit 21 includes a first pulse generator 211, a delay sub-module 212, and a low-side pulse recovery module 213.

[0066] The high-side transmission sub-circuit 1 includes a high-side pulse recovery module 11 and a second pulse generator 12;

[0067] The first pulse generator 211 is connected to the low-side pulse recovery module 213 through the delay sub-module 212; the low-side pulse recovery module 213 has the same circuit structure as the high-side pulse recovery module 11 in the high-side transmission sub-circuit 1; the first pulse generator 211 has the same functional parameters as the second pulse generator 12 in the high-side transmission sub-circuit 1.

[0068] The low-side delay matching unit 21 is used to delay the input signal of the low-side transmission sub-circuit 2 so that the output signal of the low-side transmission sub-circuit 2 is phase-matched with the output signal of the high-side transmission sub-circuit 1.

[0069] Specifically, in the embodiments of the present invention, the gate driver circuit of the present invention belongs to a high-voltage half-bridge gate driver circuit with delay matching. By adopting an improved low-side delay matching unit 21, the low-side transmission sub-circuit 2 and the high-side transmission sub-circuit 1 have similar circuit structures. The same rising edge and falling edge transmission delay as the high-side HO terminal output signal are achieved by using a similar transmission method on the low-side transmission path as on the high-side transmission path.

[0070] In the embodiments of the present invention, the low-side pulse recovery module 213 and the high-side pulse recovery module 11 in the high-side transmission sub-circuit 1 have the same circuit structure. That is to say, the low-side pulse recovery module 213 and the high-side pulse recovery module 11 are the same type of module, and their functional parameters and internal circuit structures are the same.

[0071] In an embodiment of the present invention, the low-side delay matching unit 21 includes a first pulse generator 211, a delay submodule 212, and a low-side pulse recovery module 213. The internal connection is such that the first pulse generator 211 is connected to the low-side pulse recovery module 213 through the delay submodule 212. The low-side pulse recovery module 213 has the same circuit structure as the high-side pulse recovery module 11 in the high-side transmission subcircuit 1. The first pulse generator 211 has the same functional parameters as the second pulse generator 12 in the high-side transmission subcircuit 1, thereby realizing a transmission mode in which the low-side transmission path is similar to the high-side transmission path.

[0072] Meanwhile, for the delay caused by the high-voltage level conversion in the high-side transmission sub-circuit 1, the delay sub-module 212 in the low-side path can be simulated by an equivalent RC delay circuit to achieve a transmission delay similar to that in the high-side transmission sub-circuit 1. This can reduce the impact of external environment such as temperature on the chip's transmission delay matching effect and enhance the chip's stability.

[0073] The gate driver circuit provided in this embodiment of the invention employs the same functional module in the low-side delay matching unit 21 as in the high-side transmission sub-circuit 1, enabling the low-side delay matching unit 21 to generate the same rising and falling edge transmission delays as the high-side output signal. This allows the output signal of the low-side transmission sub-circuit 2 to be phase-matched with the output signal of the high-side transmission sub-circuit 1, effectively avoiding the inaccurate and unstable delay matching in the low-side transmission path of the prior art. Furthermore, it ensures that the designed gate driver chip maintains good delay matching between the high and low side output signals even when encountering changes in chip manufacturing process, operating temperature, or circuit voltage, greatly enhancing the stability of the chip.

[0074] Figure 6 yes Figure 5 The circuit diagram of the gate driver circuit of the present invention shown is as follows: Figure 5 and Figure 6As shown, the high-side transmission sub-circuit 1 also includes a level conversion module 13 and a high-side gate driver module 14, and the low-side transmission sub-circuit 2 also includes a low-side gate driver module 22.

[0075] The first input terminal 30 of the logic transmission unit 3 is used as the external high-side signal input terminal HIN, and the second input terminal 39 of the logic transmission unit 3 is used as the external low-side signal input terminal LIN.

[0076] The first output terminal of the logic transmission unit 3 is connected to the input terminal of the second pulse generator 12, and is used to convert the first square wave signal output from the first output terminal of the logic transmission unit 3 into a first rising edge narrow pulse signal and a first falling edge narrow pulse signal.

[0077] The output of the second pulse generator 12 is connected to the high-side pulse recovery module 11 through the level conversion module 13. It is used to convert the first rising edge narrow pulse signal and the first falling edge narrow pulse signal into a low-level narrow pulse signal relative to the high-voltage side floating power supply voltage, and to filter and restore the low-level narrow pulse signal to obtain the first square wave signal.

[0078] The output terminal of the high-side pulse recovery module 11 is connected to the input terminal of the high-side gate drive module 14. The first output terminal of the high-side gate drive module 14 serves as the external high-side signal output terminal HO, which is used to convert the obtained first square wave signal into a high-side gate drive signal and output the high-side gate drive signal through the external high-side signal output terminal HO to drive the external high-side power transistor.

[0079] The second output terminal of the logic transmission unit 3 is connected to the first input terminal of the first pulse generator 211, and is used to convert the second square wave signal output by the second output terminal of the logic transmission unit 3 into a second rising edge narrow pulse signal and a second falling edge narrow pulse signal.

[0080] The first output terminal of the first pulse generator 211 is connected to the first input terminal of the delay submodule (RC delay) 212, the second output terminal of the first pulse generator 211 is connected to the second input terminal of the delay submodule 212, the first output terminal of the delay submodule 212 is connected to the first input terminal of the low-side pulse recovery module 213, and the second output terminal of the delay submodule 212 is connected to the second input terminal of the low-side pulse recovery module 213. This is used to delay the second rising edge narrow pulse signal and the second falling edge narrow pulse signal, and to filter and restore the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal to obtain the second square wave signal.

[0081] The first output terminal of the low-side pulse recovery module 213 is connected to the first input terminal of the low-side gate drive module 22. The output terminal of the low-side gate drive module 22 serves as the external low-side signal output terminal LO, which is used to convert the second square wave signal into a low-side gate drive signal and output the low-side gate drive signal through the external low-side signal output terminal to drive the external low-side power transistor, thereby improving the overall operating speed of the chip.

[0082] The second input terminal of the first pulse generator 211, the third input terminal and the fourth input terminal of the low-side pulse recovery module 213 are simultaneously connected to the external high-level input terminal VCC;

[0083] The third output terminal of the first pulse generator 211, the third output terminal of the delay submodule 212, and the second and third output terminals of the low-side pulse recovery module 213 are simultaneously connected to the external ground pin VSS.

[0084] The circuit of this embodiment of the invention provides a signal channel for signal input on the high-side and low-side transmission paths of the gate driver circuit by connecting the logic transmission unit 3 to the high-side transmission sub-circuit 1 and the low-side transmission sub-circuit 2 respectively.

[0085] Optionally, continue to refer to Figure 6 ,like Figure 6 As shown, the level conversion module 13 includes a first NMOS transistor 131, a second NMOS transistor 132, a first resistor 133, and a second resistor 134;

[0086] The source of the first NMOS transistor 131 is connected to one end of the first resistor 133, the source of the second NMOS transistor 132 is connected to one end of the second resistor 134, and the other ends of the first resistor 133 and the second resistor 134 are both connected to the external high-measurement floating power supply terminal HB.

[0087] The drains of the first NMOS transistor 131 and the second NMOS transistor 132 are both grounded. The gate of the first NMOS transistor 131 is connected to the first output terminal of the second pulse generator 12, and the gate of the second NMOS transistor 132 is connected to the second output terminal of the second pulse generator 12.

[0088] In this embodiment, the level conversion module 13 is used to transmit whether the output should be high or low. One output is the HB port of the chip, and the other output is connected to the high-side pulse recovery module 11.

[0089] The circuit of this invention implements level conversion function by using a connection circuit of two NMOS transistors and two resistors, which can efficiently realize the conversion between high and low levels between circuit modules in different operating voltage domains.

[0090] Optionally, continue to refer to Figure 6,like Figure 6 As shown, the high-side pulse recovery module 11 includes a second pulse width filter 111 and a second RS latch 112; the second pulse width filter 111 is used to filter out noise interference signals in the aforementioned low-level narrow pulse signal, thereby avoiding false triggering of subsequent circuits; the second RS latch 112 is used to restore the filtered low-level narrow pulse signal into a first square wave signal.

[0091] The first input terminal of the second pulse width filter 111 is simultaneously connected to the source of the first NMOS transistor 131 and one end of the first resistor 133; the second input terminal of the second pulse width filter 111 is simultaneously connected to the source of the second NMOS transistor 132 and one end of the second resistor 134.

[0092] The first output terminal of the second pulse width filter 111 is connected to the first input terminal of the second RS flip-flop 112, and the second output terminal of the second pulse width filter 111 is connected to the second input terminal of the second RS flip-flop 112.

[0093] The third output terminal of the second pulse width filter 111 and the first output terminal of the second RS flip-flop 112 are simultaneously connected to the external high-voltage floating power supply terminal HB.

[0094] The fourth output terminal of the second pulse width filter 111 and the second output terminal of the second RS flip-flop 112 are simultaneously connected to the external high-measurement floating ground terminal HS.

[0095] The circuit of this embodiment of the invention uses a pulse width filter and an RS flip-flop to form a high-side pulse recovery module 11, which receives the signal output by the level conversion module 13 and performs signal registration processing to ensure the stability of signal transmission.

[0096] Optionally, continue to refer to Figure 6 ,like Figure 6 As shown, the low-side pulse recovery module 213 includes a first pulse width filter 2131 and a first RS latch 2132; the first pulse width filter 2131 is used to filter out noise interference signals in the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal to avoid false triggering of the subsequent circuit; the first RS latch 2132 is used to restore the filtered second rising edge narrow pulse signal and the second falling edge narrow pulse signal into a second square wave signal;

[0097] The first output terminal of the first pulse width filter 2131 is connected to the first input terminal of the first RS flip-flop 2132, and the second output terminal of the first pulse width filter 2131 is connected to the second input terminal of the first RS flip-flop 2132.

[0098] The first input terminal of the low-side pulse recovery module 213 is the first input terminal of the first pulse width filter 2131, the second input terminal of the low-side pulse recovery module 213 is the second input terminal of the first pulse width filter 2131, and the third and fourth input terminals of the low-side pulse recovery module 213 are the third input terminals of the first pulse width filter 2131 and the third input terminals of the first RS flip-flop 2132, respectively.

[0099] The second output terminal of the low-side pulse recovery module 213 is the third output terminal of the first pulse width filter 2131, and the third output terminal of the low-side pulse recovery module 213 is the second output terminal of the first RS flip-flop 2132.

[0100] The first input terminal of the first pulse width filter 2131 is connected to the first output terminal of the delay submodule 212, and the second input terminal of the first pulse width filter 2131 is connected to the second output terminal of the delay submodule 212.

[0101] The third input terminal of the first pulse width filter 2131 is simultaneously connected to the external high-level input terminal VCC along with the third input terminal of the first RS flip-flop 2132.

[0102] The third output terminal of the first pulse width filter 2131 and the second output terminal of the first RS flip-flop 2132 are connected to the external ground pin VSS.

[0103] In this embodiment, the low-side pulse recovery module 213 and the high-side pulse recovery module 11 have the same structure, both consisting of a pulse width filter and an RS flip-flop. Furthermore, the first pulse width filter 2131 in the low-side pulse recovery module 213 and the second pulse width filter 111 in the high-side pulse recovery module 111 have the same functional parameters, as do the first RS flip-flop 2132 in the low-side pulse recovery module 213 and the second RS flip-flop 112 in the high-side pulse recovery module 111.

[0104] The circuit of this embodiment of the invention adopts the same circuit structure as the high-side pulse recovery module 11 in the low-side pulse recovery module 213 of the low-side transmission sub-circuit 2, and uses functional devices with the same functional parameters. This helps to reduce the difference in the transmission delay of the rising and falling edges generated on the high and low side transmission paths, and improves the matching effect of the output signal transmission delay between the low-side transmission sub-circuit 2 and the high-side transmission sub-circuit 1.

[0105] Optionally, continue to refer to Figure 6 ,like Figure 6As shown, the first input terminal of the low-side gate drive module 22 is connected to the first output terminal of the first RS flip-flop 2132, and the second input terminal of the low-side gate drive module 22 is connected to the external high-level input terminal VCC via the third input terminal of the first pulse width filter 2131 and the third input terminal of the first RS flip-flop 2132.

[0106] In the circuit of this embodiment of the invention, by connecting the first input terminal of the low-side gate driving module 22 to the first output terminal of the first RS flip-flop 2132, the low-side gate driving module 22 can receive the output delay signal of the low-side transmission sub-circuit 2 and transmit the low-side output delay signal to the outside of the chip.

[0107] Based on the above embodiments, as an optional embodiment, the input terminal of the high-side gate drive module 14 is connected to the third output terminal of the second RS flip-flop 112, and the second output terminal of the high-side gate drive module 14 is simultaneously connected to the third output terminal of the second pulse width filter 111, the first output terminal of the second RS flip-flop 112, the other end of the first resistor 133, and the other end of the second resistor 134 to the external high-side floating power supply terminal HB.

[0108] The third output terminal of the high-side gate drive module 14 is connected to the external high-side floating ground terminal HS, along with the fourth output terminal of the second pulse width filter 111 and the second output terminal of the second RS flip-flop 112.

[0109] The circuit of this embodiment of the invention receives the output delay signal of the high-side transmission sub-circuit 1 through the high-side gate driving module 14 and transmits the high-side output delay signal to the outside of the chip.

[0110] Optionally, continue to refer to Figure 6 ,like Figure 6 As shown, the logic transmission unit 3 may specifically include a logic control module (Logic(Dead Time)) 31, a high-side NOR gate 32, a low-side NOR gate 33, an under voltage lockout module (Under Voltage Lock Out, UVLO) 34, a high-side level shift circuit 35, a low-side level shift circuit 36, a high-side grounding resistor 37, and a low-side grounding resistor 38.

[0111] The input terminal of the high-side level shift circuit 35 is connected to both the external high-side signal input terminal HIN and one end of the high-side grounding resistor 37, while the other end of the high-side grounding resistor 37 is grounded; the output terminal of the high-side level shift circuit 35 is connected to the first input terminal of the logic control module 31.

[0112] The input terminal of the low-side level shifting circuit 36 ​​is simultaneously connected to both the external low-side signal input terminal LIN and one end of the low-side grounding resistor 38, while the other end of the low-side grounding resistor 38 is grounded;

[0113] The output of the side-level shift circuit 36 ​​is connected to the second input of the logic control module 31; the first output of the logic control module 31 is connected to the first input of the high-side NOR gate 32.

[0114] The second output of the logic control module 31 is connected to the first input of the low-side NOR gate 33;

[0115] The input terminal of the low-voltage lockout module 34 is connected to the external high-level input terminal VCC, and the output terminal of the low-voltage lockout module 34 is connected to the second input terminal of the high-side NOR gate 32 and the low-side NOR gate 32, respectively.

[0116] The second input terminal of NOR gate 33 is connected, the output terminal of high-side NOR gate 32 serves as the first output terminal of logic transmission unit 3, and the output terminal of low-side NOR gate 33 serves as the second output terminal of logic transmission unit 3.

[0117] In this embodiment, the input to the low-voltage lockout module 34 is a high-level VCC signal, which is input from outside the chip. Its output, along with the two outputs of the logic control module 31, is output separately.

[0118] Two NOR gates are used to ensure that the chip will not activate until the battery voltage reaches the safe operating voltage.

[0119] In this embodiment, the output signal h0 of the high-side NOR gate 32 and the output signal l0 of the low-side NOR gate 33 are respectively input to the second pulse generator 12 and the first pulse generator 211.

[0120] In this embodiment, the high-side grounding resistor 37 and the low-side grounding resistor 38 can be used as input pull-down resistors, which can ensure that the input voltage is pulled down to ground when the input pin is floating.

[0121] This results in a low output state, rather than an uncertain output state.

[0122] Both the high-side level shift circuit 35 and the low-side level shift circuit 36 ​​can use Schmitt triggers. By inputting the input signal into the Schmitt trigger and designing the flip-flop threshold and hysteresis window of the Schmitt trigger, the high and low levels of the input signal and noise suppression can be achieved.

[0123] 5. The logic control module 31 can employ a dead time generator, through the above...

[0124] The outputs of the high-side and low-side Schmitt triggers are connected to a dead-time generator. A certain dead time is added between the high-side and low-side input signals to ensure that the high-side and low-side outputs of the gate driver are not simultaneously high. This ensures that the upper and lower power transistors of the externally driven half-bridge will not conduct in series, resulting in a large current and ensuring circuit safety.

[0125] The low voltage lockout module 34 uses an undervoltage lockout circuit to detect the voltage value of the input power supply. When the power supply voltage is lower than the normal operating voltage, it may cause malfunctions in the circuit of the chip. At this time, a high level is output. Then, through the high-side NOR gate 32 and the low-side NOR gate 33 connected thereafter, the high and low side input signals are shielded, so that the high and low sides of the logic transmission unit 3 finally output a low-state square wave signal.

[0126] Figure 7 This is a schematic diagram of the high-side and low-side propagation delay signals in the gate driver circuit of the present invention, as shown below. Figure 7 As shown, assume the signal input to the second pulse generator 12 in the high-side transmission sub-circuit 1 is h0, the signal input to the first pulse generator 211 in the low-side transmission sub-circuit 2 is l0, the signal output from the high-side pulse recovery module 11 is h1, and the signal output from the low-side pulse recovery module 213 is l1. The input signals h0 and l0 are delayed after passing through the pulse generators. Then, the high-side signal passes through the level conversion module 13, and the low-side signal passes through the delay sub-module 212, both experiencing the same delay. Afterward, the signals pass through their respective pulse width filters and RS flip-flops to obtain the high-side output signal h1 and the low-side output signal l1. Figure 7 In this context, tpdrx represents the rising edge delay from the input signal h0 (l0) to the output signal h1 (l1), and tpdfx represents the falling edge delay from the input signal h0 (l0) to the output signal h1 (l1). It can be seen that the delays tpdrx and tpdfx generated by the signal at the rising and falling edges are the same, and the delays of the output signal at the LO terminal and the output signal at the HO terminal are matched.

[0127] In the circuit of this embodiment, the logic transmission unit 3 is composed of a logic control module 31, a high-side NOR gate 32, a low-side NOR gate 33, a low-voltage lockout module 34, a high-side level shift circuit 35, a low-side level shift circuit 36, a high-side grounding resistor 37, and a low-side grounding resistor 38, which provides input signal channels for the high-side transmission sub-circuit 1 and the low-side transmission sub-circuit 2, and can effectively improve the stability of chip operation.

[0128] On the other hand, the present invention also provides a chip comprising the gate driver circuit described above. The circuit includes a high-side transmission sub-circuit 1, a low-side transmission sub-circuit 2, and a logic transmission unit 3, wherein the logic transmission unit 3 is connected to both the high-side transmission sub-circuit 1 and the low-side transmission sub-circuit 2. The low-side transmission sub-circuit 2 includes a low-side delay matching unit 21. The low-side delay matching unit 21 includes a first pulse generator 211, a delay sub-module 212, and a low-side pulse recovery module 213. The high-side transmission sub-circuit 1 includes a high-side pulse recovery module 11. The first pulse generator 211 is connected to the low-side pulse recovery module 213 via the delay submodule 212. The low-side pulse recovery module 213 has the same circuit structure as the high-side pulse recovery module 11. The first pulse generator 211 has the same functional parameters as the second pulse generator 12. The low-side delay matching unit 21 is used to delay the input signal of the low-side transmission subcircuit 2 so that the output signal of the low-side transmission subcircuit 2 is phase-matched with the output signal of the high-side transmission subcircuit 1.

[0129] On the other hand, the present invention also provides an electronic device comprising the chip described above.

[0130] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driver circuit, characterized in that, include: The high-side transmission sub-circuit (1), the low-side transmission sub-circuit (2), and the logic transmission unit (3) are provided. The first input terminal (30) of the logic transmission unit (3) serves as the external high-side signal input terminal, and the second input terminal (39) of the logic transmission unit (3) serves as the external low-side signal input terminal. The logic transmission unit (3) includes a logic control module (31) to add a certain dead time between the high-side and low-side input signals. The first output terminal of the logic transmission unit (3) is connected to the high-side transmission sub-circuit (1), and the second output terminal of the logic transmission unit (3) is connected to the low-side transmission sub-circuit (2). The low-side transmission sub-circuit (2) includes a low-side delay matching unit (21); the low-side delay matching unit (21) includes a first pulse generator (211), a delay sub-module (212), and a low-side pulse recovery module (213). The high-side transmission sub-circuit (1) includes a high-side pulse recovery module (11) and a second pulse generator (12); The first pulse generator (211) is connected to the low-side pulse recovery module (213) through the delay submodule (212); both the low-side pulse recovery module (213) and the high-side pulse recovery module (11) are composed of a pulse width filter and an RS flip-flop, and the first pulse width filter (2131) in the low-side pulse recovery module (213) and the second pulse width filter (111) in the high-side pulse recovery module (11) have the same functional parameters, the first RS flip-flop (2132) in the low-side pulse recovery module (213) and the second RS flip-flop (112) in the high-side pulse recovery module (11) have the same functional parameters; the first pulse generator (211) and the second pulse generator (12) have the same functional parameters. The delay submodule (212) adopts an RC delay circuit. The delay generated by the RC delay circuit matches the equivalent transmission delay of the level conversion module (13) in the high-side transmission subcircuit (1), so that the transmission delay of the output signal of the low-side transmission subcircuit (2) and the output signal of the high-side transmission subcircuit (1) are equal on both the rising and falling edges.

2. The gate driver circuit according to claim 1, characterized in that, The high-side transmission sub-circuit (1) further includes a level conversion module (13) and a high-side gate driving module 14, and the low-side transmission sub-circuit (2) further includes a low-side gate driving module (22). The first output terminal of the logic transmission unit (3) is connected to the input terminal of the second pulse generator (12) to convert the first square wave signal output by the first output terminal of the logic transmission unit (3) into a first rising edge narrow pulse signal and a first falling edge narrow pulse signal; the output terminal of the second pulse generator (12) is connected to the high-side pulse recovery module (11) through the level conversion module (13) to convert the first rising edge narrow pulse signal and the first falling edge narrow pulse signal into a low-level narrow pulse signal, and to filter and restore the low-level narrow pulse signal to obtain the first square wave signal; The output terminal of the high-side pulse recovery module (11) is connected to the input terminal of the high-side gate drive module (14). The first output terminal of the high-side gate drive module (14) serves as an external high-side signal output terminal, used to convert the first square wave signal into a high-side gate drive signal and output the high-side gate drive signal through the external high-side signal output terminal. The second output terminal of the logic transmission unit (3) is connected to the first input terminal of the first pulse generator (211) to convert the second square wave signal output by the second output terminal of the logic transmission unit (3) into a second rising edge narrow pulse signal and a second falling edge narrow pulse signal. The first output terminal of the first pulse generator (211) is connected to the first input terminal of the delay submodule (212), the second output terminal of the first pulse generator (211) is connected to the second input terminal of the delay submodule (212), the first output terminal of the delay submodule (212) is connected to the first input terminal of the low-side pulse recovery module (213), and the second output terminal of the delay submodule (212) is connected to the second input terminal of the low-side pulse recovery module (213). This is used to delay the second rising edge narrow pulse signal and the second falling edge narrow pulse signal, and to filter and restore the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal to obtain the second square wave signal. The first output terminal of the low-side pulse recovery module (213) is connected to the first input terminal of the low-side gate drive module (22). The output terminal of the low-side gate drive module (22) serves as an external low-side signal output terminal, used to convert the second square wave signal into a low-side gate drive signal, and output the low-side gate drive signal through the external low-side signal output terminal. The second input terminal of the first pulse generator (211), the third input terminal and the fourth input terminal of the low-side pulse recovery module (213) are simultaneously connected to an external high-level input terminal; The third output terminal of the first pulse generator (211), the third output terminal of the delay submodule (212), and the second and third output terminals of the low-side pulse recovery module (213) are all connected to the external ground pin.

3. The gate driver circuit according to claim 2, characterized in that, The low-side pulse recovery module (213) includes a first pulse width filter (2131) and a first RS flip-flop (2132); the first pulse width filter (2131) is used to filter out noise interference signals of the delayed second rising edge narrow pulse signal and the second falling edge narrow pulse signal; the first RS flip-flop (2132) is used to restore the filtered second rising edge narrow pulse signal and the second falling edge narrow pulse signal into the second square wave signal; The first output terminal of the first pulse width filter (2131) is connected to the first input terminal of the first RS flip-flop (2132), and the second output terminal of the first pulse width filter (2131) is connected to the second input terminal of the first RS flip-flop (2132). The first input terminal of the low-side pulse recovery module (213) is the first input terminal of the first pulse width filter (2131), the second input terminal of the low-side pulse recovery module (213) is the second input terminal of the first pulse width filter (2131), and the third and fourth input terminals of the low-side pulse recovery module (213) are the third input terminal of the first pulse width filter (2131) and the third input terminal of the first RS flip-flop (2132), respectively. The second output terminal of the low-side pulse recovery module (213) is the third output terminal of the first pulse width filter (2131), and the third output terminal of the low-side pulse recovery module (213) is the second output terminal of the first RS flip-flop (2132). The first input terminal of the first pulse width filter (2131) is connected to the first output terminal of the delay submodule (212), and the second input terminal of the first pulse width filter (2131) is connected to the second output terminal of the delay submodule (212). The third input terminal of the first pulse width filter (2131) is simultaneously connected to the third input terminal of the first RS flip-flop (2132) to the external high-level input terminal; The third output terminal of the first pulse width filter (2131) and the second output terminal of the first RS flip-flop (2132) are connected to the external ground pin terminal.

4. The gate driver circuit according to claim 3, characterized in that, The first input terminal of the low-side gate drive module (22) is connected to the first output terminal of the first RS flip-flop (2132), and the second input terminal of the low-side gate drive module (22) is connected to the external high-level input terminal along with the third input terminal of the first pulse width filter (2131) and the third input terminal of the first RS flip-flop (2132).

5. The gate driver circuit according to claim 2, characterized in that, The level conversion module (13) includes a first NMOS transistor (131), a second NMOS transistor (132), a first resistor (133), and a second resistor (134). The drain of the first NMOS transistor (131) is connected to one end of the first resistor (133), the drain of the second NMOS transistor (132) is connected to one end of the second resistor (134), and the other ends of the first resistor (133) and the second resistor (134) are both connected to the external high-voltage floating power supply terminal. The source of the first NMOS transistor (131) and the source of the second NMOS transistor (132) are both grounded. The gate of the first NMOS transistor (131) is connected to the first output terminal of the second pulse generator (12), and the gate of the second NMOS transistor (132) is connected to the second output terminal of the second pulse generator (12).

6. The gate driver circuit according to claim 5, characterized in that, The high-side pulse recovery module (11) includes a second pulse width filter (111) and a second RS flip-flop (112); the second pulse width filter (111) is used to filter out noise interference signals in the low-level narrow pulse signal; the second RS flip-flop (112) is used to restore the filtered low-level narrow pulse signal into the first square wave signal. The first input terminal of the second pulse width filter (111) is simultaneously connected to the drain of the first NMOS transistor (131) and one end of the first resistor (133); the second input terminal of the second pulse width filter (111) is simultaneously connected to the drain of the second NMOS transistor (132) and one end of the second resistor (134); The first output terminal of the second pulse width filter (111) is connected to the first input terminal of the second RS flip-flop (112), and the second output terminal of the second pulse width filter (111) is connected to the second input terminal of the second RS flip-flop (112). The third output terminal of the second pulse width filter (111) and the first output terminal of the second RS flip-flop (112) are simultaneously connected to the external high-voltage floating power supply terminal; The fourth output terminal of the second pulse width filter (111) and the second output terminal of the second RS flip-flop (112) are simultaneously connected to the external high-voltage floating ground terminal.

7. The gate driver circuit according to claim 6, characterized in that, The input terminal of the high-side gate drive module (14) is connected to the third output terminal of the second RS flip-flop (112). The second output terminal of the high-side gate drive module (14) is simultaneously connected to the third output terminal of the second pulse width filter (111), the first output terminal of the second RS flip-flop (112), the other end of the first resistor (133), and the other end of the second resistor (134) to the external high-side floating power supply terminal. The third output terminal of the high-side gate drive module (14) is connected to the external high-side floating ground terminal along with the fourth output terminal of the second pulse width filter (111) and the second output terminal of the second RS flip-flop (112).

8. The gate driver circuit according to any one of claims 2-7, characterized in that, The logic transmission unit (3) includes a logic control module (31), a high-side NOR gate (32), a low-side NOR gate (33), a low-voltage lockout module (34), a high-side level shift circuit (35), a low-side level shift circuit (36), a high-side grounding resistor (37), and a low-side grounding resistor (38). The input terminal of the high-side level shift circuit (35) is connected to both the external high-side signal input terminal and one end of the high-side grounding resistor (37), and the other end of the high-side grounding resistor (37) is grounded; the output terminal of the high-side level shift circuit (35) is connected to the first input terminal of the logic control module (31); The input terminal of the low-side level shift circuit (36) is connected to both the external low-side signal input terminal and one end of the low-side grounding resistor (38), and the other end of the low-side grounding resistor (38) is grounded; the output terminal of the low-side level shift circuit (36) is connected to the second input terminal of the logic control module (31); the first output terminal of the logic control module (31) is connected to the first input terminal of the high-side NOR gate (32), and the second output terminal of the logic control module (31) is connected to the first input terminal of the low-side NOR gate (33); The input terminal of the low voltage lockout module (34) is connected to an external high-level input terminal. The output terminal of the low voltage lockout module (34) is connected to the second input terminal of the high-side NOR gate (32) and the second input terminal of the low-side NOR gate (33), respectively. The output terminal of the high-side NOR gate (32) serves as the first output terminal of the logic transmission unit (3), and the output terminal of the low-side NOR gate (33) serves as the second output terminal of the logic transmission unit (3).

9. A chip, characterized in that, Includes the gate driver circuit described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip described in claim 9 above.

Images