latches, D-type flip-flop units, and frequency dividers

Abstract

This disclosure provides a latch, a D-type flip-flop unit, and a frequency divider. The latch includes a main amplification module, a slave latch module, and a clock transmission gate module. The main amplification module includes: a first input transistor with its gate set as a first input node and its drain set as a first output node; a second input transistor with its gate set as a second input node and its drain set as a second output node, and its source connected to the source of the first input transistor; a first switching transistor with its source connected to a power supply terminal, its drain connected to the first output node, and its gate connected to a first clock signal; a second switching transistor with its source connected to a power supply terminal, its drain connected to the second output node, and its gate connected to the first clock signal; a third switching transistor with its drain connected to the source of the first input transistor and its gate connected to the first clock signal; a fourth switching transistor with its drain connected to the source of the third switching transistor, its gate connected to a second clock signal, and its source grounded; one end of a capacitor connected to the drain of the fourth switching transistor, and the other end grounded; the main amplification module and the slave latch module are connected through the clock transmission gate module.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a latch, a D-type flip-flop unit, and a frequency divider. Background Technology

[0002] In superconducting quantum computing, quantum states typically undergo controlled evolution and flipping under microwave actuation. Therefore, the measurement and control module needs to include a phase-locked loop (PLL) for generating high-frequency, low-phase-noise carrier waves. As the number of superconducting qubits continues to expand, the number of coaxial lines connecting the room-temperature measurement and control module and the superconducting quantum chip in the dilution refrigerator will also increase, leading to a continuous increase in the system size of the dilution refrigerator and measurement and control module. Therefore, it is necessary to design a PLL capable of operating at extremely low temperatures to integrate the measurement and control module with the dilution refrigerator.

[0003] Frequency dividers are used to form the feedback loop of a frequency synthesizer, dividing high-frequency signals by a specified factor to a lower frequency for comparison with a reference clock. The input of the frequency divider is the highest-frequency circuit in the phase-locked loop (PLL) and also the most power-consuming sub-circuit. Because qubits are temperature-sensitive and chips operate at extremely low temperatures, there are strict limitations on chip power consumption. Therefore, a new low-power, high-speed frequency division technology is urgently needed.

[0004] The operating frequency of a frequency divider is primarily determined by D-type flip-flops. However, at extremely low temperatures, due to the increased threshold voltage, conventional frequency dividers constructed with D-type flip-flops rarely reach the GHz level. While D-type flip-flops using current-mode logic offer high operating speeds, their high power consumption is due to quiescent current. These issues make the design of frequency divider circuits in high-frequency, low-power phase-locked loops (PLLs) extremely difficult at extremely low temperatures, necessitating the development of new structures to address this problem. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a latch, a D-type flip-flop unit, and a frequency divider.

[0006] One aspect of this disclosure provides a latch, including a main amplifier module, a slave latch module, and a clock transmission gate module. The main amplifier module includes: a first input transistor MN1, a second input transistor MN2, a first switch transistor MP1, a second switch transistor MP2, a third switch transistor MN3, a fourth switch transistor MN4, and a capacitor C. The first input transistor MN1 has a gate connected to the first input node D+ and a drain connected to the first output node QB. The second input transistor MN2 has a gate connected to the second input node D- and a drain connected to the second output node Q, with its source connected to the source of the first input transistor. The first switching transistor MP1 has its source connected to the power supply, its drain connected to the first output node QB, and its gate connected to the first clock signal. The second switching transistor MP2 has its source connected to the power supply, its drain connected to the second output node Q, and its gate connected to the first clock signal. The third switching transistor MN3 has its drain connected to the source of the first input transistor MN1 and its gate connected to the first clock signal. The fourth switching transistor MN4 has its drain connected to the source of the third switching transistor MN3, its gate connected to the second clock signal, and its source grounded. A capacitor C is connected at one end to the drain of the fourth switching transistor MN4 and at the other end to ground. The main amplification module and the slave latch module are connected through a clock transmission gate module.

[0007] According to an embodiment of this disclosure, a first input node D+ and a second input node D- are used to input a first differential signal, a main amplification module is used to process the input first differential signal into a second differential signal under the action of a first clock signal and a second clock signal, and a latch module is used to receive and latch the second differential signal.

[0008] According to embodiments of this disclosure, if either the first clock signal or the second clock signal is a high-level signal, then the other is a low-level signal.

[0009] According to embodiments of this disclosure, the latch module includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected together and connected to a power supply terminal. The gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4, and a fourth output node Q1 is connected to the drain. The gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and a third output node Q1B is connected to the drain.

[0010] According to embodiments of this disclosure, the clock transmission gate module includes a first clock transmission gate and a second clock transmission gate. The gate of the NMOS transistor of the first clock transmission gate is connected to the gate of the NMOS transistor of the second transmission gate, which is connected to a first clock signal; the gate of the PMOS transistor of the second clock transmission gate is connected to the gate of the PMOS transistor of the second transmission gate, which is connected to a second clock signal. The clock transmission gate module is turned on or off when the clock signal is applied.

[0011] According to an embodiment of this disclosure, the input of the first clock transmission gate is connected to the first output node QB, and the output is connected to the third output node Q1B; the input of the second clock transmission gate is connected to the second output node Q, and the output is connected to the fourth output node Q1.

[0012] According to an embodiment of this disclosure, when the first clock signal is a high-level signal, the second clock signal is a low-level signal. The third switch MN3 is turned on, the fourth switch MN4, the first switch MP1, and the second switch MP2 are turned off, and the clock transmission gate module is turned on. The first input transistor MN1 and the second input transistor MN2 form a branch with the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third switch MN3, and the capacitor C through the clock transmission gate module, and the capacitor C stores charge. The first differential signal is input through the first input node D+ and the second input node D-, processed into a second differential signal, and then latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0013] According to an embodiment of this disclosure, when the first clock signal is low, the second clock signal is high. The first switch MP1, the second switch MP2, and the fourth switch MN4 are turned on, the third switch MN3 is turned off, the clock transmission gate module is turned off, and the charge stored in capacitor C is discharged to ground through the fourth switch MN4. The drains of the first input transistor MN1 and the second input transistor MN2 are pulled up to the power supply voltage by the first switch MP1 and the second switch MP2, respectively. Since the clock transmission gate module is off, the state of the second differential signal is continuously latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0014] In another aspect of this disclosure, a D-type flip-flop unit is provided, comprising two latches as described above, namely a first latch and a second latch, wherein the third output node Q1B of the first latch is connected to the second input node D-′ of the second latch, and the fourth output node Q1 of the first latch is connected to the first input node D+ of the second latch.

[0015] In another aspect of this disclosure, a frequency divider is provided, comprising at least one of the aforementioned D-type flip-flop units.

[0016] The latch disclosed herein is a dynamic logic circuit that dynamically stores charge and logic state using a capacitor C. It can handle very high-frequency signals. By using a third switch MN3, a fourth switch MP4, and capacitor C, current-directed latching is achieved, thus significantly reducing power consumption while processing high-frequency signals. By replacing the original resistor with a first switch MN1 and a second switch MN2, the voltage drop from the power supply to the output is reduced, greatly improving the output swing. Extremely low power consumption is achieved while maintaining low phase noise, enabling reduced power consumption of the phase-locked loop circuit even in extremely low-temperature environments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of the latch according to an embodiment of the present disclosure;

[0018] Figure 2 This is a schematic diagram of the circuit structure of a D-type flip-flop unit according to an embodiment of the present disclosure;

[0019] Figure 3 This is a schematic diagram of the composition of a frequency divider according to an embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram illustrating the frequency division result of a frequency divider at extremely low temperatures for a 6.4 GHz frequency, provided in an embodiment of this disclosure; and

[0021] Figure 5 This is a schematic diagram showing the frequency division result of a traditional current-mode divider at an extremely low temperature for a frequency of 6.4 GHz. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. However, this disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout.

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] To facilitate understanding of the technical solutions disclosed herein by those skilled in the art, the following technical terms are explained.

[0027] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Similarly, when using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0028] Figure 1 This is a schematic diagram of the circuit structure of the latch according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the circuit structure of a D-type flip-flop unit according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the composition of a frequency divider according to an embodiment of the present disclosure.

[0029] According to embodiments of this disclosure, in conjunction with Figure 1 and Figure 3As shown, the latch includes a main amplifier module, a slave latch module, and a clock transmission gate module. The main amplifier module includes: a first input transistor MN1, a second input transistor MN2, a first switch transistor MP1, a second switch transistor MP2, a third switch transistor MN3, a fourth switch transistor MN4, and a capacitor C. The first input transistor MN1 has a gate connected to the first input node D+ and a drain connected to the first output node QB. The second input transistor MN2 has a gate connected to the second input node D- and a drain connected to the second output node Q, with its source connected to the source of the first input transistor. The first switching transistor MP1 has its source connected to the power supply, its drain connected to the first output node QB, and its gate connected to the first clock signal. The second switching transistor MP2 has its source connected to the power supply, its drain connected to the second output node Q, and its gate connected to the first clock signal. The third switching transistor MN3 has its drain connected to the source of the first input transistor MN1 and its gate connected to the first clock signal. The fourth switching transistor MN4 has its drain connected to the source of the third switching transistor MN3, its gate connected to the second clock signal, and its source grounded. A capacitor C is connected at one end to the drain of the fourth switching transistor MN4 and at the other end to ground. The main amplification module and the slave latch module are connected through a clock transmission gate module.

[0030] According to embodiments of this disclosure, the first input transistor MN1 and the second input transistor MN2 constitute a differential input pair.

[0031] According to embodiments of this disclosure, a transmission gate is a controllable switching circuit that can transmit both digital and analog signals.

[0032] According to embodiments of this disclosure, the capacitance value of capacitor C can be determined based on the charging and discharging speed. For example, the capacitance value of capacitor C can range from 10fF to 900fF. Specifically, it can be any one of 30fF, 50fF, 100fF, 200fF, 500fF, 800fF, etc.

[0033] The latch disclosed herein is a dynamic logic circuit that dynamically stores charge and logic state using a capacitor C. It can handle very high-frequency signals. By using a third switch MN3, a fourth switch MN4, and capacitor C, current-directed latching is achieved, thereby significantly reducing power consumption while handling high-frequency signals. By replacing the original resistor with a first switch MN1 and a second switch MN2, the voltage drop from the power supply to the output is reduced, greatly improving the output swing. Extremely low power consumption is achieved while maintaining low phase noise, enabling reduced power consumption of the phase-locked loop circuit even in extremely low-temperature environments.

[0034] According to an embodiment of this disclosure, a first input node D+ and a second input node D- are used to input a first differential signal, a main amplification module is used to process the input first differential signal into a second differential signal under the action of a first clock signal and a second clock signal, and a latch module is used to receive and latch the second differential signal.

[0035] According to embodiments of this disclosure, the clock signal includes a first clock signal and a second clock signal. If either the first clock signal or the second clock signal is a high-level signal, then the other is a low-level signal. For example, the first clock signal can be CLK+, which is a high-level signal, and the second clock signal can be CLK-, which is a low-level signal. Alternatively, the first clock signal can be the low-level signal CLK-, and the second clock signal can be the high-level signal CLK+.

[0036] According to embodiments of this disclosure, the latch module includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected together and connected to a power supply terminal. The gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4, and a fourth output node Q1 is connected to the drain. The gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and a third output node Q1B is connected to the drain.

[0037] According to embodiments of this disclosure, the clock transmission gate module includes a first clock transmission gate and a second clock transmission gate. Each clock transmission gate is composed of a PMOS and an NMOS transistor connected in parallel, and has a very low on-resistance (less than 1 ohm) and a very high off-resistance (greater than 10 ohms). 9 (Oh). A PMOS operates when a high-level clock signal is input, and an NMOS operates when a low-level clock signal is input. For example... Figure 1 As shown, the gates of the NMOS transistors of the first clock transmission gate and the second clock transmission gate are connected to the first clock signal CLK+; the gates of the PMOS transistors of the second clock transmission gate and the second clock signal CLK- are connected to the second clock signal CLK-. The clock transmission gate module is turned on or off when the clock signal is applied.

[0038] According to an embodiment of this disclosure, the input of the first clock transmission gate is connected to the first output node QB, and the output is connected to the third output node Q1B; the input of the second clock transmission gate is connected to the second output node Q, and the output is connected to the fourth output node Q1.

[0039] According to an embodiment of this disclosure, when the first clock signal is a high-level signal, the second clock signal is a low-level signal. The third switch MN3 is turned on, the fourth switch MN4, the first switch MP1, and the second switch MP2 are turned off, and the clock transmission gate module is turned on. The first input transistor MN1 and the second input transistor MN2 form a branch with the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third switch MN3, and the capacitor C through the clock transmission gate module, and the capacitor C stores charge. The first differential signal is input through the first input node D+ and the second input node D-, processed into a second differential signal, and then latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0040] According to an embodiment of this disclosure, when the first clock signal is low, the second clock signal is high. The first switch MP1, the second switch MP2, and the fourth switch MN4 are turned on, the third switch MN3 is turned off, the clock transmission gate module is turned off, and the charge stored in capacitor C is discharged to ground through the fourth switch MN4. The drains of the first input transistor MN1 and the second input transistor MN2 are pulled up to the power supply voltage by the first switch MP1 and the second switch MP2, respectively. Since the clock transmission gate module is off, the state of the second differential signal is continuously latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0041] Another aspect of the embodiments of this disclosure also provides a D-type trigger unit, combined with Figures 1 to 3 As shown, the D-type flip-flop unit includes two latches as described above, namely the first latch and the second latch. The third output node Q1B of the first latch is connected to the second input node D-′ of the second latch, and the fourth output node Q1 of the first latch is connected to the first input node D+ of the second latch.

[0042] According to an embodiment of this disclosure, if the gate input of the first switching transistor MP1 of the first latch is a high-level clock signal, then the gate input of the first switching transistor MP1′ of the second latch is a low-level clock signal. The first-stage latch is high-level latching, and the second-stage latch is low-level latching.

[0043] According to an embodiment of this disclosure, if the gate input of the first switch transistor MP1 of the first latch is a low-level clock signal, then the gate input of the first switch transistor MP1′ of the second latch is a high-level clock signal. The first-stage latch is low-level latching, and the second-stage latch is high-level latching.

[0044] In another aspect of the present disclosure, a frequency divider is provided, including at least one D-type flip-flop unit.

[0045] According to embodiments of this disclosure, a frequency divider is provided, combined with... Figures 1 to 3 As shown, the frequency divider includes two latches, namely a first latch and a second latch. The third output node Q1B of the first latch is connected to the second input node D-′ of the second latch, and the fourth output node Q1 of the first latch is connected to the first input node D+ of the second latch. Similarly, the third output node Q1B′ of the second latch is connected to the first input node D+ of the first latch, and the fourth output node Q1′ of the second latch is connected to the second input node D- of the first latch. This forms a cascaded feedback structure consisting of two latches.

[0046] According to embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the first latch is a high-level latch, and the second latch is a low-level latch.

[0047] According to embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the frequency divider consists of a first latch and a second latch connected end-to-end. A single-stage latch mainly comprises a main amplification module and a slave latch module, connected by a transmission gate unit controlled by the input clock. The first latch is used to input a first differential signal. The main amplification module processes the first differential signal into a second differential signal, and the slave latch module receives and latches the second differential signal. The main amplification module in the second latch is connected to the slave latch module in the first latch, processing the second differential signal output by the first latch into a third differential signal. The slave latch module in the second latch receives and latches the third differential signal. The slave latch module in the second latch is then connected to the main amplification module of the first latch, thus forming a cascaded feedback structure consisting of two stages of latches.

[0048] According to embodiments of this disclosure, such as Figure 2 As shown, the frequency divider is a fully differential structure, consisting of two differential input clock signals (input through the first clock input node and the second clock input node), two differential input signals (input through the first input node D+ and the second input node D-), and differential output signals (output through the fourth output node Q1′ and the third output node Q1B′ of the second latch).

[0049] According to embodiments of this disclosure, the first clock signal of the first latch is a high-level clock signal CLK+, and the second clock signal is a low-level clock signal CLK-, making the first latch a high-level latch module. The first clock signal of the second latch is a low-level clock signal, and the second clock signal is a high-level clock signal, making the second latch a low-level latch module.

[0050] Taking the first latch as an example, when the first clock signal is a high-level signal (CLK+), the third switch MN3 is turned on, the fourth switch MN4, the first switch MP1, and the second switch MP2 are turned off, the clock transmission gate module is turned on, and the differential input pair (the first input MN1 and the second input MN2) forms a branch through the clock transmission gate module with the cross-coupled pair (the third PMOS transistor MP3 and the fourth PMOS transistor MP4), the tail switch (the third switch MN3), and the capacitor C. The first differential input signal is input through the first input node D+ and the second input node D-, and amplified by the differential input pair (the first input MN1 and the second input MN2) to become the second differential signal. After passing through the clock transmission gate module, it is latched by the cross-coupled pair (the third PMOS transistor MP3 and the fourth PMOS transistor MP4), and the capacitor C stores the charge.

[0051] When the first clock signal is low (CLK-), the first switch MP1, the second switch MP2, and the fourth switch MN4 are turned on, the third switch MN3 is turned off, the clock transmission gate module is turned off, and the charge stored in capacitor C is discharged to ground through the fourth switch MN4. At this time, because the voltage drop of the first switch MP1 and the second switch MP2 is relatively small, the drains of the differential input pair (the first input transistor MN1 and the second input transistor MN2) are pulled up to the power supply voltage by the first switch MP1 and the second switch MP2, increasing the swing. Since the clock transmission gate module is off, the state of the second differential signal is continuously latched by the cross-coupled pair (the third PMOS transistor MP3 and the fourth PMOS transistor MP4).

[0052] Therefore, when the first clock is a high-level signal (CLK+), assuming the first differential input signal is a high-level signal (input from the first input node D+), the output terminal Q1 of the first latch will be charged to the power supply voltage by the cross-coupled transistors (the third PMOS transistor MP3 and the fourth PMOS transistor MP4), while the output terminal Q1B will be low. When the first clock signal changes to a low level CLK-, the second differential signal output from the two output terminals (Q1 and Q1B) of the first latch will be latched and maintained in its previous state, serving as the differential input signal of the second latch. At this time, the third switch MN3' of the second latch is turned on, while the fourth switch MN4', the first switch MP1', and the second switch MP2' are turned off. The clock transmission gate module is turned on, and the second output node Q' is charged to the power supply voltage through the first switch MP1' and the second switch MP2'.

[0053] Connecting the first input node D+ of the first latch and the negative output terminal (third output node Q1B′) of the second latch, and connecting the second input node D- and the positive output terminal (fourth output node Q1′) forms a negative feedback, which can realize the function of frequency division by two.

[0054] According to embodiments of this disclosure, extremely low temperature refers to the temperature inside the dilution refrigerator, i.e., a temperature of about 4.2 Kelvin (K).

[0055] Figure 4 The frequency division result of the frequency divider provided in this embodiment of the present disclosure at an extremely low temperature for a frequency of 6.4 GHz. Figure 5 This is the frequency division result of a traditional current-mode divider at an extremely low temperature for a frequency of 6.4 GHz.

[0056] This disclosure has been verified using a 110nm CMOS process at extremely low temperatures, such as... Figure 4 As shown, the horizontal axis represents time (ns), and the vertical axis, from top to bottom, represents the input clock signal (V), the output signal (V), and the current of the entire circuit (uA), respectively. The output signal (V) measures the voltage value at Q1′. When the input signal frequency is a 6.4GHz square wave, the output waveform is a square wave after frequency division by two, and the quiescent current is extremely low. Figure 5 As shown, the horizontal axis represents time (ns), and the vertical axis, from top to bottom, represents the input clock signal (V), output signal (V), and the total circuit current (uA). Traditional current-modulus dividers exhibit high quiescent current and significant power consumption when dividing a 6.4GHz frequency at extremely low temperatures. Power consumption is the product of the root mean square value of the total circuit current and the clock signal voltage.

[0057] Depend on Figure 4 and Figure 5 As can be seen, when dividing a 6.4GHz square wave by two at extremely low temperatures, the power consumption of traditional current-mode logic frequency dividers is approximately 1.45mW, while the power consumption after applying the frequency divider provided in this disclosure is only 120μW. Comparing the results of the two frequency dividers, the frequency divider circuit using the current-directing latch provided in this disclosure not only handles high-frequency signals well at extremely low temperatures, but also significantly reduces power consumption compared to traditional current-mode logic frequency dividers.

[0058] Addressing the challenges of high power consumption in traditional current-mode frequency divider circuits and significantly increased threshold voltage of MOSFETs in extremely low-temperature environments, the frequency divider circuit using the latch provided in this disclosure can effectively perform frequency division processing of the 6-8 GHz frequency signal required for superconducting quantum bit measurement and control. It achieves extremely low power consumption while ensuring low phase noise, thereby reducing the power consumption of the phase-locked loop circuit in extremely low-temperature environments.

[0059] Compared to traditional current-mode logic divider circuits, the current-directing logic divider circuit provided in this disclosure features an optimized structure. It eliminates the tail current source found in traditional current-mode circuits, significantly reducing power consumption. By replacing the resistive elements in traditional current-mode circuits with first and second switching transistors MN1 and MN2, the voltage drop from the power supply to the output terminal is reduced, greatly improving the output swing. The added capacitors also have smaller capacitance values, thus reducing the overall circuit area. Furthermore, the output signal after frequency division using the latch provided in this disclosure exhibits good phase noise, preventing deterioration of the phase noise of the entire phase-locked loop (PLL). This greatly facilitates the design of high-frequency, low-phase-noise, and low-power PLLs operating at extremely low temperatures.

[0060] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure, and the shapes and dimensions of the components in the drawings do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0061] Unless otherwise stated, the numerical parameters in this specification and the appended claims are approximate values ​​and can be varied according to desired characteristics derived from the content of this disclosure. Specifically, all figures used in the specification and claims to indicate composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Generally, this means that a specific amount varies by ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0062] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0063] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0064] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A latch for use in extremely low temperatures, comprising a master amplification module, a slave latch module, and a clock transmission gate module. The main amplification module includes: The first input transistor MN1 has a first input node D+ at its gate connection terminal and a first output node QB at its drain connection terminal. The second input transistor MN2 has a second input node D- at its gate connection terminal, a second output node Q at its drain connection terminal, and its source is connected to the source of the first input transistor. The first switching transistor MP1 has its source connected to the power supply terminal, its drain connected to the first output node QB, and its gate connected to the first clock signal. The second switching transistor MP2 has its source connected to the power supply terminal, its drain connected to the second output node Q, and its gate connected to the first clock signal. The third switching transistor MN3 has its drain connected to the source of the first input transistor MN1 and its gate connected to the first clock signal. The fourth switch MN4 has its drain connected to the source of the third switch MN3, its gate connected to the second clock signal, and its source grounded. as well as One end of capacitor C is connected to the drain of the fourth switching transistor MN4, and the other end is grounded; The main amplification module and the slave latch module are connected through the clock transmission gate module; The first input node D+ and the second input node D- are used to input a first differential signal. The main amplification module is used to process the input first differential signal into a second differential signal under the action of the first clock signal and the second clock signal. The slave latch module is used to receive and latch the second differential signal. The latch module includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4; the source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected and jointly connected to the power supply terminal, and the gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4, and a fourth output node Q1 is connected to the drain; the gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and a third output node Q1B is connected to the drain. The clock transmission gate module includes a first clock transmission gate and a second clock transmission gate; the gate of the NMOS transistor of the first clock transmission gate and the gate of the NMOS transistor of the second transmission gate are connected to a first clock signal; the gate of the PMOS transistor of the second clock transmission gate and the gate of the PMOS transistor of the second transmission gate are connected to a second clock signal; the clock transmission gate module is turned on or off when the clock signal is applied. The input of the first clock transmission gate is connected to the first output node QB, and the output is connected to the third output node Q1B; the input of the second clock transmission gate is connected to the second output node Q, and the output is connected to the fourth output node Q1. When the first clock signal is high, the second clock signal is low; the third switch MN3 is turned on, the fourth switch MN4, the first switch MP1, and the second switch MP2 are turned off, and the clock transmission gate module is turned on; the first input transistor MN1 and the second input transistor MN2 form a branch with the third PMOS transistor MP3, the fourth PMOS transistor MP4, the third switch MN3, and the capacitor C through the clock transmission gate module, and the capacitor C stores charge; the first differential signal is input through the first input node D+ and the second input node D-, processed into a second differential signal, and then latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4; When the first clock signal is low, the second clock signal is high; the first switch MP1, the second switch MP2, and the fourth switch MN4 are turned on, the third switch MN3 is turned off, the clock transmission gate module is turned off, the charge stored on capacitor C is discharged to ground through the fourth switch MN4, the drain of the first input transistor MN1 and the drain of the second input transistor MN2 are pulled up to the power supply voltage by the first switch MP1 and the second switch MP2 respectively, and since the clock transmission gate module is turned off, the state of the second differential signal is continuously latched by the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

2. The latch according to claim 1, wherein if either the first clock signal or the second clock signal is a high-level signal, then the other is a low-level signal.

3. A D-type flip-flop unit, comprising two latches as described in any one of claims 1 to 2, namely a first latch and a second latch, wherein, The third output node Q1B of the first latch is connected to the second input node D-′ of the second latch, and the fourth output node Q1 of the first latch is connected to the first input node D+′ of the second latch.

4. A frequency divider comprising at least one D-type flip-flop unit as described in claim 3.

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