Hybrid adc circuit, chip and analog-digital conversion method

Abstract

The application discloses a hybrid ADC circuit, a chip and a method for analog-digital conversion. The hybrid ADC circuit comprises an integrator, a comparator and a successive approximation analog-digital converter. The integrator comprises a sampling circuit, an operational amplifier, a first integration capacitor, a second integration capacitor and a control circuit. According to the hybrid ADC circuit, the chip and the method for analog-digital conversion, the control circuit is arranged to pre-charge the first integration capacitor and the second integration capacitor at an initial moment, so that the output residual error of the integrator is in a known state at the initial moment, thereby eliminating the need to convert the output of the integrator by the successive approximation analog-digital converter, reducing the number of conversions of the successive approximation analog-digital converter, and reducing power consumption and time.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a hybrid ADC circuit, chip, and analog-to-digital conversion method. Background Technology

[0002] Figure 1 For existing hybrid ADC circuits combining Σ-Δ and successive approximation analog-to-digital converters (SAR ADCs), the successive approximation ADC requires four sampling and conversion operations during the analog-to-digital conversion process. Initially, because the residual error of the integrator's output is unknown, the successive approximation ADC samples and converts the integrator's output. After the integrator performs N integrations, the successive approximation ADC samples and converts the integrator's output again, resulting in two conversions per stage. Since the integrator needs to perform reverse alternating sampling of the input differential signal, with each alternating sampling corresponding to one stage, at least two stages are required, resulting in four sampling and conversion operations, increasing power consumption and conversion time. This problem is particularly pronounced when the accuracy of the Σ-Δ converter (i.e., the number of integrations by the integrator) accounts for a relatively small proportion of the overall performance of this hybrid ADC circuit.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a hybrid ADC circuit, chip, and analog-to-digital conversion method that can reduce the number of conversions of the integrator output by the successive approximation analog-to-digital converter.

[0005] To achieve the above objectives, embodiments of the present invention provide a hybrid ADC circuit, including: an integrator, a comparator, and a successive approximation analog-to-digital converter, wherein the integrator includes: a sampling circuit, an operational amplifier, a first integrating capacitor, a second integrating capacitor, and a control circuit.

[0006] The sampling circuit is used to sample the differential signal and output a sampled signal.

[0007] The first and second input terminals of the operational amplifier are connected to the output terminal of the sampling circuit. The first terminal of the first integrating capacitor is connected to the first input terminal of the operational amplifier. The second terminal of the first integrating capacitor is connected to the first output terminal of the operational amplifier. The first terminal of the second integrating capacitor is connected to the second input terminal of the operational amplifier. The second terminal of the second integrating capacitor is connected to the second output terminal of the operational amplifier.

[0008] The control circuit is used to control the connection and disconnection between the first and second terminals of the first integrating capacitor and the power supply voltage, between the first and second terminals of the second integrating capacitor and the power supply voltage, between the first output terminal of the operational amplifier and the second terminal of the first integrating capacitor, and between the second output terminal of the operational amplifier and the second terminal of the second integrating capacitor.

[0009] The comparator is connected to the first and second output terminals of the operational amplifier, and outputs a corresponding code stream signal to feed back to the input terminal of the integrator.

[0010] The successive approximation analog-to-digital converter is used to sample the residual error signal output by the integrator after N integrations and perform analog-to-digital conversion to output a digital signal, where N≥1.

[0011] In one or more embodiments of the present invention, the sampling circuit includes a chopper unit, a first sampling capacitor, a second sampling capacitor, a first switching unit, a second switching unit, and a third switching unit;

[0012] The first terminal of the first sampling capacitor is connected to the chopper unit and the first switching unit. The first switching unit is also connected to the power supply voltage. The second terminal of the first sampling capacitor is connected to the second switching unit and the third switching unit. The second switching unit is also connected to the common-mode voltage. The third switching unit is also connected to the input terminal of the operational amplifier.

[0013] In one or more embodiments of the present invention, the chopper unit includes a first sampling switch, a second sampling switch, a third sampling switch, and a fourth sampling switch. A first terminal of the first sampling switch is connected to a first terminal of the second sampling switch to form a first input terminal. A first terminal of the third sampling switch is connected to a first terminal of the fourth sampling switch to form a second input terminal. A second terminal of the first sampling switch is connected to a second terminal of the third sampling switch and also to a first terminal of a first sampling capacitor. A second terminal of the second sampling switch is connected to a second terminal of the fourth sampling switch and also to a first terminal of a second sampling capacitor; and / or

[0014] The first switching unit includes a fifth sampling switch and a sixth sampling switch. The first terminal of the fifth sampling switch is connected to the first terminal of the first sampling capacitor, the first terminal of the fifth sampling switch is connected to the first terminal of the second sampling capacitor, and the second terminals of the fifth sampling switch and the sixth sampling switch are connected to the power supply voltage.

[0015] In one or more embodiments of the present invention, the second switching unit includes a seventh sampling switch and an eighth sampling switch, wherein a first terminal of the seventh sampling switch is connected to a second terminal of a first sampling capacitor, a first terminal of the eighth sampling switch is connected to a second terminal of a second sampling capacitor, and the second terminals of the seventh and eighth sampling switches are connected to a common-mode voltage; and / or

[0016] The third switching unit includes a ninth sampling switch and a tenth sampling switch. The first terminal of the ninth sampling switch is connected to the second terminal of the first sampling capacitor, the first terminal of the tenth sampling switch is connected to the second terminal of the second sampling capacitor, and the second terminals of the ninth and tenth sampling switches are connected to the input terminals of the operational amplifier.

[0017] In one or more embodiments of the present invention, the control circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch;

[0018] The first terminal of the first switch is connected to the first terminal of the first integrating capacitor, the first terminal of the second switch is connected to the second terminal of the first integrating capacitor, and the second terminals of the first switch and the second terminals of the second switch are connected to the power supply voltage.

[0019] The first terminal of the third switch is connected to the first terminal of the second integrating capacitor, the first terminal of the fourth switch is connected to the second terminal of the second integrating capacitor, and the second terminals of the third switch and the fourth switch are connected to the power supply voltage.

[0020] The first terminal of the fifth switch is connected to the first output terminal of the operational amplifier, the second terminal of the fifth switch is connected to the second terminal of the first integrating capacitor, the first input terminal of the comparator, and the first input terminal of the successive approximation analog-to-digital converter, the first terminal of the sixth switch is connected to the second output terminal of the operational amplifier, and the second terminal of the sixth switch is connected to the second terminal of the second integrating capacitor, the second input terminal of the comparator, and the second input terminal of the successive approximation analog-to-digital converter.

[0021] In one or more embodiments of the present invention, there are n integrators, where n≥2. The input terminal of the successive approximation analog-to-digital converter is connected to the output terminal of the first integrator, the output terminal of the successive approximation analog-to-digital converter is connected to the input terminal of the second integrator, the input terminal of the comparator is connected to the output terminal of the nth integrator, and the output terminal of the comparator is connected to the input terminal of the first integrator.

[0022] The present invention also discloses a chip including the aforementioned hybrid ADC circuit.

[0023] This invention also discloses an analog-to-digital conversion method for the aforementioned hybrid ADC circuit, comprising:

[0024] Initially, the connection between the sampling circuit and the first integrating capacitor, the second integrating capacitor, and the operational amplifier is disconnected. The first integrating capacitor and the second integrating capacitor are connected to the reference voltage through the control circuit. At the same time, the connection between the output terminal of the operational amplifier and the first integrating capacitor and the second integrating capacitor is disconnected through the control circuit.

[0025] After one cycle, the control circuit disconnects the first integrating capacitor from the reference voltage, disconnects the second integrating capacitor from the reference voltage, connects the output of the operational amplifier to the first integrating capacitor, and connects the output of the operational amplifier to the second integrating capacitor, and outputs the initial residual error signal through the operational amplifier.

[0026] The comparator outputs the initial bitstream signal based on the initial residual error signal and sends it to the input of the integrator.

[0027] The residual error signal is obtained by integrating the initial bitstream signal using an integrator.

[0028] The digital signal is output by sampling the total residual error signal of the integrator after N integrations by the successive approximation analog-to-digital converter, and then performing analog-to-digital conversion, where N≥1;

[0029] The comparator outputs the bitstream signal based on the total residual error signal output by the integrator after N integrations.

[0030] The total voltage signal output by the ADC circuit is obtained based on the code stream signal and the digital signal.

[0031] In one or more embodiments of the present invention, the analog-to-digital conversion method includes: one or more first stages and second stages, wherein the polarities of the signals sampled by the integrator in the first stage and the signals sampled in the second stage are opposite;

[0032] The first stage:

[0033] The comparator outputs a first initial code stream signal to the input of the integrator based on the first initial residual error signal output from the operational amplifier.

[0034] The first residual error signal is obtained by integrating the first initial code stream signal using an integrator.

[0035] The comparator outputs the first bitstream signal based on the first total residual error signal output by the integrator after N integrations.

[0036] The first digital signal is output by sampling the first total residual error signal of the integrator after N integrations by successive approximation analog-to-digital converter and performing analog-to-digital conversion.

[0037] The first total voltage signal output by the ADC circuit is obtained based on the first code stream signal and the first digital signal.

[0038] Phase Two:

[0039] The comparator outputs a second initial code stream signal based on the second initial residual error signal output from the operational amplifier and sends it to the input of the integrator.

[0040] The second residual error signal is obtained by integrating the second initial code stream signal using an integrator.

[0041] The comparator outputs the second bitstream signal based on the second total residual error signal output by the integrator after N integrations.

[0042] The second digital signal is output by sampling the second total residual error signal of the integrator after N integrations by successive approximation analog-to-digital converter and performing analog-to-digital conversion.

[0043] The second total voltage signal output by the ADC circuit is obtained based on the second code stream signal and the second digital signal.

[0044] After the first and second stages are completed, the total voltage output signal of the ADC circuit is obtained based on the first total voltage signal and the second total voltage signal.

[0045] In one or more embodiments of the present invention, the connection between the first terminal of the first integrating capacitor and the reference voltage and the connection between the second terminal of the first integrating capacitor and the reference voltage are disconnected by the control circuit in a preset order. The connection between the first terminal of the second integrating capacitor and the reference voltage and the connection between the second terminal of the second integrating capacitor and the reference voltage are also disconnected by the control circuit in a preset order.

[0046] Compared with the prior art, the hybrid ADC circuit, chip and analog-to-digital conversion method according to the embodiments of the present invention, the hybrid ADC circuit precharges the first integrating capacitor and the second integrating capacitor at the initial moment by setting the control circuit, so that the output residual error of the integrator is known at the initial moment, thereby eliminating the need to convert the output of the integrator through successive approximation analog-to-digital converters, thereby reducing the number of conversions of successive approximation analog-to-digital converters, reducing power consumption and time. Attached Figure Description

[0047] Figure 1 It is a circuit schematic diagram of a hybrid ADC circuit based on existing technology.

[0048] Figure 2 This is a circuit schematic diagram of a hybrid ADC circuit according to an embodiment of the present invention.

[0049] Figure 3This is a flowchart of an analog-to-digital conversion method for a hybrid ADC circuit according to an embodiment of the present invention. Detailed Implementation

[0050] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0051] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0052] like Figure 2 As shown, a hybrid ADC circuit includes an integrator 10, a comparator 20, and a successive approximation analog-to-digital converter 30 (SAR_ADC). In this embodiment, the integrator 10 and the comparator 20 form a Σ-Δ modulator.

[0053] At the initial moment, integrator 10 outputs an initial residual error signal. After the initial moment, it integrates a pair of differential signals Vinp and Vinn to output a residual error signal. Comparator 20 outputs corresponding code stream signals to the input of integrator 10 based on the initial residual error signal and the residual error signal, respectively. Successive approximation analog-to-digital converter 30 samples the residual error signal output by integrator 10 after N integrations and performs analog-to-digital conversion to output a digital signal, where N≥1. Based on this digital signal and the code stream signal obtained by comparator 20 based on the residual error signal output by integrator 10 after N integrations, the total voltage output signal of the ADC circuit is finally obtained.

[0054] like Figure 2 As shown, the integrator 10 includes: a sampling circuit 11, an operational amplifier op, a first integrating capacitor C1, a second integrating capacitor C2, and a control circuit 12.

[0055] The sampling circuit 11 is used to sample a pair of differential signals Vinp, Vinn or the code stream signal fed back by the comparator 20 and output the corresponding sampling signals VP, VN.

[0056] In this embodiment, the sampling circuit 11 includes a chopper unit 111, a first sampling capacitor C3, a second sampling capacitor C4, a first switching unit 112, a second switching unit 113, and a third switching unit 114.

[0057] The first terminal of the first sampling capacitor C3 is connected to the chopper unit 111 and the first switching unit 112. The first switching unit 112 is also connected to the reference voltage VRFE. The second terminal of the first sampling capacitor C3 is connected to the second switching unit 113 and the third switching unit 114. The second switching unit 113 is also connected to the common-mode voltage VCM. The third switching unit 114 is also connected to the input terminal of the operational amplifier op.

[0058] Specifically, the chopper unit 111 includes a first sampling switch S1a, a second sampling switch S2a, a third sampling switch S2b, and a fourth sampling switch S1b.

[0059] The first terminal of the first sampling switch S1a is connected to the first terminal of the second sampling switch S2a to form a first input terminal. The first terminal of the third sampling switch S2b is connected to the first terminal of the fourth sampling switch S1b to form a second input terminal. The first and second input terminals are used to receive differential signals Vinp and Vinn. The second terminal of the first sampling switch S1a is connected to the second terminal of the third sampling switch S2b and to the first terminal of the first sampling capacitor C3. The second terminal of the second sampling switch S2a is connected to the second terminal of the fourth sampling switch S1b and to the first terminal of the second sampling capacitor C4.

[0060] The first switching unit 112 includes a fifth sampling switch S3a and a sixth sampling switch S3b. The first terminal of the fifth sampling switch S3a is connected to the first terminal of the first sampling capacitor C3, and the first terminal of the fifth sampling switch S3a is connected to the first terminal of the second sampling capacitor C4. The second terminals of the fifth sampling switch S3a and the sixth sampling switch S3b are connected to the reference voltage VRFE.

[0061] The second switching unit 113 includes a seventh sampling switch S4a and an eighth sampling switch S4b. The first terminal of the seventh sampling switch S4a is connected to the second terminal of the first sampling capacitor C3, and the first terminal of the eighth sampling switch S4b is connected to the second terminal of the second sampling capacitor C4. The second terminals of the seventh sampling switch S4a and the eighth sampling switch S4b are connected to the common-mode voltage VCM.

[0062] The third switching unit 114 includes a ninth sampling switch S5a and a tenth sampling switch S5b. The first terminal of the ninth sampling switch S5a is connected to the second terminal of the first sampling capacitor C3, and the first terminal of the tenth sampling switch S5b is connected to the second terminal of the second sampling capacitor C4. The second terminal of the ninth sampling switch S5a is connected to the first input terminal of the operational amplifier op, and the second terminal of the tenth sampling switch S5b is connected to the second input terminal of the operational amplifier op. The first and second input terminals of the operational amplifier op are used to receive sampling signals VP and VN.

[0063] In this embodiment, the first input terminal of operational amplifier op is a positive input terminal, and the second input terminal of operational amplifier op is a negative input terminal. In other embodiments, the first input terminal of operational amplifier op may also be a negative input terminal, and the second input terminal of operational amplifier op may also be a positive input terminal.

[0064] In this embodiment, when the first sampling switch S1a and the fourth sampling switch S1b are closed simultaneously, the positive differential signal Vinp is connected to the first sampling capacitor C3, and the negative differential signal Vinn is connected to the second sampling capacitor C4; when the second sampling switch S2a and the third sampling switch S2b are closed simultaneously, the positive differential signal Vinp is connected to the second sampling capacitor C4, and the negative differential signal Vinn is connected to the first sampling capacitor C3. By alternately closing and opening the first and fourth sampling switches S1a and S1b, and the second and third sampling switches S2a and S2b, alternating sampling of the positive differential signal Vinp and the negative differential signal Vinn is achieved.

[0065] The seventh sampling switch S4a and the eighth sampling switch S4b are closed or opened simultaneously, and are closed or opened when the first sampling switch S1a and the fourth sampling switch S1b or when the second sampling switch S2a and the third sampling switch S2b are closed.

[0066] The fifth sampling switch S3a, the sixth sampling switch S3b, the ninth sampling switch S5a, and the tenth sampling switch S5b are simultaneously closed or open. When the first sampling capacitor C3 and the second sampling capacitor C4 are not sampling, the fifth sampling switch S3a, the sixth sampling switch S3b, the ninth sampling switch S5a, and the tenth sampling switch S5b can be closed.

[0067] Furthermore, the first terminal of the first integrating capacitor C1 is connected to the first input terminal of the operational amplifier op, and the second terminal of the first integrating capacitor C1 is connected to the first output terminal of the operational amplifier op. The first terminal of the second integrating capacitor C2 is connected to the second input terminal of the operational amplifier op, and the second terminal of the second integrating capacitor C2 is connected to the second output terminal of the operational amplifier op. The operational amplifier op, in conjunction with the first integrating capacitor C1 and the second integrating capacitor C2, outputs a residual error signal based on the sampled signals VP and VN.

[0068] In this embodiment, the control circuit 12 is used to control the connection and disconnection between the first and second terminals of the first integrating capacitor C1 and the reference voltage VRFE, between the first and second terminals of the second integrating capacitor C2 and the reference voltage VRFE, between the first output terminal of the operational amplifier op and the second terminal of the first integrating capacitor C1, and between the second output terminal of the operational amplifier op and the second terminal of the second integrating capacitor C2, so as to control the operational amplifier op to output the initial residual error signal in conjunction with the first integrating capacitor C1 and the second integrating capacitor C2.

[0069] Specifically, the control circuit 12 controls the connection between the first and second terminals of the first integrating capacitor C1 and the reference voltage VRFE, and the connection between the first and second terminals of the second integrating capacitor C2 and the reference voltage VRFE, and controls the disconnection between the first output terminal of the operational amplifier op and the second terminal of the first integrating capacitor C1, and the connection between the second output terminal of the operational amplifier op and the second terminal of the second integrating capacitor C2, thereby pre-charging and resetting the first integrating capacitor C1 and the second integrating capacitor C2.

[0070] After one cycle, that is, after the first integrating capacitor C1 and the second integrating capacitor C2 are reset, the control circuit 12 controls the first and second terminals of the first integrating capacitor C1 to disconnect from the reference voltage VRFE and the first and second terminals of the second integrating capacitor C2 to disconnect from the reference voltage VRFE. It also controls the first output terminal of the operational amplifier op to connect with the second terminal of the first integrating capacitor C1 and the second output terminal of the operational amplifier op to connect with the second terminal of the second integrating capacitor C2. At this time, the operational amplifier op, together with the first integrating capacitor C1 and the second integrating capacitor C2, outputs the initial residual error signal.

[0071] like Figure 2 As shown, the control circuit 12 includes a first switch S6a, a second switch S6b, a third switch S7a, a fourth switch S7b, a fifth switch S8a, and a sixth switch S8b.

[0072] The first terminal of the first switch S6a is connected to the first terminal of the first integrating capacitor C1, the first terminal of the second switch S6b is connected to the second terminal of the first integrating capacitor C1, and the second terminals of the first switch S6a and the second terminals of the second switch S6b are connected to the reference voltage VREF.

[0073] The first terminal of the third switch S7a is connected to the first terminal of the second integrating capacitor C2, the first terminal of the fourth switch S7b is connected to the second terminal of the second integrating capacitor C2, and the second terminals of the third switch S7a and the fourth switch S7b are connected to the reference voltage VREF.

[0074] The first terminal of the fifth switch S8a is connected to the first output terminal of the operational amplifier op, and the second terminal of the fifth switch S8a is connected to the second terminal of the first integrating capacitor C1, the first input terminal of the comparator 20, and the first input terminal of the successive approximation analog-to-digital converter 30. The first terminal of the sixth switch S8b is connected to the second output terminal of the operational amplifier op, and the second terminal of the sixth switch S8b is connected to the second terminal of the second integrating capacitor C2, the second input terminal of the comparator 20, and the second input terminal of the successive approximation analog-to-digital converter 30.

[0075] In this embodiment, the first output terminal of operational amplifier op is a negative output terminal, and the second output terminal of operational amplifier op is a positive output terminal. In other embodiments, the first output terminal of operational amplifier op can also be a positive output terminal, and the second output terminal of operational amplifier op can also be a negative output terminal.

[0076] Initially, sampling circuit 11 is disconnected from operational amplifier op, meaning the ninth sampling switch S5a and the tenth sampling switch S5b are open. Switches S6a, S6b, S7a, and S7b are closed, while switches S8a and S8b are open, thus pre-charging the first integrating capacitor C1 and the second integrating capacitor C2. After one cycle, switches S6a, S6b, S7a, and S7b are open again, while switches S8a and S8b are closed, and operational amplifier op outputs the initial residual error signal.

[0077] In other embodiments, there may be n integrators 10, namely the first integrator to the nth integrator, where n≥2. The input terminal of the successive approximation analog-to-digital converter 30 is connected to the output terminal of the first integrator, the output terminal of the successive approximation analog-to-digital converter 30 is connected to the input terminal of the second integrator, the input terminal of the comparator 20 is connected to the output terminal of the nth integrator, and the output terminal of the comparator 20 is connected to the input terminal of the first integrator.

[0078] like Figure 3 As shown, this embodiment also discloses an analog-to-digital conversion method for a hybrid ADC circuit, including:

[0079] Initially, the connection between the sampling circuit 11 and the first integrating capacitor C1, the second integrating capacitor C2, and the operational amplifier op is disconnected. The first integrating capacitor C1 and the second integrating capacitor C2 are connected to the reference voltage VREF through the control circuit 12. At the same time, the connection between the output terminal of the operational amplifier op and the first integrating capacitor C1 and the second integrating capacitor C2 is disconnected through the control circuit 12.

[0080] After one cycle, the control circuit 12 disconnects the first integrating capacitor C1 from the reference voltage VREF, disconnects the second integrating capacitor C2 from the reference voltage VREF, connects the output of the operational amplifier op to the first integrating capacitor C1, and connects the output of the operational amplifier op to the second integrating capacitor C2, and outputs the initial residual error signal through the operational amplifier op.

[0081] The comparator 20 outputs the initial bitstream signal based on the initial residual error signal to the input of the integrator 10.

[0082] The residual error signal is obtained by integrating the initial bitstream signal using integrator 10.

[0083] The digital signal is output by sampling the total residual error signal output by the integrator 10 after N integrations through successive approximation analog-to-digital converter 30 and performing analog-to-digital conversion, where N≥1.

[0084] The comparator 20 outputs the bitstream signal based on the total residual error signal output by the integrator 10 after N integrations.

[0085] The total voltage signal output by the ADC circuit is obtained based on the code stream signal and the digital signal.

[0086] In this embodiment, the analog-to-digital conversion involves two stages, including:

[0087] Phase 1:

[0088] Initially, the ninth sampling switch S5a and the tenth sampling switch S5b are disconnected, thus disconnecting the sampling circuit 11 from the first integrating capacitor C1, the second integrating capacitor C2, and the operational amplifier op. The control circuit 12 connects the first and second terminals of the first integrating capacitor C1 to the reference voltage VREF, and also connects the first and second terminals of the second integrating capacitor C2 to the reference voltage VREF. Simultaneously, the control circuit 12 disconnects the connection between the first output terminal of the operational amplifier op and the second terminal of the first integrating capacitor C1, and also disconnects the connection between the second output terminal of the operational amplifier op and the second terminal of the second integrating capacitor C2. This means closing the first switch S6a, the second switch S6b, the third switch S7a, and the fourth switch S7b, and opening the fifth switch S8a and the sixth switch S8b, thereby pre-charging the first integrating capacitor C1 and the second integrating capacitor C2.

[0089] After one cycle, control circuit 12 disconnects the first and second terminals of the first integrating capacitor C1 from the reference voltage VREF, disconnects the first and second terminals of the second integrating capacitor C2 from the reference voltage VREF, connects the first output terminal of operational amplifier op to the second terminal of the first integrating capacitor C1, and connects the second output terminal of operational amplifier op to the second terminal of the second integrating capacitor C2. Operational amplifier op then outputs a first initial residual error signal, i.e., it opens the first switch S6a, the second switch S6b, the third switch S7a, and the fourth switch S7b, and closes the fifth switch S8a and the sixth switch S8b. After operational amplifier op stably outputs the first initial residual error signal, if operational amplifier op does not have a first offset voltage DV1, the first initial residual error signal is zero; if operational amplifier op has a first offset voltage DV1, the first initial residual error signal is the first offset voltage DV1.

[0090] After obtaining the first initial residual error signal, the comparator 20 outputs the first initial code stream signal based on the first initial residual error signal and sends it to the input of the integrator 10.

[0091] Simultaneously, integrator 10 begins its first phase of normal operation, where the first sampling switch S1a and the fourth sampling switch S1b alternately switch between being closed and open, while the second sampling switch S2a and the third sampling switch S2b are open. The seventh sampling switch S4a and the eighth sampling switch S4b close and open as the first sampling switch S1a and the fourth sampling switch S1b close. When the first sampling switch S1a, the fourth sampling switch S1b, the seventh sampling switch S4a, and the eighth sampling switch S4b are all open, the fifth sampling switch S3a, the sixth sampling switch S3b, the ninth sampling switch S5a, and the tenth sampling switch S5b close.

[0092] The first initial code stream signal is integrated by the integrator 10 to obtain the first residual error signal. The comparator 20 then outputs the code stream signal based on the first residual error signal and sends it to the input of the integrator 10. The integrator 10 then repeatedly integrates in this way.

[0093] The comparator 20 outputs the first bitstream signal DT1 based on the first total residual error signal output by the integrator 10 after N integrations.

[0094] The first digital signal D1 is output by sampling the first total residual error signal output by the integrator 10 after N integrations through successive approximation analog-to-digital converter 30 and performing analog-to-digital conversion, where N≥1.

[0095] The first total voltage signal P output by the hybrid ADC circuit in the first stage is obtained based on the first code stream signal DT1 and the first digital signal D1. OUT =DT1*2 NS +D1=DT1*2 NS +(D1_offset+D1_int), where NS is the accuracy of the successive approximation analog-to-digital converter 30, and when the operational amplifier op has a first offset voltage, D1_offset is the offset signal corresponding to the first offset voltage DV1, and D1_int is the signal obtained after N integrations of the first residual error signal corresponding to the first initial residual error signal being 0.

[0096] Phase Two:

[0097] Initially, the ninth sampling switch S5a and the tenth sampling switch S5b are disconnected, thus disconnecting the sampling circuit 11 from the first integrating capacitor C1, the second integrating capacitor C2, and the operational amplifier op. The control circuit 12 connects the first and second terminals of the first integrating capacitor C1 to the reference voltage VREF, and also connects the first and second terminals of the second integrating capacitor C2 to the reference voltage VREF. Simultaneously, the control circuit 12 disconnects the connection between the first output terminal of the operational amplifier op and the second terminal of the first integrating capacitor C1, and also disconnects the connection between the second output terminal of the operational amplifier op and the second terminal of the second integrating capacitor C2. This means closing the first switch S6a, the second switch S6b, the third switch S7a, and the fourth switch S7b, and opening the fifth switch S8a and the sixth switch S8b, thereby pre-charging the first integrating capacitor C1 and the second integrating capacitor C2.

[0098] After one cycle, control circuit 12 disconnects the first and second terminals of the first integrating capacitor C1 from the reference voltage VREF, disconnects the first and second terminals of the second integrating capacitor C2 from the reference voltage VREF, connects the first output terminal of operational amplifier op to the second terminal of the first integrating capacitor C1, and connects the second output terminal of operational amplifier op to the second terminal of the second integrating capacitor C2. Operational amplifier op then outputs a second initial residual error signal, i.e., it opens the first switch S6a, the second switch S6b, the third switch S7a, and the fourth switch S7b, and closes the fifth switch S8a and the sixth switch S8b. After operational amplifier op stably outputs the second initial residual error signal, if operational amplifier op does not have a second offset voltage DV2, the second initial residual error signal is zero; if operational amplifier op has a second offset voltage DV2, the second initial residual error signal is the second offset voltage DV2.

[0099] After obtaining the second initial residual error signal, the comparator 20 outputs the second initial code stream signal based on the second initial residual error signal and sends it to the input of the integrator 10.

[0100] Simultaneously, integrator 10 begins its second phase of normal operation, where the second sampling switch S2a and the third sampling switch S2b alternately switch between being closed and open, while the first sampling switch S1a and the fourth sampling switch S1b remain open. The seventh sampling switch S4a and the eighth sampling switch S4b close and open as the second and third sampling switches S2a and S2b close. When the second and third sampling switches S2a and S2b, and the seventh and eighth sampling switches S4a and S4b are all open, the fifth, sixth, ninth, and tenth sampling switches S5a and S5b close.

[0101] The second initial code stream signal is integrated by integrator 10 to obtain the second residual error signal. Comparator 20 then outputs the code stream signal based on the second residual error signal and sends it to the input of integrator 10. Integrator 10 repeatedly integrates in this way.

[0102] The comparator 20 outputs the second bitstream signal DT2 based on the second total residual error signal output by the integrator 10 after N integrations.

[0103] The second digital signal D2 is output by sampling the second total residual error signal output by the integrator 10 after N integrations through successive approximation analog-to-digital converter 30 and performing analog-to-digital conversion, where N≥1.

[0104] The second total voltage signal N, output by the hybrid ADC circuit in the second stage, is obtained based on the second code stream signal DT2 and the second digital signal D2. OUT =DT2*2 NS +D2=DT2*2 NS +(D2_offset+D2_int), where NS is the accuracy of the successive approximation analog-to-digital converter 30, and when the operational amplifier op has a second offset voltage, D2_offset is the offset signal corresponding to the second offset voltage DV2, and D2_int is the signal obtained after N integrations of the second residual error signal corresponding to the second initial residual error signal being 0.

[0105] After the first and second phases are completed, based on the first total voltage signal P OUT Second total voltage signal N OUT Obtain the total voltage output signal D_OUT of the ADC circuit = (DT1*2) NS +D1_int)-(DT2*2 NS +D2_int)=P OUT -N OUT .

[0106] In this embodiment, the first stage and the second stage can each be implemented once or alternately multiple times.

[0107] In this embodiment, the order in which the first terminal of the first integrating capacitor C1 is disconnected from the reference voltage VREF and the order in which the second terminal of the first integrating capacitor C1 is disconnected from the reference voltage VREF, as well as the order in which the first terminal of the second integrating capacitor C2 is disconnected from the reference voltage VREF and the order in which the second terminal of the second integrating capacitor C2 is disconnected from the reference voltage VREF, can all be preset as needed. Specifically, this can be achieved by controlling the disconnection order of the first switch S6a, the second switch S6b, the third switch S7a, and the fourth switch S7b of the control circuit 12. In one embodiment, the first switch S6a and the third switch S7a can be disconnected first, and the second switch S6b and the fourth switch S7b can be disconnected after a certain delay. This can reduce glitches generated in the output signal when the switches are disconnected simultaneously. The delay time is generally on the order of nanoseconds.

[0108] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A hybrid ADC circuit, characterized by, The application relates to an integrator, a comparator and a successive approximation analog-to-digital converter. The integrator comprises a sampling circuit, an operational amplifier, a first integration capacitor, a second integration capacitor and a control circuit. The sampling circuit is used for sampling a differential signal to output a sampling signal. The first input end and the second input end of the operational amplifier are connected with the output end of the sampling circuit. The first end of the first integration capacitor is connected with the first input end of the operational amplifier. The second end of the first integration capacitor is connected with the first output end of the operational amplifier. The first end of the second integration capacitor is connected with the second input end of the operational amplifier. The second end of the second integration capacitor is connected with the second output end of the operational amplifier. The control circuit is used for controlling the communication and disconnection between the first end and the second end of the first integration capacitor and a reference voltage, between the first end and the second end of the second integration capacitor and the reference voltage, between the first output end of the operational amplifier and the second end of the first integration capacitor, and between the second output end of the operational amplifier and the second end of the second integration capacitor. The comparator is connected with the first output end and the second output end of the operational amplifier and outputs a corresponding code stream signal to the input end of the integrator. The successive approximation analog-to-digital converter is used for sampling and analog-to-digital converting the signal output by the integrator after N times of integration to output a digital signal, wherein N is greater than or equal to 1.

2. The hybrid ADC circuit of claim 1, wherein, The control circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch. The first end of the first switch is connected with the first end of the first integration capacitor. The first end of the second switch is connected with the second end of the first integration capacitor. The second end of the first switch and the second end of the second switch are connected with a power supply voltage. The first end of the third switch is connected with the first end of the second integration capacitor. The first end of the fourth switch is connected with the second end of the second integration capacitor. The second end of the third switch and the second end of the fourth switch are connected with the power supply voltage. The first end of the fifth switch is connected with the first output end of the operational amplifier. The second end of the fifth switch is connected with the second end of the first integration capacitor, the first input end of the comparator and the first input end of the successive approximation analog-to-digital converter. The first end of the sixth switch is connected with the second output end of the operational amplifier. The second end of the sixth switch is connected with the second end of the second integration capacitor, the second input end of the comparator and the second input end of the successive approximation analog-to-digital converter. The sampling circuit comprises a chopping unit, a first sampling capacitor, a second sampling capacitor, a first switch unit, a second switch unit and a third switch unit. The first end of the first sampling capacitor is connected with the chopping unit and the first switch unit. The first switch unit is simultaneously connected with the power supply voltage. The second end of the first sampling capacitor is connected with the second switch unit and the third switch unit. The second switch unit is simultaneously connected with a common-mode voltage. The third switch unit is simultaneously connected with the input end of the operational amplifier.

3. The hybrid ADC circuit of claim 2, wherein, The chopping unit comprises a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch, a first end of the first sampling switch is connected with a first end of the second sampling switch to form a first input end, a first end of the third sampling switch is connected with a first end of the fourth sampling switch to form a second input end, a second end of the first sampling switch is connected with a second end of the third sampling switch and a first end of a first sampling capacitor, a second end of the second sampling switch is connected with a second end of the fourth sampling switch and a first end of a second sampling capacitor; and / or The first switch unit comprises a fifth sampling switch and a sixth sampling switch, a first end of the fifth sampling switch is connected with the first end of the first sampling capacitor, a first end of the fifth sampling switch is connected with the first end of the second sampling capacitor, a second end of the fifth sampling switch and a second end of the sixth sampling switch are connected with a power supply voltage.

4. The hybrid ADC circuit of claim 2, wherein, The second switch unit comprises a seventh sampling switch and an eighth sampling switch, a first end of the seventh sampling switch is connected with a second end of the first sampling capacitor, a first end of the eighth sampling switch is connected with a second end of the second sampling capacitor, a second end of the seventh sampling switch and a second end of the eighth sampling switch are connected with a common-mode voltage; and / or The third switch unit comprises a ninth sampling switch and a tenth sampling switch, a first end of the ninth sampling switch is connected with the second end of the first sampling capacitor, a first end of the tenth sampling switch is connected with the second end of the second sampling capacitor, a second end of the ninth sampling switch and a second end of the tenth sampling switch are connected with an input end of an operational amplifier.

5. The hybrid ADC circuit of claim 1, wherein, The integrator is provided with n, n≥2, an input end of the successive approximation analog-to-digital converter is connected with an output end of a first integrator, an output end of the successive approximation analog-to-digital converter is connected with an input end of a second integrator, an input end of the comparator is connected with an output end of an n-th integrator, and an output end of the comparator is connected with an input end of the first integrator.

6. A chip, characterized by The hybrid ADC circuit comprises the hybrid ADC circuit according to any one of claims 1-5.

7. A method of analog-to-digital conversion, characterized by The hybrid ADC circuit comprises the hybrid ADC circuit according to any one of claims 1-5. At an initial moment, the connection between the sampling circuit and the first integration capacitor, the second integration capacitor and the operational amplifier is disconnected, the first integration capacitor is connected with the reference voltage and the second integration capacitor is connected with the reference voltage through the control circuit, and the output end of the operational amplifier is disconnected with the first integration capacitor and the second integration capacitor through the control circuit; After one period, the connection between the first integration capacitor and the reference voltage and the connection between the second integration capacitor and the reference voltage are disconnected through the control circuit, the output end of the operational amplifier is connected with the first integration capacitor and the second integration capacitor, and an initial residual error signal is outputted by the operational amplifier; An initial code stream signal is outputted by the comparator based on the initial residual error signal to the input end of the integrator; The initial code stream signal is integrated by the integrator to obtain a residual error signal; and The initial code stream signal is integrated by the integrator to obtain a residual error signal. The total residual error signal outputted by the successive approximation analog-to-digital converter sampling integrator after N times of integration is converted into a digital signal by analog-to-digital conversion, and N≥1; The code stream signal is outputted by the comparator based on the total residual error signal outputted by the integrator after N times of integration; The total voltage signal outputted by the ADC circuit is obtained based on the code stream signal and the digital signal.

8. The method of analog-to-digital conversion according to claim 7, wherein, The analog-to-digital conversion method comprises one or more first stages and second stages, and the polarity of the signal sampled by the integrator in the first stage is opposite to that of the signal sampled in the second stage; In the first stage: The first initial code stream signal is outputted by the comparator based on the first initial residual error signal outputted by the operational amplifier to the input end of the integrator; The first residual error signal is obtained by integrating the first initial code stream signal by the integrator; The first code stream signal is outputted by the comparator based on the first total residual error signal outputted by the integrator after N times of integration; The first digital signal is outputted by the successive approximation analog-to-digital converter sampling the first total residual error signal outputted by the integrator after N times of integration and performing analog-to-digital conversion; The first total voltage signal outputted by the ADC circuit is obtained based on the first code stream signal and the first digital signal; In the second stage: The second initial code stream signal is outputted by the comparator based on the second initial residual error signal outputted by the operational amplifier to the input end of the integrator; The second residual error signal is obtained by integrating the second initial code stream signal by the integrator; The second code stream signal is outputted by the comparator based on the second total residual error signal outputted by the integrator after N times of integration; The second digital signal is outputted by the successive approximation analog-to-digital converter sampling the second total residual error signal outputted by the integrator after N times of integration and performing analog-to-digital conversion; The second total voltage signal outputted by the ADC circuit is obtained based on the second code stream signal and the second digital signal; After the first stage and the second stage are completed, the total voltage output signal outputted by the ADC circuit is obtained based on the first total voltage signal and the second total voltage signal.

9. The method of analog-to-digital conversion according to claim 7, wherein, The first end of the first integration capacitor is disconnected from the reference voltage and the second end of the first integration capacitor is disconnected from the reference voltage in a preset order by the control circuit, and the first end of the second integration capacitor is disconnected from the reference voltage and the second end of the second integration capacitor is disconnected from the reference voltage in a preset order by the control circuit.

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