Data receiving device, method and chip for power line carrier communication

Abstract

The present invention discloses a data receiving device, method and chip for power carrier communication. The device includes a front-end processing unit, which is used to perform analog-to-digital conversion, scaling processing and filtering processing on the received analog signal to obtain a first digital signal; a digital gain unit, which is used to power amplify the first digital signal to obtain a second digital signal; a digital compensation unit, including a first power error calculator, a first integral controller and a judge, the first power error calculator is used to obtain the difference between the first target power and the power of the second digital signal to obtain a first power difference, the first integral controller is used to integrate the first power difference to obtain a first integral gain value, and the judge is used to determine the power amplification gain value of the digital gain unit according to the size relationship between the first integral gain value and the preset threshold value. In this way, not only the rapid tracking of power changes is achieved, and the system performance is effectively improved, but also the implementation complexity is simplified and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data receiving device, method and chip for power line carrier communication. Background Art

[0002] In the communication system, it is necessary to process signals with different sensitivity ranges, and the bit width of the analog-to-digital converter is limited. This requires the communication system to attenuate large signals and amplify small signals, and adjust the signal amplitude to a suitable range by adjusting the appropriate gain to achieve its best demodulation effect. As the input signal changes continuously, the gain will also change accordingly to automatically maintain the output signal amplitude and limit it to a reasonable range. This is the automatic gain control algorithm. The automatic gain control algorithm in the related art, when using proportional integral control, leads to complex gain control calculation and high power consumption, and when using integral control, it leads to slow system tracking speed and poor system performance. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the purpose of the present invention is to propose a data receiving device, method and chip for power carrier communication, which determines the power amplification gain value of the digital gain unit according to the size relationship between the first integral gain value and the preset threshold value, can achieve rapid tracking of power changes, effectively improve system performance, and at the same time, only the first power difference is integrated to obtain the first integral gain value, which simplifies the implementation complexity of gain control and reduces power consumption. Therefore, combining the integral processing and determining the power amplification gain value according to the size relationship between the first integral gain value and the preset threshold value can not only eliminate static errors and ensure the following speed, but also reduce the computational complexity, reduce power consumption, reduce delays, and effectively improve system performance.

[0004] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a data receiving device for power carrier communication, the device comprising: a front-end processing unit, used to perform analog-to-digital conversion, scaling processing and filtering processing on the received analog signal to obtain a first digital signal; a digital gain unit, the digital gain unit is connected to the front-end processing unit, and is used to power amplify the first digital signal to obtain a second digital signal; a digital compensation unit, the digital compensation unit is connected to the digital gain unit, and the digital compensation unit comprises a first power error calculator, a first integral controller and a judge, wherein the first power error calculator is used to obtain the difference between the first target power and the power of the second digital signal to obtain a first power difference, the first integral controller is used to integrate the first power difference to obtain a first integral gain value, and the judge is used to determine the power amplification gain value of the digital gain unit according to the size relationship between the first integral gain value and a preset threshold value.

[0005] In some embodiments of the present invention, the judgement device is specifically used to: adjust the first integral gain value and the multiple gain value according to the size relationship between the first integral gain value and the preset threshold value, and determine the power amplification gain value of the digital gain unit according to the adjusted first integral gain value and the multiple gain value.

[0006] In some embodiments of the present invention, the judgement device is specifically used to: when the first integral gain value is greater than a first preset threshold value, reduce the first integral gain value by a first preset multiple and amplify the multiple gain value by a first preset multiple; when the first integral gain value is less than a second preset threshold value, amplify the first integral gain value by a second preset multiple and reduce the multiple gain value by a second preset multiple; when the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, keep the first integral gain value and the multiple gain value unchanged.

[0007] In some embodiments of the present invention, the decision device is specifically used to obtain the power amplifier gain value through the following formula: Gain = 2^GainE*GainM, where Gain is the power amplifier gain value, GainE is the adjusted multiple gain value, and GainM is the adjusted first integral gain value.

[0008] In some embodiments of the present invention, the first integral controller is specifically used to: when the first power difference is greater than a first preset power limit, integrate the first power difference to obtain a first integral gain value.

[0009] In some embodiments of the present invention, the first integral controller is further configured to perform smoothing filtering on the first power difference.

[0010] In some embodiments of the present invention, the front-end processing unit includes: a front-end processing sub-unit, which is used to perform analog-to-digital conversion and scaling processing on the analog signal to obtain a third digital signal; and a digital filtering sub-unit, which is connected to the front-end processing sub-unit and is used to filter the third digital signal to obtain the first digital signal.

[0011] In some embodiments of the present invention, the front-end processing subunit includes an analog gain amplifier, an analog-to-digital converter and a digital gain amplifier connected in sequence, the analog gain amplifier is used to scale the analog signal, the analog-to-digital conversion unit is used to perform analog-to-digital conversion on the scaled analog signal to obtain a fourth digital signal, and the digital gain amplifier is used to scale the fourth digital signal to obtain a third digital signal.

[0012] In some embodiments of the present invention, the device further comprises: a gain controller connected to the front-end processing subunit and configured to determine scaling gain values ​​of the analog gain amplifier and the digital gain amplifier.

[0013] In some embodiments of the present invention, the gain controller includes: a second power error calculator, a second integral controller and a gain decomposer, the second power error calculator is used to obtain the difference between the second target power and the power of the third digital signal to obtain a second power difference, the second integral controller is used to integrate the second power difference to obtain a second integral gain value, and the gain decomposer is used to decompose the second integral gain value to obtain the scaling gain values ​​of the analog gain amplifier and the digital gain amplifier.

[0014] In some embodiments of the present invention, the second integral controller is specifically configured to integrate the second power difference to obtain a second integral gain value when the second power difference is greater than the second power limit.

[0015] In some embodiments of the present invention, the second integral controller is further configured to perform smoothing filtering on the second power difference.

[0016] In some embodiments of the present invention, the gain decomposer is specifically used to: when the second integral gain value is greater than the effective gain range of the analog gain amplifier, set the scaling gain value of the analog gain amplifier to the maximum gain value of the analog gain amplifier, and set the scaling gain value of the digital gain amplifier to the gain difference between the second integral gain value and the maximum gain value; when the second integral gain value is less than or equal to the effective gain range of the analog gain amplifier, set the scaling gain of the analog gain amplifier to the second integral gain value, and set the scaling gain value of the digital gain amplifier to zero.

[0017] In some embodiments of the present invention, the device also includes: a synchronization unit, which is connected to the digital gain unit and is used to determine the frame boundary of the second digital signal; and a demodulation and decoding unit, which is connected to the synchronization unit and is used to demodulate and decode the second digital signal based on the frame boundary to obtain the original signal.

[0018] To achieve the above objective, a second aspect of the present invention provides a chip, comprising a power line carrier communication receiving device according to any one of the above embodiments.

[0019] To achieve the above-mentioned purpose, the third aspect of the embodiment of the present invention proposes a data receiving method for power carrier communication, the method comprising: performing analog-to-digital conversion, scaling processing and filtering processing on the received analog signal to obtain a first digital signal, and power amplifying the first digital signal to obtain a second digital signal; obtaining the difference between the first target power and the power of the second digital signal to obtain a first power difference, and integrating the first power difference to obtain a first integral gain value; determining the power amplification gain value according to the relationship between the first integral gain value and a preset threshold value.

[0020] To achieve the above-mentioned purpose, the fourth aspect of the present invention proposes another chip, including: a memory, a processor, and a data receiving program for power carrier communication stored in the memory and executable on the processor. When the processor executes the data receiving program for power carrier communication, the embodiment of the above-mentioned data receiving method for power carrier communication is implemented.

[0021] According to the data receiving device, method and chip for power carrier communication of the embodiment of the present invention, the first digital signal is obtained by performing analog-to-digital conversion, scaling processing and filtering processing on the received analog signal, and the first digital signal is power-amplified to obtain the second digital signal, and the difference between the first target power and the power of the second digital signal is obtained to obtain the first power difference, and the first power difference is integrated to obtain the first integral gain value, and the power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value. The power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value, which can realize the rapid tracking of power changes and effectively improve the system performance. At the same time, only the first power difference is integrated to obtain the first integral gain value, which simplifies the implementation complexity of gain control and reduces power consumption. Therefore, the integration processing and the power amplification gain value determined according to the size relationship between the first integral gain value and the preset threshold value are combined with each other, which can not only eliminate static errors and ensure the following speed, but also reduce the calculation complexity, reduce power consumption, reduce delay, and effectively improve system performance.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 It is a structural block diagram of a data receiving device for power line carrier communication according to an embodiment of the present invention.

[0025] Figure 2 It is a structural block diagram of a data receiving device for power line carrier communication according to another embodiment of the present invention.

[0026] Figure 3 It is a structural block diagram of a data receiving device for power line carrier communication according to another embodiment of the present invention.

[0027] Figure 4 It is a structural block diagram of a data receiving device for power line carrier communication according to another embodiment of the present invention.

[0028] Figure 5 The present invention is a block diagram of a chip having a data receiving device for power line carrier communication according to an embodiment of the present invention.

[0029] Figure 6 It is a flowchart of a data receiving method for power line carrier communication according to an embodiment of the present invention.

[0030] Figure 7 It is a structural block diagram of a chip having a data receiving device for power line carrier communication according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0032] The following describes in detail a data receiving device, method and chip for power line carrier communication according to an embodiment of the present invention in conjunction with the accompanying drawings.

[0033] Figure 1 It is a structural block diagram of a data receiving device for power line carrier communication according to an embodiment of the present invention.

[0034] like Figure 1 As shown, the data receiving device 10 for power carrier communication includes: a front-end processing unit 100 , a digital gain unit 200 and a digital compensation unit 300 .

[0035] Among them, the front-end processing unit 100 is used to perform analog-to-digital conversion, scaling processing and filtering processing on the received analog signal to obtain a first digital signal; the digital gain unit 200 is connected to the front-end processing unit 100, and is used to power amplify the first digital signal to obtain a second digital signal; the digital compensation unit 300 is connected to the digital gain unit 200, and the digital compensation unit 300 includes a first power error calculator 302, a first integral controller 304 and a judge 306, the first power error calculator 302 is used to obtain the difference between the first target power and the power of the second digital signal to obtain a first power difference, the first integral controller 304 is used to integrate the first power difference to obtain a first integral gain value, and the judge 306 is used to determine the power amplification gain value of the digital gain unit according to the size relationship between the first integral gain value and a preset threshold value.

[0036] Specifically, the signal received by the front-end processing unit 100 is an analog signal, so it is necessary to set an analog-to-digital converter to convert the analog-to-digital signal into a digital signal for subsequent processing; at the same time, in order to improve the conversion accuracy and avoid the analog signal being too large or too small, an analog gain amplifier can be set before the analog-to-digital converter to reduce or amplify the analog signal through the analog gain amplifier; at the same time, in order to ensure that the converted digital signal is within a certain amplitude range, a digital gain amplifier can also be set after the analog-to-digital converter to reduce or amplify the converted digital signal through the digital gain amplifier. Furthermore, a filter can also be set after the digital gain amplifier to filter the reduced or amplified digital signal through the filter to filter out the out-of-band interference and narrowband interference in the digital signal, and finally obtain the first digital signal.

[0037] It should be noted that when there is large out-of-band interference and narrowband interference in the system, the power of the first digital signal obtained after filtering will be greatly attenuated, affecting the performance of the system. Therefore, a digital gain unit 200 is provided after the filter. The digital gain unit 200 performs power amplification on the first digital signal to obtain the second digital signal, and the digital gain unit 200 is compensated by the digital compensation unit 300.

[0038] Specifically, PID (Proportional Integral Differential) control is a widely used control method in automatic control theory. It responds to changes in the regulated quantity by using one or more of proportional control, integral control and differential control to stabilize the system in a desired state. Among them, proportional control is used to control the response speed of the system to ensure that it can act on the output quickly; integral control is used to control the accuracy of the system to eliminate cumulative errors; differential control is used to control the stability of the system and has a leading control effect.

[0039] Considering that although proportional control can quickly respond to changes in system gain, it cannot eliminate steady-state errors, and an excessively large open-loop proportional coefficient will not only increase the overshoot of the system, but also reduce the system stability margin, or even make it unstable, and an excessively small open-loop proportional coefficient will not play a practical role. At the same time, as long as there is an error in the system, the integral control will continue to accumulate to eliminate the error, so as long as there is enough time, the integral control can completely eliminate the error, making the system error zero, thereby eliminating the steady-state error. In the power line carrier communication system, the carrier frame interval is at least 400 microseconds, which is enough time to ensure that the integral control responds to the signal power change, and the existence of differential control is not very meaningful, but increases the complexity of implementation. Therefore, in the embodiment of the present invention, only the power error is integrated to obtain the first integral gain value. Thereby greatly reducing the computational complexity of the gain control, and the processing delay is small, which is suitable for power line communication engineering.

[0040] Furthermore, since the simple integral control cannot quickly respond to the system power change, in order to realize the rapid compensation of the digital gain unit 200, the decision device 306 is introduced in the digital compensation unit 300, and the power amplification gain value of the digital gain unit 200 is determined by the decision device 306. Specifically, the first power error calculator 302 can first calculate the difference between the first target power (which can be predetermined) and the power of the second digital signal to obtain the first power difference, and then the first integral controller 304 integrates the first power difference to obtain the first integral gain value, and finally the decision device 306 determines the power amplification gain value of the digital gain unit according to the magnitude relationship between the first integral gain value and the preset threshold value. In this way, not only can the rapid tracking of power changes be realized, the system response speed is met, and the system performance is effectively improved, but also only the integral processing is performed in the digital compensation unit, which simplifies the implementation complexity and reduces the power consumption.

[0041] Therefore, with the cooperation between the first integral controller and the decision device, not only can the static error be eliminated, but also the response speed is fast, the calculation complexity is small, the processing delay is small, and the system performance is good.

[0042] In some embodiments, the determiner 306 is specifically used to: adjust the first integral gain value and the multiple gain value according to the size relationship between the first integral gain value and the preset threshold value, and determine the power amplification gain value of the digital gain unit according to the adjusted first integral gain value and the multiple gain value.

[0043] As an implementation method, the judge 306 is specifically used to: when the first integral gain value is greater than the first preset threshold value, reduce the first integral gain value by a first preset multiple and amplify the multiple gain value by the first preset multiple; when the first integral gain value is less than the second preset threshold value, amplify the first integral gain value by a second preset multiple and reduce the multiple gain value by the second preset multiple; when the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, keep the first integral gain value and the multiple gain value unchanged.

[0044] For example, assuming that the initial value of the multiple gain value GainE is 1, and the first preset multiple and the second preset multiple are both 2. Then, after obtaining the first integral gain value GainM, if GainM> the first preset threshold value, the first integral gain value GainM is halved, and the multiple gain value GainE is doubled, that is, GainM=GainM / 2, GainE=GainE*2; if GainM< the second preset threshold value, the first integral gain value GainM is doubled, and the multiple gain value GainE is halved, that is, GainM=GainM*2, GainE=GainE / 2; if the second preset threshold value ≤GainM≤the first preset threshold value, the first integral gain value GainM and the multiple gain value GainE are kept unchanged. Therefore, by halving or doubling the first integral gain value GainM, the first integral gain value GainM can be converged quickly, thereby realizing rapid tracking of power changes.

[0045] Further, after adjusting the first integral gain value GainM and the multiple gain value GainE, the decision device 306 can obtain the power amplification gain value through the following formula:

[0046] Gain=2^GainE*GainM (1)

[0047] Wherein, Gain is the power amplifier gain value, GainE is the adjusted multiple gain value, and GainM is the adjusted first integral gain value.

[0048] It can be understood that when the first integral gain value GainM is greater than the first preset threshold value, the first integral gain value GainM is adjusted to GainM / 2, the multiple gain value GainE is adjusted to 2*GainE, and the corresponding power amplification gain value Gain is 2^(2*GainE)*(GainM / 2); when the first integral gain value GainM is less than the second preset threshold value, the first integral gain value GainM is adjusted to 2*GainM, the multiple gain value GainE is adjusted to GainE / 2, and the corresponding power amplification gain value Gain is 2^(GainE / 2)*(2*GainM); when the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, the power amplification gain value Gain is 2^GainE*GainM. It can be seen from the formula that by halving or doubling the first integral gain value GainM, the first integral gain value GainM can converge quickly, thereby achieving rapid tracking of power changes. After the power amplification gain value is obtained, the digital gain unit 200 may be compensated.

[0049] It should be noted that the above example speeds up the power tracking speed by doubling or halving the power error, thereby improving the system performance. In practical applications, it is not limited to doubling or halving, and other parameters or weighted processing methods can also be used, which should all fall within the scope of protection of this application.

[0050] In some embodiments, the first integral controller 304 is specifically configured to: when the first power difference is greater than a first preset power limit, integrate the first power difference to obtain a first integral gain value.

[0051] Specifically, when the digital compensation unit 300 adjusts the power amplification gain value based on the target power, there will be a problem of frequent adjustment of the power amplification gain value near the target power, which will cause the power amplification gain value to jitter rapidly within a certain range, resulting in signal spurious in the digital domain, affecting the system performance. Therefore, in the digital compensation unit 300, it is first determined whether the first power difference is greater than the first preset power limit. If so, the first integral controller 304 integrates the first power difference to obtain the first integral gain value, otherwise, no integral processing is performed. Thus, by adding a threshold judgment to the power error, and when the threshold is not exceeded, gain adjustment is prohibited to avoid gain jitter.

[0052] In some embodiments, the first integral controller 304 is further configured to perform smoothing filtering on the first power difference.

[0053] For example, assuming that the first target power is targetpower1 and the power of the second digital signal is power1, then the first power difference error1 between the first target power and the power of the second digital signal is equal to targetpower1-power1; then, the first power difference error1 is smoothed and filtered to obtain the first power difference erroravg1 after filtering, which can be specifically expressed by the following formula (2):

[0054] erroravg1=erroravg1-(erroravg1-error)*K (2)

[0055] Where K is the coefficient of the smoothing filter.

[0056] Then, it is determined whether the first power difference erroravg1 after filtering is greater than the first preset power limit. If so, the first power difference erroravg1 after filtering is integrated to obtain a first integral gain value:

[0057] GainM(n)=GainM(n-1)+erroravg1*Ki (3)

[0058] Wherein, GainM(n) is the first integral gain value of the current signal, GainM(n-1) is the first integral gain value of the previous signal, and Ki is the integral coefficient.

[0059] If the first power difference erroravg1 is not greater than the first preset power limit, the first power difference erroravg1 is not integrated, that is, the first integral gain value remains unchanged:

[0060] GainM(n)=GainM(n-1) (4)

[0061] Therefore, by performing smoothing filtering on the first power difference, and based on the size relationship between the first power difference after filtering and the first preset power limit, it is determined whether the first power difference needs to be integrated, so that when necessary, only the first power difference is integrated to obtain the first integral gain value, which can effectively avoid the problem of gain jitter caused by frequent gain adjustment, resulting in spurious distribution of digital domain signals, reduce the computational complexity of gain control, reduce processing delay, simplify the implementation complexity of the data receiving device, reduce the power consumption of the data receiving device, and is conducive to application in the data receiving system of power carrier communication.

[0062] In some embodiments, reference Figure 2As shown, the front-end processing unit 100 includes: a front-end processing subunit 102 and a digital filtering subunit 104. The front-end processing subunit 102 is used to perform analog-to-digital conversion and scaling processing on the analog signal to obtain a third digital signal; the digital filtering subunit 104 is connected to the front-end processing subunit 102 and is used to perform filtering processing on the third digital signal to obtain the first digital signal.

[0063] In certain embodiments, continue to refer to Figure 2 , the front-end processing subunit 102 includes: an analog gain amplifier A1 (APGC), an analog-to-digital converter A2 (ADC) and a digital gain amplifier A3 (DPGA) connected in sequence. Among them, the analog gain amplifier A1 is used to scale the analog signal, such as reducing or amplifying the received power carrier analog signal; the analog-to-digital converter A2 is used to perform analog-to-digital conversion on the scaled analog signal to obtain a fourth digital signal, such as performing analog-to-digital conversion on the reduced or amplified analog signal to obtain a fourth digital signal; the digital gain amplifier A3 is used to scale the fourth digital signal to obtain a third digital signal, such as reducing or amplifying the fourth digital signal to obtain a third digital signal. Then, the digital filtering subunit 104, such as a filter, filters the third digital signal to obtain the first digital signal. It can be understood that due to the channel characteristics of the power carrier communication, there are a large number of narrowband interference and pulse interference in the channel, so the filtering process is usually to filter out the out-of-band interference and narrowband interference of the third digital signal.

[0064] In this way, the received analog signal is scaled by the front-end processing subunit 102 and then converted into a digital signal so that the digital signal can be processed inside the data receiving device, and noise interference is filtered out by the digital filtering subunit 104, which helps to improve the performance of the data receiving system of the power carrier communication.

[0065] In some embodiments, reference Figure 3 As shown, the data receiving device 10 for power carrier communication further includes: a gain controller 400 , which is connected to the front-end processing subunit 102 and is used to determine the scaling gain values ​​of the analog gain amplifier A1 and the digital gain amplifier A3 .

[0066] Specifically, the gain controller 400 performs gain calculation based on the data of the output signal of the front-end processing sub-unit 102, and feeds back the calculation result to the analog gain amplifier A1 and the digital gain amplifier A3 in the front-end processing sub-unit 102, so that after the analog gain amplifier A1 reduces or amplifies the analog signal, the amplitude of the analog signal is within a reasonable range. At the same time, after the digital gain amplifier A3 reduces or amplifies the digital signal obtained by analog-to-digital conversion, it is also within the corresponding range.

[0067] In some embodiments, continue to refer to Figure 3 The gain controller 400 includes: a second power error calculator 402, a second integral controller 404 and a gain decomposer 406. The second power error calculator 402 is used to obtain the difference between the second target power and the power of the third digital signal to obtain a second power difference; the second integral controller 404 is used to integrate the second power difference to obtain a second integral gain value; the gain decomposer 406 is used to decompose the second integral gain value to obtain the scaling gain values ​​of the analog gain amplifier A1 and the digital gain amplifier A3.

[0068] Specifically, the second target power may be a pre-set power value of the front-end processing subunit 102 that is expected to output data, the second target power may be expressed as targetpower2, and the power of the third digital signal may be expressed as power2. The difference between the second target power targetpower2 and the power power2 of the third digital signal, i.e., the second power difference error2 is targetpower2-power2. It can be understood that the second integral gain value is the sum of the gain values ​​of the analog gain amplifier A1 and the digital gain amplifier A3, so the gain decomposer 406 is required to decompose the second integral gain value, and feed back the decomposed scaling gain value of the analog gain amplifier A1 to the analog gain amplifier A1, and feed back the scaling gain value of the digital gain amplifier A3 to the digital gain amplifier A3, so that the signal amplitude of the output data of the front-end processing subunit 102 can be within a reasonable range, and the data receiving power value can be ensured to be as close to the expected power value of the data as possible.

[0069] In some embodiments, the second integral controller 404 is specifically configured to integrate the second power difference to obtain a second integral gain value when the second power difference is greater than a second preset power limit.

[0070] In some embodiments, the second integral controller 404 is further configured to perform smoothing filtering on the second power difference.

[0071] It should be noted that, for the relevant description of the second power error calculator 402 and the second integral controller 404, please refer to the relevant description of the first power error calculator 302 and the first integral controller 304, which will not be repeated here.

[0072] In some embodiments, the gain decomposer 406 is specifically used to: when the second integral gain value is greater than the effective gain range of the analog gain amplifier A1, set the scaling gain value of the analog gain amplifier A1 to the maximum gain value of the analog gain amplifier A1, and set the scaling gain value of the digital gain amplifier A3 to the gain difference between the second integral gain value and the maximum gain value; when the second integral gain value is less than or equal to the effective gain range of the analog gain amplifier A1, set the scaling gain of the analog gain amplifier A1 to the second integral gain value, and set the scaling gain value of the digital gain amplifier A3 to zero.

[0073] It can be understood that when the gain of the analog gain amplifier A1 is within the preset gain range, it is considered to be an effective gain, and when it exceeds the preset gain range, it is considered to be an invalid gain. In some embodiments, if the second integral gain value GainM2 is greater than the effective gain range of the analog gain amplifier A1, the maximum gain value GainMmax of the analog gain amplifier A1 is used as the scaling gain value of the analog gain amplifier A1, and the difference between GainM2 and GainMmax is used as the scaling gain value of the digital gain amplifier A3; if GainM2 is less than or equal to the effective gain range of the analog gain amplifier A1, GainM2 is used as the scaling gain value of the analog gain amplifier A1, and the scaling gain value of the digital gain amplifier A3 is set to 0, that is, the digital gain amplifier A3 does not perform gain adjustment on the digital signal. It can be understood that in the communication channel, for analog gain and digital gain of the same size, the system interference generated by the analog gain is less than the system interference generated by the digital gain, so when performing gain decomposition, the decomposition of the analog gain is given priority.

[0074] In some embodiments, reference Figure 4 As shown, the data receiving device 10 for power carrier communication also includes: a synchronization unit 500 and a demodulation and decoding unit 600, the synchronization unit 500 is connected to the digital gain unit 200, and is used to determine the frame boundary of the second digital signal; the demodulation and decoding unit 600 is connected to the synchronization unit 500, and is used to demodulate and decode the second digital signal based on the frame boundary to obtain the original signal.

[0075] It can be understood that the gain controller 400 makes the amplitude of the output signal of the front-end processing subunit 102 within a reasonable range, and the digital compensation unit 300 quickly compensates for the signal power loss caused by the filtering of the digital filtering subunit 104. In this way, through the joint action of the gain controller 400 and the digital compensation unit 300, the automatic gain adjustment of the receiving side of the data receiving system of the power carrier communication is realized, ensuring that the signal amplitude of the data is within a reasonable range before the synchronization unit 500 processes, thereby achieving the best synchronization and demodulation effect. Afterwards, the frame boundary of the second digital signal output by the digital gain unit 200 is determined by the synchronization unit 500. The demodulation and decoding unit 600 performs a fast Fourier transform on the second digital signal to convert the time domain signal into a frequency domain signal, which is helpful for the subsequent frequency domain processing and bit-level processing of the signal, and finally recovers the received original data.

[0076] In summary, according to the data receiving device of the power carrier communication of the embodiment of the present invention, the gain controller performs gain calculation according to the signal output by the front-end processing unit, and feeds back the calculation result to the analog gain amplifier and the digital gain amplifier of the front-end, so that the signal amplitude output by the front-end processing unit is limited to a reasonable range; the digital compensator performs digital gain compensation on the digital signal after digital filtering to ensure that when the system has large out-of-band interference or large narrowband interference, the best synchronization and demodulation effect can still be achieved; according to the characteristics of the power line communication system, automatic gain control can be simply and quickly realized by using only integral processing, which simplifies the complexity of implementation and reduces power consumption; gain adjustment will cause the signal power to jitter rapidly near the expected power, causing digital domain signal spurious, affecting system performance, and increasing the power error threshold judgment. When the error is lower than the threshold value, the gain adjustment is no longer performed, thereby eliminating the jitter phenomenon; when the system has large out-of-band interference or large narrowband interference, after digital filtering, the signal power will be greatly attenuated. If the digital compensator cannot quickly track the power change, it will affect the system performance, and by adding the power error doubling / halving judgment in the digital compensator, the power change can be quickly tracked.

[0077] Corresponding to the above embodiment, an embodiment of the present invention further proposes a chip.

[0078] Figure 5 is a block diagram of a chip having a data receiving device for power carrier communication according to an embodiment of the present invention. Figure 5 As shown, the chip 20 includes the data receiving device 10 for power line carrier communication described in any one of the above embodiments.

[0079] According to the chip of the embodiment of the present invention, the first digital signal is obtained by performing analog-to-digital conversion, scaling processing and filtering processing on the received analog signal, and the first digital signal is power-amplified to obtain the second digital signal, and the difference between the first target power and the power of the second digital signal is obtained to obtain the first power difference, and the first power difference is integrated to obtain the first integral gain value, and the power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value. The power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value, which can realize the rapid tracking of power changes and effectively improve the system performance. At the same time, only the first power difference is integrated to obtain the first integral gain value, which simplifies the implementation complexity of gain control and reduces power consumption. Therefore, the integration processing and the determination of the power amplification gain value according to the size relationship between the first integral gain value and the preset threshold value are combined with each other, which can not only eliminate static errors and ensure the following speed, but also reduce the calculation complexity, reduce power consumption, reduce delay, and effectively improve system performance.

[0080] It should be pointed out that the above explanation of the embodiments and beneficial effects of the data receiving device for power line carrier communication is also applicable to the chip of the embodiment of the present invention, and will not be elaborated here in detail to avoid redundancy.

[0081] Corresponding to the above embodiment, an embodiment of the present invention further proposes a data receiving method for power line carrier communication.

[0082] Figure 6 FIG. 1 is a flow chart of a data receiving method for power line carrier communication according to an embodiment of the present invention. Figure 6 As shown, the method includes:

[0083] S11: performing analog-to-digital conversion, scaling processing, and filtering processing on the received analog signal to obtain a first digital signal, and performing power amplification on the first digital signal to obtain a second digital signal.

[0084] S13: Obtain a difference between the first target power and the power of the second digital signal to obtain a first power difference, and integrate the first power difference to obtain a first integral gain value.

[0085] S15: Determine a power amplification gain value according to a magnitude relationship between the first integral gain value and a preset threshold value.

[0086] In some embodiments of the present invention, a power amplification gain value is determined based on the size relationship between the first integral gain value and a preset threshold value, including: adjusting the first integral gain value and the multiple gain value based on the size relationship between the first integral gain value and the preset threshold value; and determining the power amplification gain value based on the adjusted first integral gain value and the multiple gain value.

[0087] In some embodiments of the present invention, the first integral gain value and the multiple gain value are adjusted according to the size relationship between the first integral gain value and the preset threshold value, including: when the first integral gain value is greater than the first preset threshold value, reducing the first integral gain value by a first preset multiple and amplifying the multiple gain value by a second preset multiple; when the first integral gain value is less than the second preset threshold value, amplifying the first integral gain value by a third preset multiple and reducing the multiple gain value by a fourth preset multiple; when the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, keeping the first integral gain value and the multiple gain value unchanged.

[0088] In some embodiments of the present invention, the power amplification gain value is obtained by the following formula: Gain=2^GainE*GainM.

[0089] According to the data receiving method for power carrier communication of the embodiment of the present invention, the first digital signal is obtained by performing analog-to-digital conversion, scaling processing and filtering processing on the received analog signal, and the first digital signal is power-amplified to obtain the second digital signal, and the difference between the first target power and the power of the second digital signal is obtained to obtain the first power difference, and the first power difference is integrated to obtain the first integral gain value, and the power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value. The power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value, which can realize the rapid tracking of power changes and effectively improve the system performance. At the same time, only the first power difference is integrated to obtain the first integral gain value, which simplifies the implementation complexity of gain control and reduces power consumption. Therefore, the integration processing and the power amplification gain value determined according to the size relationship between the first integral gain value and the preset threshold value are combined with each other, which can not only eliminate static errors and ensure the following speed, but also reduce the calculation complexity, reduce power consumption, reduce delay, and effectively improve system performance.

[0090] To implement the above embodiment, another chip is provided in the embodiment of the present invention. Figure 7 is a block diagram of a chip according to an embodiment of the present invention. Figure 7 As shown, the chip 700 includes: a memory 702, a processor 704, and a data receiving program 706 for power carrier communication stored in the memory 702 and executable on the processor 704. When the processor 704 executes the data receiving program 706 for power carrier communication, the embodiment of the data receiving method for power carrier communication described above is implemented.

[0091] According to the chip of the embodiment of the present invention, the first digital signal is obtained by performing analog-to-digital conversion, scaling processing and filtering processing on the received analog signal, and the first digital signal is power-amplified to obtain the second digital signal, and the difference between the first target power and the power of the second digital signal is obtained to obtain the first power difference, and the first power difference is integrated to obtain the first integral gain value, and the power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value. The power amplification gain value of the digital gain unit is determined according to the size relationship between the first integral gain value and the preset threshold value, which can realize the rapid tracking of power changes and effectively improve the system performance. At the same time, only the first power difference is integrated to obtain the first integral gain value, which simplifies the implementation complexity of gain control and reduces power consumption. Therefore, the integration processing and the determination of the power amplification gain value according to the size relationship between the first integral gain value and the preset threshold value are combined with each other, which can not only eliminate static errors and ensure the following speed, but also reduce the calculation complexity, reduce power consumption, reduce delay, and effectively improve system performance.

[0092] It should be noted that the above explanations of the embodiments and beneficial effects of the power carrier communication receiving device are also applicable to the chip 700 of the embodiment of the present invention, and will not be elaborated here in detail to avoid redundancy.

[0093] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or equipment (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or equipment and execute instructions), or used in combination with these instruction execution systems, devices or equipment.

[0094] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0095] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0096] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that at least one of the features is included in the embodiment. In the description of the present invention, the meaning of the word "multiple" is at least two or two and above, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments. Relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0097] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0098] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0099] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data receiving device for power line carrier communication, characterized in that: The device comprises: A front-end processing unit, configured to perform analog-to-digital conversion, scaling processing, and filtering processing on the received analog signal to obtain a first digital signal; A digital gain unit, the digital gain unit is connected to the front-end processing unit and is used to power amplify the first digital signal to obtain a second digital signal; A digital compensation unit, the digital compensation unit is connected to the digital gain unit, the digital compensation unit includes a first power error calculator, a first integral controller and a decision device, wherein the first power error calculator is used to obtain the difference between the first target power and the power of the second digital signal to obtain a first power difference value, the first integral controller is used to integrate the first power difference value to obtain a first integral gain value, and the decision device is used to determine the power amplification gain value of the digital gain unit according to the relationship between the first integral gain value and a preset threshold value; The decision device is specifically used to: adjust the first integral gain value and the multiple gain value according to the magnitude relationship between the first integral gain value and the preset threshold value, and determine the power amplification gain value of the digital gain unit according to the adjusted first integral gain value and the multiple gain value; The decision device is specifically used for: When the first integral gain value is greater than a first preset threshold value, reducing the first integral gain value by a first preset multiple, and increasing the multiple gain value by the first preset multiple; When the first integral gain value is less than a second preset threshold value, amplifying the first integral gain value by a second preset multiple, and reducing the multiple gain value by the second preset multiple; When the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, the first integral gain value and the multiple gain value are kept unchanged.

2. The data receiving device for power line carrier communication according to claim 1, characterized in that: The decision device is specifically used to obtain the power amplification gain value through the following formula: Gain=2^GainE*GainM Wherein, Gain is the power amplification gain value, GainE is the adjusted multiple gain value, and GainM is the adjusted first integral gain value.

3. The data receiving device for power line carrier communication according to claim 1, characterized in that: The first integral controller is specifically configured to: when the first power difference is greater than a first preset power limit, integrate the first power difference to obtain the first integral gain value.

4. The data receiving device for power line carrier communication according to claim 3, characterized in that: The first integral controller is further used to perform smoothing filtering on the first power difference.

5. The data receiving device for power line carrier communication according to any one of claims 1 to 4, characterized in that: The front-end processing unit comprises: A front-end processing subunit, the front-end processing subunit is used to perform analog-to-digital conversion and scaling processing on the analog signal to obtain a third digital signal; A digital filtering subunit, the digital filtering subunit is connected to the front-end processing subunit, and is used to filter the third digital signal to obtain the first digital signal.

6. The data receiving device for power line carrier communication according to claim 5, characterized in that: The front-end processing subunit includes an analog gain amplifier, an analog-to-digital converter and a digital gain amplifier connected in sequence, the analog gain amplifier is used to scale the analog signal, the analog-to-digital converter is used to perform analog-to-digital conversion on the scaled analog signal to obtain a fourth digital signal, and the digital gain amplifier is used to scale the fourth digital signal to obtain the third digital signal.

7. The data receiving device for power line carrier communication according to claim 6, characterized in that: The device further comprises: a gain controller connected to the front-end processing subunit and configured to determine scaling gain values ​​of the analog gain amplifier and the digital gain amplifier.

8. The data receiving device for power line carrier communication according to claim 7, characterized in that: The gain controller includes: a second power error calculator, a second integral controller and a gain decomposer, the second power error calculator is used to obtain the difference between the second target power and the power of the third digital signal to obtain a second power difference value, the second integral controller is used to integrate the second power difference value to obtain a second integral gain value, and the gain decomposer is used to decompose the second integral gain value to obtain the scaling gain values ​​of the analog gain amplifier and the digital gain amplifier.

9. The data receiving device for power line carrier communication according to claim 8, characterized in that: The second integral controller is specifically configured to integrate the second power difference to obtain the second integral gain value when the second power difference is greater than a second power limit.

10. The data receiving device for power line carrier communication according to claim 9, characterized in that: The second integral controller is further used to perform smoothing filtering on the second power difference.

11. The data receiving device for power line carrier communication according to claim 9, characterized in that: The gain decomposer is specifically used for: When the second integral gain value is greater than the effective gain range of the analog gain amplifier, setting the scaling gain value of the analog gain amplifier to the maximum gain value of the analog gain amplifier, and setting the scaling gain value of the digital gain amplifier to the gain difference between the second integral gain value and the maximum gain value; When the second integral gain value is less than or equal to the effective gain range of the analog gain amplifier, the scaling gain of the analog gain amplifier is set to the second integral gain value, and the scaling gain value of the digital gain amplifier is set to zero.

12. The data receiving device for power line carrier communication according to any one of claims 1 to 4, characterized in that: The device also includes: a synchronization unit, the synchronization unit being connected to the digital gain unit and configured to determine a frame boundary of the second digital signal; A demodulation and decoding unit, the demodulation and decoding unit is connected to the synchronization unit, and is used to demodulate and decode the second digital signal based on the frame boundary to obtain an original signal.

13. A chip, characterized in that: It comprises a data receiving device for power line carrier communication according to any one of claims 1-12.

14. A data receiving method for power line carrier communication, characterized in that: The method comprises: Performing analog-to-digital conversion, scaling processing, and filtering processing on the received analog signal to obtain a first digital signal, and performing power amplification on the first digital signal to obtain a second digital signal; Acquire a difference between a first target power and a power of the second digital signal to obtain a first power difference value, and integrate the first power difference value to obtain a first integral gain value; Determine a power amplification gain value according to a magnitude relationship between the first integral gain value and a preset threshold value; The determining of the power amplification gain value according to the magnitude relationship between the first integral gain value and the preset threshold value includes: Adjust the first integral gain value and the multiple gain value according to the magnitude relationship between the first integral gain value and the preset threshold value; Determine the power amplification gain value according to the adjusted first integral gain value and the multiple gain value; The adjusting the first integral gain value and the multiple gain value according to the magnitude relationship between the first integral gain value and the preset threshold value includes: When the first integral gain value is greater than a first preset threshold value, reducing the first integral gain value by a first preset multiple, and increasing the multiple gain value by a second preset multiple; When the first integral gain value is less than a second preset threshold value, amplifying the first integral gain value by a third preset multiple, and reducing the multiple gain value by a fourth preset multiple; When the first integral gain value is greater than or equal to the second preset threshold value and less than or equal to the first preset threshold value, the first integral gain value and the multiple gain value are kept unchanged.

15. The data receiving method for power line carrier communication according to claim 14, characterized in that: The power amplification gain value is obtained by the following formula: Gain=2^GainE*GainM Wherein, Gain is the power amplification gain value, GainE is the adjusted multiple gain value, and GainM is the adjusted first integral gain value.

16. A chip, characterized in that: include: A memory, a processor, and a data receiving program for power carrier communication stored in the memory and executable on the processor. When the processor executes the data receiving program for power carrier communication, the data receiving method for power carrier communication according to any one of claims 14-15 is implemented.

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