Reference Clock Complementary Metal Oxide Semiconductor (CMOS) Input Buffer

Abstract

The present application relates to a reference clock complementary metal oxide semiconductor (CMOS) input buffer with self-calibration and improved electrostatic discharge (ESD) performance. In one embodiment, the reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage-controlled switches, which are individually coupled to individual output switches [M2-i] of the plurality of output switches. By selectively switching at least one voltage-controlled switch of the plurality of voltage-controlled switches, the voltage of the falling edge signal or the rising edge signal of the Schmitt trigger can be adjusted.

Description

Technical Field

[0001] The present disclosure relates generally to the operation of image sensors, and in particular, to improved performance of reference clock input buffers. Background Art

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cell phones, surveillance cameras, as well as medical, automotive, and other applications. The technology used to manufacture image sensors continues to advance rapidly. For example, the demand for higher image sensor resolution and lower power consumption has led to further miniaturization and integration of image sensors into digital devices.

[0003] Image sensor pixels generate electrical signals based on timing acquisition provided by a reference clock signal. In some embodiments, the reference clock pulses are generated by an input buffer based on a complementary metal oxide semiconductor (CMOS) transistor circuit. However, when the electrical signal propagates from the image sensor pixel through a relatively long printed circuit board (PCB) trace or through a flexible cable with impedance mismatch, the electrical signal may produce ripples or slope changes. Signal ripples and slope changes make it difficult to select a suitable threshold value that defines the boundary between the clock high state and the clock low state. Therefore, there is a need for an improved system and method for threshold determination of a reference clock signal. Summary of the invention

[0004] Aspects of the present disclosure provide a reference clock input buffer for an image sensor, wherein the reference clock input buffer includes: a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge, wherein the falling edge and the rising edge are separated by a hysteresis voltage, and wherein the Schmitt trigger includes a plurality of output switches; and a plurality of voltage-controlled switches individually coupled to individual output switches of the plurality of output switches, wherein the voltage of the falling edge signal or the rising edge signal of the Schmitt trigger can be adjusted by selectively switching at least one voltage-controlled switch of the plurality of voltage-controlled switches.

[0005] Another aspect of the present disclosure provides a method of operating a reference clock input buffer of an image sensor, wherein the method includes: generating a clock signal having a falling edge and a rising edge through a Schmitt trigger, wherein the falling edge and the rising edge are separated by a hysteresis voltage, and wherein the Schmitt trigger includes a plurality of output switches; and adjusting a voltage of the falling edge signal or the rising edge signal of the Schmitt trigger by selectively switching at least one voltage-controlled switch among a plurality of voltage-controlled switches, wherein individual switches of the plurality of voltage-controlled switches are coupled to individual output switches of the plurality of output switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 is a diagram of an example image sensor in accordance with an embodiment of the present technology.

[0008] Figure 2 is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology.

[0009] Figure 3A and 3B yes Figure 2 Graph of the output of the reference clock input buffer illustrated in FIG.

[0010] Figure 4 is a sample graph of voltage ripple in accordance with an embodiment of the present technology.

[0011] Figure 5 is a graph of jitter noise according to an embodiment of the present technology.

[0012] Fig. 6A and 6B is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology.

[0013] Figure 7 is a graph of the statistical distribution of Vih of a reference clock input buffer according to an embodiment of the present technology.

[0014] Fig. 8A is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology.

[0015] Figure 8B is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology.

[0016] Fig. 9 is a graph showing the distribution of Vih of a reference clock input buffer according to an embodiment of the present technology.

[0017] Fig.10 is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology.

[0018] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for the purpose of simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. In addition, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate less obstructed viewing of these various embodiments of the present invention. DETAILED DESCRIPTION

[0019] An image sensor is disclosed, and in particular an image sensor including a reference clock CMOS input buffer with self-calibration and improved electrostatic discharge (ESD) performance. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0020] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in multiple places throughout this specification are not necessarily all referring to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0021] For ease of description, spatially relative terms (e.g., "below," "beneath," "under," "beneath," "above," "on," and the like) may be used to describe the relationship of one element or feature to another (or more) element or feature, as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figure is flipped, then the elements described as being "below" or "below" or "under" other elements or features will be oriented to be "above" the other elements or features. Thus, the exemplary terms "below" or "under" may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0022] It will be appreciated from the foregoing that, for the purpose of illustration, specific embodiments of the technology have been described herein, but various modifications may be made without departing from the present disclosure. In addition, although various advantages and features associated with certain embodiments are described above in the context of these embodiments, other embodiments may also exhibit such advantages and / or features, and not all embodiments need to exhibit such advantages and / or features to fall within the scope of the technology. In the case of describing a method, the method may include more, less, or other steps. In addition, the steps may be performed in any suitable order. Therefore, the present disclosure may cover other embodiments not explicitly shown or described herein. In the context of the present disclosure, "approximately" means + / -5% of the stated value.

[0023] Throughout this specification, several terms from the art are used. These terms will take their ordinary meanings in the art from which they come, unless specifically defined herein or the context of their use would clearly imply otherwise. It should be noted that element names and symbols (e.g., Si vs. silicon) are used interchangeably throughout this document; however, both have the same meaning.

[0024] In short, embodiments of the present technology are directed to controlling the rising and / or falling edges of a clock buffer to avoid voltage ripples in the signal generated by an optical sensor. In some embodiments, the clock buffer is based on a Schmitt trigger design. Typically, the rising edge is separated from the falling edge by a certain amount of hysteresis, so that the rising edge occurs at one voltage Vih and the falling edge occurs at another voltage Vil. When the rising and / or falling edges of the clock buffer coincide with voltage ripples in the signal, the input clock exhibits increased jitter, which in turn affects the image sensor link timing budget (also known as the "serdes" timing budget) of the entire serializer / deserializer path.

[0025] In some embodiments, the Schmitt trigger clock buffer may include multiple transistors of different sizes (e.g., different lengths L and / or widths W). In operation, one or more transistors may be selected (e.g., by another transistor connected in series) to operate or not operate within the Schmitt trigger. When the selectable transistors have different sizes, the output Vih (and / or Vil) varies with the size of the selected transistor. Thus, voltage ripple regions may be avoided by appropriately selecting transistors. As an additional advantage, the ESD protection of the circuit may be improved by adding transistors connected in series.

[0026] In some embodiments, the input voltage of the Schmitt trigger can be changed to control the statistical spread of the Vih and / or Vil values. For example, the input voltage values ​​of the Schmitt trigger can range from Vref_low as the lower boundary to Vref_high as the upper boundary. Once Vref_low and Vref_high are established on the "copy" Schmitt trigger (i.e., the test Schmitt trigger), the supply voltage Vin of the "master" Schmitt trigger (i.e., the operational Schmitt trigger) can also be maintained within these values. In some embodiments, the replica and master Schmitt triggers can be the same circuit, but are first used as replicas during calibration and then as masters in normal operation. In some embodiments, the input voltage change from Vref_low to Vref_high can be generated by a state machine and provided to the Schmitt trigger as Vin.

[0027] Figure 11 is a diagram of an example image sensor 10 according to an embodiment of the present technology. The image sensor 10 includes a pixel array 12, a control circuit system 16, a readout circuit system 14, and a functional logic 18. In one example, the pixel array 12 is a two-dimensional (2D) array of image sensor pixels 11 (e.g., pixels P1, P2 ..., Pn). Each of the image sensor pixels 11 includes a large photodiode (LPD) for low light detection and a small photodiode (SPD) for strong light detection. In different embodiments, two or more image sensor pixels 11 may be grouped into multiple pixel units. As illustrated, the image sensor pixels 11 are arranged into rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the image sensor pixels 11 acquire image data of a scene, which can then be used to present a 2D image of a person, place, object, etc. However, in other embodiments, the image sensor pixels 11 may be arranged in a configuration other than rows and columns.

[0028] In one embodiment, after each image sensor pixel 11 in pixel array 12 acquires its image charge, the image data is read out by readout circuitry 14 via bit lines 13 and then transferred to function logic 18. The readout image data of each image sensor pixel 11 together constitutes an image frame. In various embodiments, readout circuitry 14 may include a signal amplifier, analog-to-digital (ADC) conversion circuitry, and data transmission circuitry. Function logic 18 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise). In some embodiments, control circuitry 16 and function logic 18 may be combined into a single functional block to control the capture of images by image sensor pixels 11 and read out image data from readout circuitry 14. Function logic 18 may include a digital processor. In an embodiment, readout circuitry 14 may read a row of image data at a time along a readout column line (bit line 13), or may use various other techniques to read image data, such as serial readout of all pixels at the same time or fully parallel readout.

[0029] In one embodiment, the control circuit system 16 is coupled to the pixel array 12 to control the operation of multiple photodiodes in the pixel array 12. For example, the control circuit system 16 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal, which is used to simultaneously enable all pixels within the pixel array 12 during a single data acquisition window to simultaneously capture their corresponding image data. In another embodiment, the shutter signal is a rolling shutter signal so that during continuous acquisition windows, each row, each column, or each group of pixels is sequentially enabled. In another embodiment, image acquisition is synchronized with a lighting effect such as a flash. In a different embodiment, the control circuit system 16 may be configured to control each of the image sensor pixels 11 to perform acquisition operations of one or more dark current pixel frames and normal image frames for image calibration.

[0030] In one embodiment, readout circuitry 14 includes an analog-to-digital converter (ADC) that converts analog image data received from pixel array 12 into a digital representation. The digital representation of the image data may be provided to function logic 18.

[0031] In various embodiments, the image sensor 10 may be part of a digital camera, a cell phone, a laptop computer, or the like. In an embodiment, the image sensor 10 is incorporated as part of an automotive monitoring system or a vision system. In addition, the image sensor 10 may be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, a wireless transmitter, an HDMI port, etc.), a lighting / flash, an electrical input (keyboard, a touch display, a trackpad, a mouse, a microphone, etc.), and / or a display. The other hardware may pass instructions to the image sensor 10, extract image data from the image sensor 10, or manipulate the image data supplied by the image sensor 10.

[0032] Figure 2 is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology. The illustrated reference clock input buffer 20 is a Schmitt trigger. The output voltage Vout depends on the input voltage Vin, the power supply voltage VDD, and the characteristics of the transistors (switches) M1 to M6. In the context of this specification, transistors (switches) M2 and M5 are referred to as output transistors (switches). In operation, the Schmitt trigger 20 produces an output Vout characterized by hysteresis. Figure 3A Discuss examples of such hysteresis.

[0033] Figure 3Ais a graph of the output of the reference clock input buffer (Schmitt trigger). The horizontal axis of the graph shows the input voltage Vin, and the vertical axis shows the output voltage Vout. The operation of the Schmitt trigger 20 is characterized by hysteresis, which is shown as the difference between Vih (as the falling edge of Vout) and Vil (as the rising edge of Vout). In different embodiments, such hysteresis can reach 400mV to 500mV or other values. For example, in some embodiments, Vil is about 0.623V and Vih is about 1.136V. Figure 3B is a simulated plot of the output of a Schmitt trigger containing an additional inverter that Figure 3A The Vout described in is inverted.

[0034] Figure 4 is a sample graph of voltage ripple according to an embodiment of the present technology. The horizontal axis shows time in μs, and the vertical axis shows the voltage within a relatively long PCB trace or flexible cable, for example, that transmits the signal generated by the image sensor pixel. Two plateaus 30 and 31 indicate voltage ripple regions. In the illustrated case, these ripples extend over a time period of about 2ns at voltages of about 0.9V and 1.6V. In different embodiments, different values ​​are possible. For example, when the Vih of the reference clock input buffer 20 is consistent with the ripple of the illustrated signal, the resulting clock output carries a jitter penalty that may affect the noise and timing budget of the image sensor. Therefore, it is generally expected that the falling edge Vih and / or the rising edge Vil of the reference clock avoid the ripple region of the voltage signal. However, even when Vih and / or Vil are established to avoid ripples, in some embodiments, the location of the ripple region or the values ​​of Vih and Vil may vary with manufacturing variations, which brings additional problems when designing a reference clock input buffer (e.g., a Schmitt trigger). In some embodiments, such differences in Vih caused by manufacturing variations may be significant, corresponding to approximately 300 mV.

[0035] Figure 5is a graph of jitter noise according to an embodiment of the present technology. The horizontal axis shows the Vih voltage of the Schmitt trigger, and the vertical axis shows the jitter noise in the acquired voltage signal expressed as root mean square (RMS) noise. Results are shown for the following three target Vih values: 0.953V, 1.034V, and 1.135V. However, as explained above, the actual Vih value of a given Schmitt trigger may vary due to, for example, manufacturing variations or other variables. The horizontal dashed line indicates the desired limit of RMS noise of about 10ps. In the illustrated example, based on this desired (target) limit of RMS noise and a target change W of Vih of about 300mV, the target value of Vih is about 1.075V. The above numbers are provided as non-limiting illustrations, and different values ​​may be applicable in different embodiments.

[0036] Fig. 6A and 6B is a schematic diagram of a reference clock input buffer 100 (Schmitt trigger) according to an embodiment of the present technology. The illustrated Schmitt trigger 100 includes an additional transistor (switch) M7. In the context of this specification, switch M2 is referred to as an output switch and switch M7 is referred to as a voltage controlled switch. In some embodiments, switch M7 may be of a P-channel metal oxide semiconductor (PMOS) type. In the illustrated embodiment, switch M7 separates switch M2 from a power supply (voltage source) VDD. In some embodiments, the addition of switch M7 improves the ESD protection of the Schmitt trigger. Transistors (switches) M2 and M7 are collectively referred to as an output voltage control array M80. Reference is made below to Figure 6B Some embodiments of circuit M80 are described.

[0037] Figure 6B1 is a schematic diagram of a reference clock input buffer (Schmitt trigger) according to an embodiment of the present technology. In the illustrated figure, the Schmitt trigger 100 includes a plurality of output switches M2-i and a plurality of voltage-controlled switches M7-i. As shown, each N-channel metal oxide semiconductor (NMOS) transistor M2 (e.g., M2-1, M2-2, M2-3) is connected to VDD through one of the P-channel metal oxide semiconductor (PMOS) transistors M7 (e.g., M7-1, M7-2, M7-3). Therefore, the selected transistor M2-i can be activated and deactivated by its corresponding transistor M7-i. It can be shown that the value of Vih varies with different sizes of transistor M2-i (e.g., with different lengths L and / or widths W). In some embodiments, a smaller size of transistor M2-i results in a smaller Vih. As a non-limiting example, these different sized and selectively activated transistors M2-i can produce Vih of 1.135V, 1.034V, and 0.953V. In at least some embodiments, voltage ripple regions in the sensor signal can be avoided by selecting a suitable Vih through appropriate selection of transistors M2-i. As explained above, electrostatic discharge (ESD) protection of the circuit can also be improved by adding series-connected transistors M7-i. In some embodiments, Vil can be adjusted through integrated circuit (I2C) register control and resistor ladder.

[0038] Figure 7 is a graph of the statistical distribution of Vih for a reference clock input buffer according to an embodiment of the present technology. As explained above, manufacturing variations may cause changes in the Vih / Vil values. An example of such a change in Vih is illustrated as a Gaussian distribution in the graph. However, changing the Vin value of the Schmitt trigger will also change the Vout value, i.e., the Vih and Vil values ​​will also change with changes in Vin. Therefore, the value of, for example, Vih can be further adjusted by changing the Vin value between, for example, Vref_low and Vref_high.

[0039] Furthermore, changes in VDD track changes in Vin. For example, for a lower VDD, Vin is typically also lower, all else being equal.

[0040] In some embodiments, varying Vin between the Vref_low and Vref_high thresholds can keep the Vih spread within a specific target range. Figure 5 As discussed, in a particular embodiment, a nominal Vih of 1.075V is characterized by a possible variation of approximately 300mV, with the jitter RMS still remaining below 10ps. Figure 7, if the total Vih spread described is about 300mV, then the spread can be further reduced by selecting Vin in the range of Vref_low to Vref_high. For example, Vref_low and Vref_high can be set to 1 / 3 and 2 / 3 of the total spread of Vin to capture the situation that is statistically most likely to occur in the actual manufacturing process while reducing the variability of Vih. Fig. 8A and 8B A sample circuit is described which depends on the value of Vin for such an adjustment.

[0041] Fig. 8A is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology. In some embodiments, an input voltage range Vref_low to Vref_high can be tested on a replica circuit corresponding to a master circuit. For example, the replica circuit can be selected from a given manufacturing batch or within a given image sensor.

[0042] Possible separation of the test results for the replica circuit may be performed as follows. Vih values ​​below, for example, average Vih-100mV may be marked as the "11" case (i.e., below the lower target boundary of Vih and below the upper target boundary of Vih). Similarly, Vih values ​​above, for example, average Vih+100mV may be marked as the "00" case (i.e., above the lower target boundary of Vih and above the upper target boundary of Vih). Similarly, Vih values ​​within the target range may be marked as the "01" case (i.e., above the lower target boundary of Vih and below the upper target boundary of Vih). The "10" case (i.e., below the lower target boundary of Vih and simultaneously above the upper target boundary of Vih) is not possible. Once the range of Vref_low to Vref_high is selected and tested, these values ​​may be transferred to the Vin of the master (i.e., working, production) circuit. In some embodiments, after completing its calibration function, the replica circuit may be reused as a master circuit.

[0043] Figure 8B is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology. In the illustrated embodiment, separate Schmitt trigger circuits Replica 1 and Replica 2 are used to determine the limits of Vih based on the changes in Vref_high and Vref_low at the respective inputs of the Replica 1 and Replica 2 circuits. Once determined, the values ​​of Vref_high and Vref_low can be transmitted as the limits of the input voltage of the main Schmitt trigger. In some embodiments, the process of determining the values ​​of Vref_high and Vref_low described above can be referred to as a "calibration" or "trimming" process

[0044] Fig. 9is a graph of the distribution of Vih for a reference clock input buffer according to an embodiment of the present technology. The results were obtained through Spice simulation. The horizontal axis shows the test case number (e.g., cnr#), and the vertical axis shows the distribution of Vih. For the illustrated case, the Vih before calibration (i.e., before trimming) was in a band of about 300mV. After trimming Vin to the range of Vref_high and Vref_low, the distribution of Vih was reduced to a band of about 100mV. As explained above, a tighter distribution of Vih (or a tighter distribution of Vil) generally produces less signal jitter when all other parameters remain the same.

[0045] Fig.10 is a schematic diagram of a reference clock input buffer according to an embodiment of the present technology. The illustrated schematic diagram includes the replica circuit and the master circuit described above. The Vref_high and Vref_low voltages are provided to the master and replica Schmitt trigger circuits through a state machine. In addition, in order to reduce the local mismatch between the replica and the master, a closed loop is established between the replica and the master through a latch (e.g., a flip-flop circuit) 90. During the calibration phase, the latch 90 implements the control bits ("00", "01", "11") that reuse the same Schmitt trigger to generate the normal clock output phase.

[0046] In some embodiments, the Vout signals from the master and replica Schmitt trigger circuits can be used for different parts of the image sensor. For example, the output of the master circuit can be used for the phase-locked loop (PLL) output, while the output of the replica Schmitt trigger can be used for the I2C protocol and system control PLL. However, in practical applications, such an approach requires more complex digital control circuits.

[0047] Many embodiments of the techniques described above may take the form of computer or controller executable instructions, including routines executed by a programmable computer or controller. Those skilled in the relevant art will appreciate that the techniques may be practiced on computer / controller systems other than those shown and described above. The techniques may be embodied in a special-purpose computer, an application-specific integrated circuit (ASIC), a controller, or a data processor that is specially programmed, configured, or constructed to execute one or more of the computer-executable instructions described above. Of course, any logic or algorithm described herein may be implemented in software or hardware, or in a combination of software and hardware.

[0048] The above description of the illustrated examples of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the present invention are described herein for illustrative purposes, various modifications may be made within the scope of the present invention as will be appreciated by those skilled in the relevant art.

[0049] These modifications may be made to the present invention in light of the above detailed description. The terms used in the appended claims should not be interpreted as limiting the present invention to the specific examples disclosed in this specification. Rather, the scope of the present invention will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. A reference clock input buffer for an image sensor, comprising: A Schmitt trigger (100) configured to generate a clock signal having a falling edge and a rising edge, wherein the falling edge and the rising edge are separated by a hysteresis voltage, and wherein the Schmitt trigger comprises a plurality of output switches (M2-i); and a plurality of voltage-controlled switches (M7-i) individually coupled to individual output switches (M2-i) of the plurality of output switches, The voltage Vih, Vil of the falling edge signal or the rising edge signal of the Schmitt trigger can be adjusted by selectively switching at least one voltage-controlled switch (M7-i) among the plurality of voltage-controlled switches.

2. The reference clock input buffer of claim 1, wherein the output switches (M2-i) are NMOS switches.

3. The reference clock input buffer of claim 2, wherein the voltage controlled switches (M7-i) are PMOS switches.

4. The reference clock input buffer of claim 3, wherein the voltage-controlled switches (M7-i) are connected to a supply voltage. 5 . The reference clock input buffer of claim 1 , wherein the plurality of voltage-controlled switches include three voltage-controlled switches individually connected to three output switches among the plurality of output switches. 6 . The reference clock input buffer of claim 5 , wherein individual output switches of the plurality of output switches have three different sizes. 7 . The reference clock input buffer of claim 6 , wherein the voltage Vih of the rising edge signal of the Schmitt trigger is reduced by selectively switching a minimum output switch among the plurality of output switches to an ON state. 8 . The reference clock input buffer of claim 6 , wherein the voltage Vih of the rising edge signal of the Schmitt trigger is increased by selectively switching a maximum output switch among the plurality of output switches to an ON state.

9. The reference clock input buffer of claim 1 , wherein the Schmitt trigger is a master Schmitt trigger, the reference clock input buffer further comprising a replica Schmitt trigger configured to generate a range of input voltage values ​​[Vref_low, Vref_high] during a calibration phase, wherein the range of input voltage values ​​is configured as an input to the master Schmitt trigger during an operation phase.

10. The reference clock input buffer of claim 9, wherein the replica Schmitt trigger and the master Schmitt trigger are the same Schmitt trigger, which operates as the replica Schmitt trigger in one time period and operates as the master Schmitt trigger in another time period.

11. The reference clock input buffer of claim 9, further comprising: a state machine configured to generate the range of input voltage values; and A latch configured to generate a control bit for an output voltage control array.

12. A method of operating a reference clock input buffer of an image sensor, comprising: generating a clock signal having a falling edge and a rising edge by a Schmitt trigger (100), wherein the falling edge and the rising edge are separated by a hysteresis voltage, and wherein the Schmitt trigger comprises a plurality of output switches (M2-i); and By selectively switching at least one voltage-controlled switch (M7-i) among a plurality of voltage-controlled switches, the voltage Vih, Vil of the falling edge signal or the rising edge signal of the Schmitt trigger is adjusted, Wherein individual switches of the plurality of voltage-controlled switches (M7-i) are coupled to individual output switches (M2-i) of the plurality of output switches.

13. The method of claim 12, wherein the output switches (M2-i) are NMOS switches and the voltage-controlled switches (M7-i) are PMOS switches.

14. The method of claim 12, wherein the plurality of voltage-controlled switches comprises three voltage-controlled switches individually connected to three output switches of the plurality of output switches.

15. The method of claim 14, wherein individual output switches of the plurality of output switches have three different sizes.

16. The method according to claim 15, further comprising: The voltage Vih of the rising edge signal of the Schmitt trigger is reduced by selectively switching a minimum output switch among the plurality of output switches to an ON state.

17. The method according to claim 15, further comprising: The voltage Vih of the rising edge signal of the Schmitt trigger is increased by selectively switching a maximum output switch among the plurality of output switches to an ON state.

18. The method of claim 12, wherein the Schmitt trigger is a master Schmitt trigger, the method further comprising: During the calibration phase, a range of input voltage values ​​[Vref_low, Vref_high] is generated by a replica Schmitt trigger of the reference clock input buffer; and During an operation phase, the main Schmitt trigger is operated using the range of input voltage values ​​as input to the main Schmitt trigger.

19. The method of claim 18, wherein the replica Schmitt trigger and the master Schmitt trigger are the same Schmitt trigger configured to operate as the replica Schmitt trigger during the calibration phase and configured to operate as the master Schmitt trigger during the operation phase.

20. The method of claim 18, further comprising: Generate the range of input voltage values ​​by a state machine; and Control bits for the output voltage control array are generated by latches configured to receive inputs from the replica Schmitt trigger and provide outputs to the master Schmitt trigger.

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