Display Substrate, Preparation Method Thereof, and Display Device

Abstract

A display substrate (10), a method for manufacturing the same, and a display device. The display substrate (10) includes a display area (100) and a non-display area surrounding the display area (100). The display area (100) includes a first display area (100a), a second display area (100b), and a fan-out routing area (100c). The second display area (100b) is located between the first display area (100a) and the fan-out routing area (100c). The first display area (100a) includes a plurality of first sub-pixels (P11). The first sub-pixel (P11) includes a first pixel circuit (P11a) and a first light-emitting element (P11b). The second display area (100b) includes a plurality of second sub-pixels (P12). The second sub-pixel (P12) includes a second pixel circuit (P12a) and a second light-emitting element (P12b). The fan-out routing area (100c) includes a plurality of data fan-out lines (700) and a plurality of third sub-pixels (P13). The third sub-pixel (P13) includes a third light-emitting element (P13b). At least one second pixel circuit (P12b) is electrically connected to at least two light-emitting elements. The at least two light-emitting elements are selected from at least one of the second light-emitting element (P12b) and the third light-emitting element (P13b). The plurality of data fan-out lines (700) are electrically connected to a plurality of data lines (DA).

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. With the continuous development of display technologies, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area surrounding the display area. The display area includes a first display area, a second display area, and a fan-out routing area, and the second display area is located between the first display area and the fan-out routing area;

[0005] A plurality of data lines, located in the display area;

[0006] The first display area includes a plurality of first sub-pixels, and each first sub-pixel includes a first pixel circuit and a first light-emitting element, and the orthographic projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap;

[0007] The second display area includes a plurality of second sub-pixels, and each second sub-pixel includes a second pixel circuit and a second light-emitting element, and the orthographic projections of the second pixel circuit and the second light-emitting element on the display substrate at least partially overlap;

[0008] The first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines;

[0009] The fan-out routing area includes a plurality of data fan-out lines and a plurality of third sub-pixels. The third sub-pixels include third light-emitting elements. At least one of the second pixel circuits is electrically connected to at least two light-emitting elements, and the at least two light-emitting elements are selected from at least one of the second light-emitting elements and the third light-emitting elements. The plurality of data fan-out lines are electrically connected to the plurality of data lines.

[0010] In an exemplary embodiment, the orthographic projection of the second pixel circuit on the display substrate plane and the orthographic projection of the third light-emitting element on the display substrate plane do not overlap.

[0011] In an exemplary embodiment, the data fan-out lines are stepped traces, and the orthographic projection of the data fan-out lines on the display substrate plane does not overlap with the orthographic projections of the first pixel circuit and the second pixel circuit on the display substrate plane.

[0012] In an exemplary embodiment, the display area includes a first connection line and a second connection line. The first connection line is configured to connect at least one of the following: the anode of the first light-emitting element of the first pixel circuit, the anode of the second light-emitting element of the second pixel circuit, the anode of the third light-emitting element of the second pixel circuit; the second connection line is configured to connect the anodes of the at least two light-emitting elements.

[0013] In an exemplary embodiment, the materials of the first connection line and the second connection line are transparent conductive materials.

[0014] In an exemplary embodiment, the fan-out routing area includes first-color light-emitting elements, second-color light-emitting elements, and third-color light-emitting elements, and the second connection line is configured to connect the anodes of at least two of the third-color light-emitting elements.

[0015] In an exemplary embodiment, the third-color light-emitting element is a green light-emitting element.

[0016] In an exemplary embodiment, the third sub-pixel further includes a third pixel circuit. The orthographic projection of the third pixel circuit on the display substrate at least partially overlaps with the orthographic projection of the first-color light-emitting element or the second-color light-emitting element on the display substrate, and does not overlap with the orthographic projection of the third-color light-emitting element on the display substrate.

[0017] In an exemplary embodiment, the second connection line is further configured to connect at least one of the following: the anodes of at least two of the first-color light-emitting elements, the anodes of at least two of the second-color light-emitting elements.

[0018] In an exemplary embodiment, the data fan-out line includes at least one lateral connection portion and at least one longitudinal connection portion. A positive projection of the lateral connection portion on the display substrate plane does not overlap with a positive projection of the third light-emitting element on the display substrate plane, and a positive projection of the longitudinal connection portion on the display substrate plane and a positive projection of the third light-emitting element on the display substrate plane have at least an overlapping area.

[0019] In an exemplary embodiment, the at least one second pixel circuit is electrically connected to at least two light-emitting elements and includes any one or more of the following:

[0020] Two of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0021] Three of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The three light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0022] Four of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The four light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0023] Five of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The five light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element.

[0024] In an exemplary embodiment, the display substrate includes a semiconductor layer, a first gate electrode layer, a second gate electrode layer, a first source-drain electrode layer, a second source-drain electrode layer, and an anode stacked on a substrate, where:

[0025] The semiconductor layer includes active layers of multiple transistors. The first gate electrode layer includes gate electrodes of multiple transistors and multiple first capacitor electrodes. The second gate electrode layer includes multiple second capacitor electrodes. The first source-drain electrode layer includes multiple data lines, source electrodes and drain electrodes of multiple transistors. The second source-drain electrode layer includes connection electrodes;

[0026] The multiple data fan-out lines are disposed in the same layer as one or more of the first gate electrode layer, the second gate electrode layer, and the second source-drain electrode layer.

[0027] In an exemplary embodiment, the display substrate includes a light-shielding layer, a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second semiconductor layer, a third gate electrode layer, a source-drain electrode layer, and an anode stacked on a substrate, where:

[0028] The first semiconductor layer includes an active layer of at least one polysilicon transistor, the first gate electrode layer includes gate electrodes of at least one polysilicon transistor and a plurality of first capacitor electrodes, the second gate electrode layer includes a plurality of second capacitor electrodes, the second semiconductor layer includes an active layer of at least one oxide transistor, the third gate electrode layer includes a gate electrode of at least one oxide transistor, and the source-drain electrode layer includes a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors;

[0029] The plurality of data fan-out lines are disposed in the same layer as one or more of the light-shielding layer, the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer.

[0030] In an exemplary embodiment, the display substrate further includes an electrode connection layer disposed between the source-drain electrode layer and the anode, and the material of the electrode connection layer is indium tin oxide or indium zinc oxide.

[0031] In an exemplary embodiment, at least one of the third sub-pixels includes any one or more of the following virtual electrode lines: a virtual active layer, a virtual gate electrode, a virtual capacitor electrode, and a virtual source-drain electrode, and the virtual electrode lines are connected to a fixed-potential signal line through signal traces.

[0032] In an exemplary embodiment, at least one of the third sub-pixels includes a virtual data fan-out line, and the virtual data fan-out line is connected to a fixed-potential signal line through signal traces.

[0033] An embodiment of the present disclosure also provides a display device including the display substrate as described in any one of the above.

[0034] An embodiment of the present disclosure also provides a method for manufacturing a display substrate. The display substrate includes a display area and a non-display area surrounding the display area. The display area includes a first display area, a second display area, and a fan-out wiring area, and the second display area is located between the first display area and the fan-out wiring area. The manufacturing method includes:

[0035] A plurality of first sub-pixels are formed in the first display area. The first sub-pixels include a first pixel circuit and a first light-emitting element, and the orthographic projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap. A plurality of second sub-pixels are formed in the second display area. The second sub-pixels include a second pixel circuit and a second light-emitting element, and the orthographic projections of the second pixel circuit and the second light-emitting element on the display substrate at least partially overlap. The first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines. A plurality of third sub-pixels and a plurality of data fan-out lines are formed in the fan-out wiring area. The third sub-pixels include a third light-emitting element. At least one of the second pixel circuits is electrically connected to at least two light-emitting elements, and the at least two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element. The plurality of data fan-out lines are electrically connected to the plurality of data lines.

[0036] Other aspects will be apparent after reading the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale, and the purpose is only to schematically illustrate the content of the present disclosure.

[0038] Figure 1 It is a schematic structural diagram of a display device;

[0039] Figure 2 It is a schematic plan view of a display substrate;

[0040] Figure 3 It is a schematic plan view of a display area in a display substrate;

[0041] Figure 4 It is a schematic cross-sectional view of a display area in a display substrate;

[0042] Figure 5 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0043] Figure 6 It is a timing diagram of the operation of a pixel driving circuit;

[0044] Figure 7 It is a schematic plan view of a bonding area in a display substrate;

[0045] Figure 8 It is a schematic diagram of a data fan-out line in a bonding area;

[0046] Figure 9Schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 10 is Figure 9 side view of the display substrate in;

[0048] Figure 11 is Figure 9 schematic enlarged structure view of area A in;

[0049] Figure 12 is Figure 9 schematic layout structure view of the fan-out routing area in;

[0050] Figure 13 is Figure 9 another schematic enlarged structure view of area A in;

[0051] Figure 14 is Figure 12 schematic cross-sectional structure view in the direction of B-B' in;

[0052] Figure 15 is Figure 12 another schematic cross-sectional structure view in the direction of B-B' in;

[0053] Figure 16 is Figure 12 schematic cross-sectional structure view in the direction of C-C' in. Detailed implementation manners

[0054] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other. To keep the following description of the embodiments of the present disclosure clear and concise, some details of known functions and known components are omitted in the present disclosure. The accompanying drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design

[0055] In the drawings, sometimes for clarity, the sizes, thicknesses of layers or regions of the respective components are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to that size, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0056] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0057] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the circumstances.

[0058] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0059] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0060] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other.

[0061] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0062] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0063] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0064] "About" in the present disclosure means not strictly limiting the boundary and allowing values within the process and measurement errors.

[0065] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may generate data voltages to be provided to the data lines D1, D2, D3, ……, and Dn by using the gray value and the control signal received from the timing controller. For example, the data signal driver may sample the gray value using a clock signal and apply the data voltages corresponding to the gray value to the data lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ……, and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light emission signal driver may generate emission signals to be provided to the light emission signal lines E1, E2, E3, ……, and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driver may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission signal driver may be configured in the form of a shift register and may generate light emission signals in such a way that the light emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, and each sub-pixel Pxij may be connected to a corresponding data line, a corresponding scan signal line, and a corresponding light emission signal line, where i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and the j-th data line.

[0066] Figure 2 It is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on the other sides of the display area 100. The display area 100 may include a plurality of sub-pixels configured to display dynamic pictures or still images. The bonding area 200 may include data fan-out lines that connect a plurality of data lines to an integrated circuit. The border area 300 may include power supply lines that transmit voltage signals. The bonding area 200 and the border area 300 may include dam structures in a ring shape. At least one side of the border area 300 may be a curled area formed by bending. Alternatively, both the display area 100 and the border area 300 may be bent or curved areas. The present disclosure does not limit this here.

[0067] In an exemplary embodiment, the display area may include a plurality of pixel units arranged in a matrix. Figure 3 It is a schematic plan view of a display area in a display substrate. As Figure 3 shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first color sub-pixel P1 that emits first color light, a second color sub-pixel P2 that emits second color light, and a third color sub-pixel P3 that emits third color light. The first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3 are respectively connected to a scan signal line, a data line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3 are respectively connected to the pixel driving circuits of their respective sub-pixels. The light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0068] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The present disclosure does not limit this here. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhombic, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid arrangement. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square arrangement. The present disclosure does not limit this here.

[0069] Figure 4It is a schematic cross-sectional structure diagram of a display area in a display substrate, showing the structures of three sub-pixels of an OLED display substrate. As Figure 4 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.

[0070] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and a storage capacitor that constitute a pixel driving circuit, Figure 4 and only one transistor 102A and one storage capacitor 102B are taken as examples herein. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The packaging layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403. The first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials, and the second packaging layer 402 may be made of organic materials. The second packaging layer 402 is disposed between the first packaging layer 401 and the third packaging layer 403, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0071] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0072] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 It is a schematic equivalent circuit diagram of a pixel driving circuit. As Figure 5 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and seven signal lines (a data line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0073] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to a second node N2, that is, the second end of the storage capacitor C is connected to a control electrode of the third transistor T3.

[0074] The control electrode of the first transistor T1 is connected to the second scan signal line S2, a first pole of the first transistor T1 is connected to the initial signal line INIT, and a second pole of the first transistor is connected to the second node N2. When a conductive level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

[0075] The control electrode of the second transistor T2 is connected to the first scan signal line S1. The first electrode of the second transistor T2 is connected to the second node N2. The second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0076] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1. The second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0077] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1. The first electrode of the fourth transistor T4 is connected to the data line D. The second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data line D into the pixel driving circuit.

[0078] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E. The first electrode of the fifth transistor T5 is connected to the first power supply line VDD. The second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E. The first electrode of the sixth transistor T6 is connected to the third node N3. The second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0079] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1. The first electrode of the seventh transistor T7 is connected to the initial signal line INIT. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize the amount of charge accumulated in the first electrode of the light-emitting device or release the amount of charge accumulated in the first electrode of the light-emitting device.

[0080] In an exemplary embodiment, the second pole of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0081] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0082] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light-emitting signal line E, and the initial signal line INIT extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data line D extend in the vertical direction.

[0083] In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode).

[0084] Figure 6 is a timing diagram of the operation of a pixel driving circuit. The following is through Figure 5 the operation process of the exemplary pixel driving circuit to illustrate the exemplary embodiments of the present disclosure. Figure 5 The pixel driving circuit in includes seven transistors (the first transistor T1 to the sixth transistor T7), one storage capacitor C, and seven signal lines (data line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS). All seven transistors are P-type transistors.

[0085] In an exemplary embodiment, the operation process of the pixel driving circuit can include:

[0086] The first stage A1, called the reset stage, has the signal of the second scan signal line S2 as a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E as high-level signals. The signal of the second scan signal line S2 being a low-level signal turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scan signal line S1 and the light-emitting signal line E being high-level signals turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light in this stage.

[0087] The second stage A2, called the data writing stage or the threshold compensation stage, has the signal of the first scan signal line S1 as a low-level signal, and the signals of the second scan signal line S2 and the light-emitting signal line E as high-level signals, and the data line D outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal line S1 being a low-level signal turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data line D to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data line D and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first electrode of the OLED to initialize (reset) the first electrode of the OLED, clear the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scan signal line S2 being a high-level signal turns off the first transistor T1. The signal of the light-emitting signal line E being a high-level signal turns off the fifth transistor T5 and the sixth transistor T6.

[0088] The third stage A3, called the light-emitting stage, has the signal of the light-emitting signal line E as a low-level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 as high-level signals. The signal of the light-emitting signal line E being a low-level signal turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the OLED to emit light.

[0089] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is as follows:

[0090] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * [(Vdd - Vd] 2

[0091] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0092] Figure 7 It is a schematic plan view of the bonding area in a display substrate. Figure 8 It is a schematic diagram of the data fan-out line in a bonding area. As Figure 7 shown, in the plane parallel to the display substrate, the bonding area 200 is located on one side of the display area 100. The bonding area 200 may include a first fan-out area 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driving chip area 205, and a bonding pin area 206 arranged in sequence along the direction away from the display area 100. The first fan-out area 201 includes at least data fan-out lines, and multiple data fan-out lines are configured to connect the data lines of the display area in a fan-out (Fanout) routing manner, as Figure 8 shown. The bending area 202 includes a composite insulating layer provided with a groove, and is configured to bend the bonding area 200 to the back of the display area 100. The second fan-out area 203 includes multiple data fan-out lines led out in a fan-out routing manner. The anti-static area 204 includes an anti-static circuit, and is configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driving chip area 205 includes an integrated circuit (Integrated Circuit, abbreviated as IC), and is configured to be connected to multiple data fan-out lines. The bonding pin area 206 includes a bonding pad (Bonding Pad), and is configured to be bonded and connected to an external flexible printed circuit (Flexible Printed Circuit, abbreviated as FPC).

[0093] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products. Ultra-narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of bezels or even borderless designs have received increasing attention in the design of OLED display products. Currently, the left bezel, right bezel, and upper bezel of a display device can be controlled within 1.0 mm, but the narrowing design of the lower bezel (the bezel on the side of the bonding area) is more difficult and has been maintained at about 2.0 mm. This is because the data fan-out lines are usually set in the fan-out area of the bonding area, and the fan-out area occupies a large amount of space. Generally, the width of the bonding area is smaller than the width of the display area. The signal lines of the integrated circuit and bonding pads in the bonding area need to be introduced into the wider display area in a fan-out manner through the fan-out area. The greater the width difference between the display area and the bonding area, the more diagonal fan-out lines there are in the fan-out area, and the greater the distance between the driver chip area and the display area, resulting in a wider lower bezel, causing the lower bezel to be much larger than the left and right bezels.

[0094] Figure 9 Schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure, Figure 10 is Figure 9 a side view of the display substrate in. As Figure 9 and Figure 10 shown, the display substrate 10 may include a display area 100, a bonding area 500 located on the opposite side of the first direction D1 of the display area 100, and a bezel area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a planarized area, including a plurality of sub-pixels Pxij that make up a pixel array to display dynamic pictures or still images. The display substrate may employ a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0095] In an exemplary embodiment, the bonding area 500 may include a lead area 501, a bending area 502, and a composite circuit area 503 arranged in sequence along the opposite direction of the first direction D1 (away from the display area). The lead area 501 is connected to the display area 100, the bending area 502 is connected to the lead area 501, and the composite circuit area 503 is connected to the bending area 502.

[0096] In an exemplary embodiment, the lead area 501 may be provided with a plurality of lead-out lines. One ends of the plurality of lead-out lines are correspondingly connected to a plurality of data lines in the display area 100, and the other ends are connected to the integrated circuit in the composite circuit area 503, so that the integrated circuit applies data signals to the data lines through the lead-out lines.

[0097] In an exemplary embodiment, the bending region 502 can be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 can be inverted, that is, the surface of the composite circuit region 503 facing upward can be converted to face downward through the bending of the bending region 502, and the third direction D3 intersects with the first direction D1. In an exemplary embodiment, when the bending region 502 is bent, the composite circuit region 503 can overlap with the display region 100 in the third direction D3 (thickness direction).

[0098] In an exemplary embodiment, the composite circuit region 503 can include an anti-static region, a driver chip region, and a bonding pin region. The integrated circuit (IC) 20 can be bonded and connected to the driver chip region, and the flexible printed circuit (FPC) 30 can be bonded and connected to the bonding pin region. In an exemplary embodiment, the integrated circuit 20 can generate driving signals required for driving the sub-pixels and can provide the driving signals to the sub-pixels in the display region 100. For example, the driving signals can be data signals for driving the light-emitting brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit 20 can be bonded and connected to the driver chip region through an anisotropic conductive film or other means, and the width of the integrated circuit 20 in the second direction D2 can be smaller than the width of the composite circuit region 503 in the second direction D2, and the second direction D2 intersects with the first direction D1. In an exemplary embodiment, the bonding pin region can be provided with pads including a plurality of pins (PINs), and the flexible circuit board 30 can be bonded and connected to the pads.

[0099] In an exemplary embodiment, the first direction D1 can be the extending direction (column direction) of the data lines in the display region, the second direction D2 can be the extending direction (row direction) of the scan signal lines in the display region, the third direction D3 can be the direction perpendicular to the plane of the display substrate, the first direction D1 and the second direction D2 can be perpendicular to each other, and the first direction D1 and the third direction D3 can be perpendicular to each other.

[0100] In an exemplary embodiment, as Figure 9 shown, the display region 100 includes a substrate and a first display region 100a, a second display region 100b, and a fan-out routing region 100c provided on the substrate, and the second display region 100b is located between the first display region 100a and the fan-out routing region 100c. Figure 11 For Figure 9 a schematic enlarged structure diagram of region A in Figure 12 For Figure 9 a schematic fan-out routing arrangement structure diagram of the fan-out routing region 100c in Figure 11 and Figure 12As shown, the display area 100 may include a plurality of sub-pixels, a plurality of data lines DA, and a plurality of data fan-out lines 700. The positive projections of the plurality of data lines DA and the plurality of data fan-out lines 700 on the display substrate plane at least partially overlap; the lead area 501 of the bonding area may include a plurality of lead-out lines 600. In an exemplary embodiment, the plurality of sub-pixels in the display area 100 are arranged in a matrix to form a plurality of pixel rows and a plurality of pixel columns. The plurality of data lines DA in the display area 100 extend along the first direction D1 or the opposite direction of the first direction D1, and are sequentially arranged at a set interval along the second direction D2. Each data line DA is connected to all the sub-pixels of a pixel column in the display area 100. The plurality of lead-out lines 600 of the lead area 501 are sequentially arranged at a set interval along the second direction D2. The first ends of the plurality of lead-out lines 600 are located at the edge B of the display area, and the second ends of the plurality of lead-out lines 600 extend in a direction away from the display area to the bending area. The first ends of the plurality of data fan-out lines 700 in the display area 100 are located at the edge B of the display area and are correspondingly connected to the first ends of a part of the lead-out lines 600 of the lead area 501. The second ends of the plurality of data fan-out lines 700 extend in a direction away from the lead area and are correspondingly connected to a part of the data lines DA in the display area 100. A part of the lead-out lines 600 in the lead area 501 are connected to the data fan-out lines 700, and the other part of the lead-out lines 600 are correspondingly connected to the other part of the data lines DA extending to the lead area 501. In an exemplary embodiment, the display area edge B may be the edge of the display area 100 close to the lead area 501 side.

[0101] In an exemplary embodiment, the first display area 100a may include a plurality of first sub-pixels P11. The first sub-pixels P11 may include a first pixel circuit P11a and a first light-emitting element P11b. The positive projections of the first pixel circuit P11a and the first light-emitting element P11b on the display substrate at least partially overlap; the second display area 100b may include a plurality of second sub-pixels P12. The second sub-pixels P12 may include a second pixel circuit P12a and a second light-emitting element P12b. The positive projections of the second pixel circuit P12a and the second light-emitting element P12b on the display substrate at least partially overlap. The first pixel circuit P11a and the second pixel circuit P12a are electrically connected to the plurality of data lines DA; the fan-out line area 100c may include a plurality of data fan-out lines 700 and a plurality of third sub-pixels P13. The third sub-pixels P13 include a third light-emitting element P13b; at least one second pixel circuit P12a is electrically connected to at least two light-emitting elements, and the at least two light-emitting elements are selected from at least one of the second light-emitting element P12b and the third light-emitting element P13b. The plurality of data fan-out lines 700 are electrically connected to the plurality of data lines DA.

[0102] In an exemplary embodiment, at least one second pixel circuit P12a is electrically connected to at least two light-emitting elements, including any one or more of the following:

[0103] At least one second pixel circuit P12a is electrically connected to at least two second light-emitting elements P12b;

[0104] At least one second pixel circuit P12a is electrically connected to at least two third light-emitting elements P13b;

[0105] At least one second pixel circuit P12a is electrically connected to at least one second light-emitting element P12b and at least one third light-emitting element P13b.

[0106] In an exemplary embodiment, the data line DA and the data fan-out line 700 may be disposed in different film layers, and an insulating layer is provided between the data line DA and the data fan-out line 700.

[0107] In an exemplary embodiment, the lead-out line 600 and the data fan-out line 700 may be disposed in the same film layer and formed simultaneously through the same patterning process. The lead-out line 600 and the data fan-out line 700 may be an integrally connected structure.

[0108] In an exemplary embodiment, the lead-out line 600 and the data fan-out line 700 may be disposed in different film layers, an insulating layer is provided therebetween, and they are connected through vias.

[0109] In an exemplary embodiment, multiple lead-out lines 600 may be arranged to be parallel to the first direction D1, that is, the lead-out line 600 is parallel to the data line DA.

[0110] In an exemplary embodiment, the orthographic projection of any one lead-out line 600 on the substrate does not overlap with the orthographic projection of other lead-out lines 600 on the substrate, and the orthographic projection of any one data fan-out line 700 on the substrate does not overlap with the orthographic projection of other data fan-out lines 700 on the substrate.

[0111] In an exemplary embodiment, the orthographic projection of the second pixel circuit P12a on the display substrate plane does not overlap with the orthographic projection of the third light-emitting element P13b on the display substrate plane. That is, the third sub-pixel P13 has no pixel circuit but only a light-emitting element, and the third sub-pixel P13 is driven by the second pixel circuit P12a.

[0112] In an exemplary embodiment, the data fan-out line 700 has a stepped trace, and the orthographic projection of the data fan-out line 700 on the display substrate plane does not overlap with the orthographic projections of the first pixel circuit P11a and the second pixel circuit P12a on the display substrate plane.

[0113] In an exemplary embodiment, the display area 100 includes a first connection line 31 and a second connection line 32. The first connection line 31 is configured to connect at least one of the following: the anode of the first light-emitting element P11b to the first pixel circuit P11a, the anode of the second light-emitting element P12b to the second pixel circuit P12a, and the anode of the third light-emitting element P13b to the second pixel circuit P12a. The second connection line 32 is configured to connect the anodes of at least two light-emitting elements, where the at least two light-emitting elements are selected from at least one of the second light-emitting element P12b and the third light-emitting element P13b.

[0114] In an exemplary embodiment, the materials of the first connection line 31 and the second connection line 32 are transparent conductive materials.

[0115] In an exemplary embodiment, as Figure 12 shown, the data fan-out line 700 includes at least one lateral connection portion 700a extending along the second direction D2 and at least one longitudinal connection portion 700b extending along the first direction D1. The second direction D2 intersects the first direction D1, the first direction D1 is parallel to the data line DA, the orthographic projection of the lateral connection portion 700a on the display substrate plane does not overlap with the orthographic projection of the third light-emitting element P13b on the display substrate plane, and the orthographic projection of the longitudinal connection portion 700b on the display substrate plane and the orthographic projection of the third light-emitting element P13b on the display substrate plane have at least an overlapping area.

[0116] In an exemplary embodiment, the fan-out wiring area includes a first-color light-emitting element, a second-color light-emitting element, and a third-color light-emitting element. The second connection line 32 is configured to connect the anodes of at least two third-color light-emitting elements.

[0117] In an exemplary embodiment, the third-color light-emitting element can be a green light-emitting element or a light-emitting element of other colors.

[0118] In an exemplary embodiment, the third sub-pixel further includes a third pixel circuit. The orthographic projection of the third pixel circuit on the display substrate at least partially overlaps with the orthographic projection of the first-color light-emitting element or the second-color light-emitting element on the display substrate, and does not overlap with the orthographic projection of the third-color light-emitting element on the display substrate.

[0119] In an exemplary embodiment, the second connection line 32 is further configured to connect at least one of the following: the anodes of at least two first-color light-emitting elements, the anodes of at least two second-color light-emitting elements.

[0120] In an exemplary embodiment, the first-color light-emitting element can be a red light-emitting element, the second-color light-emitting element can be a blue light-emitting element, or alternatively, the first-color light-emitting element can be a blue light-emitting element, and the second-color light-emitting element can be a red light-emitting element.

[0121] Figure 13 Another enlarged structural schematic diagram of region A in Figure 9 In an exemplary embodiment, as Figure 13 shown, at least one second pixel circuit P12a is electrically connected to at least two light-emitting elements, including any one or more of the following:

[0122] Two light-emitting elements are connected in series and then connected to a second pixel circuit P12a, and the two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0123] Three of the light-emitting elements are connected in series and then connected to a second pixel circuit P12a, and the three light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0124] Four light-emitting elements are connected in series and then connected to a second pixel circuit P12a, and the four light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element;

[0125] Five light-emitting elements are connected in series and then connected to a second pixel circuit P12a, and the five light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element.

[0126] In an exemplary embodiment, the number of data fan-out lines 700 is less than or equal to the number of data lines DA.

[0127] In an exemplary embodiment, as Figure 12 shown, at least one third sub-pixel P13 includes a virtual data fan-out line 701, and the virtual data fan-out line 701 is connected to a fixed potential signal line through a signal trace.

[0128] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first gate electrode layer, a second gate electrode layer, a source-drain electrode layer, and an anode stacked on a substrate. Insulating layers are provided between the first gate electrode layer and the second gate electrode layer, between the second gate electrode layer and the source-drain electrode layer, and between the source-drain electrode layer and the anode, where:

[0129] The semiconductor layer includes active layers of multiple transistors, the first gate electrode layer includes multiple scan signal lines, gate electrodes of multiple transistors, and multiple first capacitor electrodes, the second gate electrode layer includes multiple second capacitor electrodes, and the source-drain electrode layer includes multiple data lines DA, source electrodes and drain electrodes of multiple transistors; the first capacitor electrodes and the second capacitor electrodes form a capacitor, and the transistors and the capacitor form a pixel circuit;

[0130] Multiple data fan-out lines 700 can be disposed on the same layer as one or more of the first gate electrode layer and the second gate electrode layer.

[0131] In an exemplary embodiment, as Figure 14 shown, the display substrate includes a semiconductor layer, a first gate electrode layer, a second gate electrode layer, a first source / drain electrode layer, a second source / drain electrode layer, and an anode stacked on a substrate, where:

[0132] The semiconductor layer includes active layers of a plurality of transistors, the first gate electrode layer includes gate electrodes of a plurality of transistors and a plurality of first capacitor electrodes, the second gate electrode layer includes a plurality of second capacitor electrodes, the first source / drain electrode layer includes a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, and the second source / drain electrode layer includes connection electrodes; the first capacitor electrodes and the second capacitor electrodes form a capacitor, and the transistors and the capacitor form a pixel circuit;

[0133] A plurality of data fan-out lines 700 may be disposed in the same layer as one or more of the first gate electrode layer, the second gate electrode layer, and the second source / drain electrode layer.

[0134] In an exemplary embodiment, as Figure 15 shown, the display substrate includes a light-shielding layer (not shown in the figure), a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second semiconductor layer, a third gate electrode layer, a source / drain electrode layer, and an anode stacked on a substrate, where:

[0135] The first semiconductor layer includes active layers of at least one polysilicon transistor, the first gate electrode layer includes gate electrodes of at least one polysilicon transistor and a plurality of first capacitor electrodes, the second gate electrode layer includes a plurality of second capacitor electrodes, the second semiconductor layer includes active layers of at least one oxide transistor, the third gate electrode layer includes gate electrodes of at least one oxide transistor, and the source / drain electrode layer includes a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors;

[0136] A plurality of data fan-out lines 700 may be disposed in the same layer as one or more of the light-shielding layer, the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer.

[0137] In an exemplary embodiment, as Figure 14 or Figure 15 shown, at least one third sub-pixel P13 includes any one or more of the following virtual electrode lines 102C: a virtual active layer, a virtual gate electrode, a virtual capacitor electrode, a virtual source / drain electrode, and the virtual electrode line 102C is connected to a fixed-potential signal line through a signal trace

[0138] An exemplary description is given below through a preparation process of a display substrate. The "patterning process" in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be any one or more of spraying, spin coating, and inkjet printing. Etching can be any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the orthographic projection range of A" means that the edge of the display area of the orthographic projection of B falls within the edge of the display area of the orthographic projection of A, or the edge of the display area of the orthographic projection of A overlaps with the edge of the display area of the orthographic projection of B.

[0139] In one exemplary embodiment, the preparation process of the display substrate may include the following operations.

[0140] (1)Form a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate, and a semiconductor layer pattern disposed on the first insulating layer, where the semiconductor layer pattern includes at least active layers of a plurality of transistors. The semiconductor layer pattern is formed in a first display area and a second display area. In an exemplary embodiment, the semiconductor layer pattern may also be formed in a fan-out routing area. Since the subsequent formed data fan-out lines include at least one horizontal connection portion and at least one vertical connection portion, the horizontal connection portion of the data fan-out line may be disposed between two adjacent sub-pixels. Therefore, the horizontal connection portion of the data fan-out line does not affect the pixel circuit layout in the sub-pixel adjacent to the horizontal connection portion, or rather, the horizontal connection portion of the data fan-out line has a relatively small impact on the pixel circuit layout in the sub-pixel adjacent to the horizontal connection portion. Thus, in the fan-out routing area, pixel circuits are not provided in the sub-pixels where the orthographic projection on the substrate overlaps with the vertical connection portion of the data fan-out line on the substrate, while pixel circuits may be provided in the sub-pixels adjacent to the horizontal connection portion of the data fan-out line. That is, each sub-pixel in the first display area and the second display area includes a semiconductor layer pattern, and some or all of the sub-pixels in the fan-out routing area do not include a semiconductor layer pattern. In an exemplary embodiment, the substrate may be a flexible substrate.

[0141] (2)Form a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, where the first conductive layer pattern includes at least a plurality of data fan-out lines located in the display area, a plurality of scan signal lines, gate electrodes of a plurality of transistors, and a plurality of first capacitor electrodes, and a plurality of lead-out lines located in the lead area of the bonding area. The data fan-out lines and the lead-out lines may be an integrated structure connected to each other. In an exemplary embodiment, the data fan-out lines are formed in the fan-out routing area. In an exemplary embodiment, the first conductive layer may be referred to as a first gate electrode (GATE 1) layer.

[0142] (3) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, patterning the second metal film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern at least includes a plurality of second capacitive electrodes located in the display area. In an exemplary embodiment, the second conductive layer may be referred to as the second gate electrode (GATE 2) layer.

[0143] (4) Form a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer covering the second conductive layer pattern. A plurality of vias are formed in the fourth insulating layer. The plurality of vias may include: active vias located at the positions of a plurality of active layers in the display area, and a plurality of first vias and second vias at the ends of data fan-out lines in the display area. The active vias expose the active layers, the first vias expose the data fan-out lines, and the second vias expose the lead-out lines.

[0144] (5) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third metal film on the substrate on which the foregoing pattern is formed, patterning the third metal film through a patterning process to form a third conductive layer pattern on the fourth insulating layer. The third conductive layer pattern at least includes: a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors. The source electrodes and drain electrodes are respectively connected to the corresponding active layers through the active vias. The plurality of data lines extend to the lead area in the bonding area. A part of the data lines is connected to the data fan-out lines through the first vias, and another part of the data lines is connected to the lead-out lines through the second vias. In an exemplary embodiment, the third conductive layer may be referred to as the first source-drain electrode (SD1) layer.

[0145] (6) Form an electrode connection layer pattern. In an exemplary embodiment, forming the electrode connection layer pattern may include: sequentially depositing a fifth insulating thin film and an electrode connection layer thin film on the substrate on which the foregoing pattern is formed, patterning the fifth insulating thin film and the electrode connection layer thin film respectively by a patterning process to form a fifth insulating layer covering the third conductive layer pattern, and an electrode connection layer pattern provided on the fifth insulating layer. A plurality of third vias are formed in the fifth insulating layer, and the fifth insulating layer within the third vias is removed to expose the surfaces of the drain electrodes of a plurality of transistors. The electrode connection layer pattern includes at least a plurality of mutually insulated first connection lines and second connection lines. One end of the first connection line is connected to the drain electrode of the transistor through a third via. The first connection line is formed in the first display area, the second display area, and the fan-out wiring area. The second connection line is formed in the second display area and the fan-out wiring area. The first connection line is configured to connect the anodes of the first light-emitting elements to be formed later, a part of the anodes of the second light-emitting elements, and a part of the anodes of the third light-emitting elements to the drain electrode of the transistor. The second connection line is configured to connect the anodes of the second light-emitting elements and the third light-emitting elements to be formed later pairwise with each other.

[0146] (7) Form a planarization layer pattern. In an exemplary embodiment, forming the planarization layer pattern may include: coating a planarization thin film on the substrate on which the foregoing pattern is formed, patterning the planarization thin film by a patterning process to form a planarization layer covering the electrode connection layer. A fourth via and a fifth via are provided on the planarization layer. The fourth via exposes the other end of the first connection line. The fifth via exposes both ends of the second connection line. The fourth via is configured to connect the anodes of the first light-emitting elements to be formed later, a part of the anodes of the second light-emitting elements, and a part of the anodes of the third light-emitting elements to the other end of the first connection line through the via. The fifth via is configured to connect the anodes of the second light-emitting elements and the third light-emitting elements to be formed later pairwise with each other through the via to the second connection line.

[0147] (8) Form an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a transparent conductive thin film on the substrate on which the foregoing pattern is formed, patterning the transparent conductive thin film by a patterning process to form an anode provided on the planarization layer. The anodes of the first light-emitting elements, a part of the anodes of the second light-emitting elements, and a part of the anodes of the third light-emitting elements are connected to the other end of the first connection line through the fourth via. The anodes of the second light-emitting elements and the third light-emitting elements are connected pairwise with each other through the fifth via to the second connection line.

[0148] In an exemplary embodiment, the subsequent preparation process may include: coating a pixel definition thin film, patterning the pixel definition thin film through a patterning process to form a pixel definition layer, and a pixel opening is provided in the pixel definition layer of each sub-pixel, and the pixel opening exposes the anode. An organic light-emitting layer is formed by evaporation or inkjet printing, and a cathode is formed on the organic light-emitting layer. A packaging layer is formed, and the packaging layer may include a stacked first packaging layer, second packaging layer, and third packaging layer. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer is disposed between the first packaging layer and the third packaging layer, which can ensure that external moisture cannot enter the light-emitting structure layer, such as Figure 16 as shown

[0149] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a stacked first flexible material layer, first inorganic material layer, semiconductor layer, second flexible material layer, and second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-si).

[0150] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The material of the electrode connection layer is a transparent conductive material, specifically indium tin oxide ITO or indium zinc oxide IZO. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer is called a buffer layer and is used to improve the water and oxygen resistance of the substrate. The second insulating layer and the third insulating layer are called gate insulating (GI) layers. The fourth insulating layer is called an interlayer dielectric (ILD) layer. The planarization layer may be made of an organic material, and the transparent conductive thin film may be indium tin oxide ITO or indium zinc oxide IZO. The active layer may be made of polysilicon (p-Si), that is, the present disclosure is applicable to LTPS thin film transistors.

[0151] Although the preparation process of the substrate in this embodiment is described by taking the data fan-out line arranged in the first conductive layer and the data line arranged in the third conductive layer as an example, in the present disclosure, the data fan-out line and the data line may be arranged in any layer, as long as it is ensured that the data line and the data fan-out line are located in different conductive layers. The present disclosure does not make any limitation here.

[0152] The structure of the display substrate shown in the present disclosure and its preparation process are merely an exemplary illustration. In the exemplary embodiment, the corresponding structure may be changed according to actual needs, and the patterning process may be increased or decreased. The present disclosure does not make any limitation here.

[0153] In a display substrate, a fan-out area is provided in the bonding area, and the data lines in the display area are led out through the data fan-out lines in the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower border is relatively wide, which is not conducive to realizing a narrow border. In the exemplary embodiment of the present disclosure, lead-out lines are provided in the lead-out area of the bonding area, and data fan-out lines are provided in the display area. The lead-out lines are connected to the corresponding data signal lines through the data fan-out lines. This not only realizes the corresponding connection between multiple lead-out lines and multiple data signal lines, but also makes it unnecessary to set fan-shaped oblique lines in the lead-out area. The multiple lead-out lines are parallel vertical lines and can be directly introduced into the composite circuit area of the bonding area, effectively reducing the vertical length of the lead-out area, greatly reducing the width of the lower border, making the widths of the upper border, lower border, left border, and right border of the display device similar, all less than 1.0 mm, improving the screen-to-body ratio, and being conducive to realizing a full-screen display.

[0154] In an exemplary embodiment of the present disclosure, by providing a second pixel circuit in the sub-pixels of the second display region, and not providing a pixel circuit in the sub-pixels of the fan-out routing region, but only providing a third light-emitting element, the second pixel circuit can drive the second light-emitting element or the third light-emitting element, so that sufficient space can be vacated in the fan-out routing region for the routing of data fan-out lines.

[0155] In an exemplary embodiment, as Figure 14 shown in FIG. 15, in the fan-out routing region, at least one third sub-pixel may be provided with any one or more of the following virtual electrode lines 102C: a virtual active layer, a virtual gate electrode, a virtual capacitor electrode, a virtual source-drain electrode, and the virtual electrode lines may be connected to a fixed potential signal line through signal routing. By providing virtual electrode lines in at least one third sub-pixel in an exemplary embodiment of the present disclosure, the uniformity of the display substrate manufacturing process can be improved, and thus the manufacturing quality can be improved.

[0156] An exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate. The display substrate includes a display region and a non-display region surrounding the display region. The display region includes a first display region, a second display region, and a fan-out routing region. The second display region is located between the first display region and the fan-out routing region. The manufacturing method includes:

[0157] forming a plurality of first sub-pixels in the first display region, the first sub-pixels including a first pixel circuit and a first light-emitting element, and the positive projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap; forming a plurality of second sub-pixels in the second display region, the second sub-pixels including a second pixel circuit and a second light-emitting element, and the positive projections of the second pixel circuit and the second light-emitting element on the display substrate at least partially overlap, and the first pixel circuit and the second pixel circuit are electrically connected to a plurality of data lines; forming a plurality of third sub-pixels and a plurality of data fan-out lines in the fan-out routing region, the third sub-pixels including a third light-emitting element, at least one second pixel circuit is electrically connected to at least two light-emitting elements, and at least two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element, and the plurality of data fan-out lines are electrically connected to the plurality of data lines.

[0158] An exemplary embodiment of the present disclosure also provides a display device, including the display substrate of the foregoing embodiment. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an advertising panel, a watch phone, an e-book, a portable multimedia player, or a display screen of various products of the Internet of Things, etc., any product or component with a display function. In an exemplary embodiment, the display device may be a wearable display device that can be worn on the human body in some way, such as a smart watch, a smart bracelet, etc.

[0159] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general designs. Without conflict, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments.

[0160] Those of ordinary skill in the art should understand that the technical solutions of this disclosure can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of this disclosure, and all should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate includes a display area and a non-display area surrounding the display area. The display area includes a first display area, a second display area, and a fan-out routing area. The second display area is located between the first display area and the fan-out routing area; A plurality of data lines are located in the display area; The first display area includes a plurality of first sub-pixels. The first sub-pixels include a first pixel circuit and a first light-emitting element. The orthographic projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap; The second display area includes a plurality of second sub-pixels. The second sub-pixels include a second pixel circuit and a second light-emitting element. The orthographic projections of the second pixel circuit and the second light-emitting element on the display substrate at least partially overlap; The first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines; The fan-out routing area includes a plurality of data fan-out lines and a plurality of third sub-pixels. At least a part of the third sub-pixels includes a third light-emitting element and does not include a third pixel circuit. The orthographic projection of the data fan-out lines on the display substrate plane partially overlaps with the orthographic projection of at least a part of the third sub-pixels on the display substrate. At least one of the second pixel circuits is electrically connected to the anodes of at least two light-emitting elements through a connection line. The at least two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element. The plurality of data fan-out lines are electrically connected to the plurality of data lines.

2. The display substrate according to claim 1, wherein, The orthographic projection of the second pixel circuit on the display substrate plane and the orthographic projection of the third light-emitting element on the display substrate plane do not overlap.

3. The display substrate according to claim 1, wherein The data fan-out lines are stepped traces. The orthographic projection of the data fan-out lines on the display substrate plane does not overlap with the orthographic projections of the first pixel circuit and the second pixel circuit on the display substrate plane.

4. The display substrate according to claim 1, wherein, The display area includes a first connection line and a second connection line. The first connection line is configured to connect at least one of the following: the first pixel circuit and the anode of the first light-emitting element, the second pixel circuit and the anode of the second light-emitting element, the second pixel circuit and the anode of the third light-emitting element; The second connection line is configured to connect the anodes of the at least two light-emitting elements.

5. The display substrate according to claim 4, wherein, The materials of the first connection line and the second connection line are transparent conductive materials.

6. The display substrate according to claim 4, wherein, The fan-out routing area includes a first-color light-emitting element, a second-color light-emitting element, and a third-color light-emitting element. The second connection line is configured to connect the anodes of at least two of the third-color light-emitting elements.

7. The display substrate according to claim 6, wherein, The third-color light-emitting element is a green light-emitting element.

8. The display substrate according to claim 6, wherein, At least another part of the third sub-pixels includes a third light-emitting element and a third pixel circuit. The orthographic projection of the third pixel circuit on the display substrate at least partially overlaps with the orthographic projection of the first-color light-emitting element or the second-color light-emitting element on the display substrate, and does not overlap with the orthographic projection of the third-color light-emitting element on the display substrate.

9. The display substrate according to claim 6, wherein, The second connection line is further configured to connect at least one of the following: anodes of at least two of the first color light-emitting elements, anodes of at least two of the second color light-emitting elements.

10. The display substrate according to claim 1, wherein, The data fan-out line includes at least one horizontal connection portion and at least one vertical connection portion. A positive projection of the horizontal connection portion on the display substrate plane does not overlap with a positive projection of the third light-emitting element on the display substrate plane, and a positive projection of the vertical connection portion on the display substrate plane and a positive projection of the third light-emitting element on the display substrate plane have at least an overlapping area.

11. The display substrate according to claim 1, wherein, The at least one second pixel circuit is electrically connected to at least two light-emitting elements and includes any one or more of the following: Two of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element; Three of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The three light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element; Four of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The four light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element; Five of the light-emitting elements are connected in series and then connected to one of the second pixel circuits. The five light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element.

12. The display substrate according to any one of claims 1 to 11, wherein, The display substrate includes a semiconductor layer, a first gate electrode layer, a second gate electrode layer, a first source-drain electrode layer, a second source-drain electrode layer, and an anode stacked on a substrate, wherein: The semiconductor layer includes active layers of multiple transistors. The first gate electrode layer includes gate electrodes of multiple transistors and multiple first capacitor electrodes. The second gate electrode layer includes multiple second capacitor electrodes. The first source-drain electrode layer includes multiple data lines, source electrodes and drain electrodes of multiple transistors. The second source-drain electrode layer includes connection electrodes; The multiple data fan-out lines are disposed in the same layer as one or more of the first gate electrode layer, the second gate electrode layer, and the second source-drain electrode layer.

13. The display substrate according to any one of claims 1 to 11, wherein, The display substrate includes a light-shielding layer, a first semiconductor layer, a first gate electrode layer, a second gate electrode layer, a second semiconductor layer, a third gate electrode layer, a source-drain electrode layer, and an anode stacked on a substrate, wherein: The first semiconductor layer includes active layers of at least one polysilicon transistor. The first gate electrode layer includes gate electrodes of at least one polysilicon transistor and multiple first capacitor electrodes. The second gate electrode layer includes multiple second capacitor electrodes. The second semiconductor layer includes active layers of at least one oxide transistor. The third gate electrode layer includes gate electrodes of at least one oxide transistor. The source-drain electrode layer includes multiple data lines, source electrodes and drain electrodes of multiple transistors; The multiple data fan-out lines are disposed in the same layer as one or more of the light-shielding layer, the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer.

14. The display substrate according to claim 12 or 13 further includes an electrode connection layer disposed between the source-drain electrode layer and the anode, and the material of the electrode connection layer is indium tin oxide or indium zinc oxide.

15. The display substrate according to claim 12 or 13, wherein At least one of the third sub-pixels includes any one or more of the following virtual electrode lines: a virtual active layer, a virtual gate electrode, a virtual capacitor electrode, and a virtual source-drain electrode, and the virtual electrode lines are connected to the fixed potential signal lines through signal traces.

16. The display substrate according to claim 12 or 13, wherein At least one of the third sub-pixels includes a virtual data fan-out line, and the virtual data fan-out line is connected to the fixed potential signal line through a signal trace.

17. A display device includes the display substrate according to any one of claims 1 to 16.

18. A method for manufacturing a display substrate, the display substrate includes a display area and a non-display area surrounding the display area, the display area includes a first display area, a second display area, and a fan-out trace area, and the second display area is located between the first display area and the fan-out trace area; the manufacturing method includes: Forming a plurality of first sub-pixels in the first display area, the first sub-pixels include a first pixel circuit and a first light-emitting element, and the orthographic projections of the first pixel circuit and the first light-emitting element on the display substrate at least partially overlap; Forming a plurality of second sub-pixels in the second display area, the second sub-pixels include a second pixel circuit and a second light-emitting element, and the orthographic projections of the second pixel circuit and the second light-emitting element on the display substrate at least partially overlap, the first pixel circuit and the second pixel circuit are electrically connected to the plurality of data lines; forming a plurality of third sub-pixels and a plurality of data fan-out lines in the fan-out trace area, at least a part of the third sub-pixels include a third light-emitting element and do not include a third pixel circuit, the orthographic projection of the data fan-out line on the display substrate plane partially overlaps with the orthographic projection of at least a part of the third sub-pixels on the display substrate, at least one of the second pixel circuits is electrically connected to the anodes of at least two light-emitting elements through a connection line, the at least two light-emitting elements are selected from at least one of the second light-emitting element and the third light-emitting element, and the plurality of data fan-out lines are electrically connected to the plurality of data lines.

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