A RISC-V vector processing unit implementation method and architecture

Abstract

The present invention discloses a RISC-V vector processing unit implementation method, which is based on the RISC-V processor vector extension set and implemented in a coprocessor mode. The vector processing unit includes four ports, namely, a main processor interaction port, a vector instruction request port, a vector instruction feedback port, and a vector instruction memory write port. The vector processing unit includes a three-level pipeline, supports sequential dispatch, out-of-order execution, and out-of-order writeback, including decoding and dispatching, execution, writeback and delivery, and its instruction fetching and partial decoding are completed in a scalar processor. The decoding and dispatching are used as the first-level pipeline to decode and pipeline conflict judgment of the vector instruction when the vector unit receives the vector instruction of the main processor. If there is no pipeline conflict, it can be dispatched, the execution is used as the second-level pipeline for the execution of the vector instruction, and the writeback is used as the third-level pipeline for the writeback of the vector instruction, including writing back a scalar register and writing back a vector register.

Description

Technical Field

[0001] The present invention relates to the field of RISC-V vector extension technology, and in particular to a RISC-V vector processing unit implementation method and architecture. Background Art

[0002] Data-level parallelism has achieved stability in a wide range of applications such as multimedia, data flow, and more recently machine learning and deep learning, and RISC-V vector extensions are now ready for approval of version 1.0, and relatively few implementations of RISC-V vector extensions have been implemented in China.

[0003] At present, there are generally two forms for implementing vector extension. One design uses a coprocessor to expand around the application processor. Although it increases the complexity of the interface between the scalar and vector parts, it has strong scalability. The execution modules of vector instructions and scalar instructions can be completely separated. The traditional vector architecture based on multi-channel design is used internally. The vector registers are divided into blocks and multiple identical channels for parallel execution are connected. The width of each channel is the same as the maximum data size. Each channel provides a corresponding arithmetic logic unit, but this design consumes huge area and power consumption. The early RISC-V vector extension version is suitable for multi-channel technology, but some changes introduced by its new RISC-V vector extension 1.0 version will make the vector processing unit design using multi-channel technology face cross-channel data processing problems. When using multi-channel technology, additional module design needs to be added to solve the cross-channel data problem. This design will increase the complexity of the entire vector unit design, especially when the number of channels is increased.

[0004] Another is to integrate the vector processing unit into the scalar processor to avoid the interface between the scalar and vector parts. The internal operation unit is designed in a SIMD pipeline manner. The processor executes in sequence and is single-cycle. Instead of queuing multiple instructions into the execution channel, one instruction is executed at a time, thereby eliminating the need for scheduling instruction design. Instructions can be executed in multiple cycles according to the operation and vector length. Pipelines can be added to increase the maximum frequency. The internal vector register design is the same as the scalar processor, but multiple data ports are provided. The data path width matches the vector register length. This design simplifies data transmission to the arithmetic logic unit because the data of one register is transmitted per cycle. The power consumption and area are relatively small, but the performance improvement brought by adding vector extension is relatively low. This design combines the advantages of the two design methods. First, the scalar processor is vector-extended in a coprocessor manner. As a functional unit in the execution stage of the scalar processor, the operation and implementation of the vector instructions are defined and separated from the scalar execution unit, which improves the execution rate of vector instructions and reduces the dependence on the scalar processor. Regardless of the scalar processor architecture, as long as the scalar processor supports the coprocessor port design, it can be vector-extended. The second design uses SIMD pipelining in the execution module, which can not only simplify data transmission, but also avoid the additional design caused by the cross-lane data problem faced by the use of multi-channel technology, which can reduce the implementation complexity and bring better performance improvement. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention proposes a RISC-V vector processing unit implementation method and architecture, which is built on a scalar RISC-V main processor in the form of a coprocessor.

[0006] In order to solve the above technical problems, the technical solution of the present invention is:

[0007] A RISC-V vector processing unit implementation method comprises the following steps:

[0008] S1, vector instruction preparation stage, executed in the scalar processor, fetch vector instructions, perform simple decoding on the vector instructions, determine whether a scalar source operand is required, read the scalar register, and the scalar processor FIFO, determine the scalar data correlation, and if it can be dispatched, save the vector instruction destination register index information that needs to be written back to the scalar register in the scalar processor FIFO, and generate a vector instruction request signal, waiting for the vector processing unit to respond;

[0009] S2, vector instruction decoding and dispatching stage, judging whether to respond to the main processor vector request signal according to the vector unit's own state;

[0010] S3, vector instruction execution stage, this stage is used to execute vector instructions, and indirectly realize the execution of all elements in the register group through multiple cycle execution. The total bit width of each element is VLEN bits, that is, the length of a vector register. Each execution unit adopts pipeline design, that is, SIMD pipeline;

[0011] S4, vector instruction write back and delivery stage, vector instructions can be written back to scalar registers and vector registers. The vector written back to the scalar register needs to generate feedback information to the scalar processor through the vector instruction feedback port, and wait for the scalar processor to respond. It can be directly written back to the scalar processor through the feedback port of the vector processing unit, and the instruction information saved in the scalar processor is removed, completing the delivery of the instruction. The vector instruction written back to the vector register is directly written back to the vector register through arbitration and the information saved in the dispatch stage is removed to complete the delivery of the vector instruction.

[0012] Preferably, in step S2, if a response is received, the vector instruction and the scalar source operand are received, and then the vector instruction is fully decoded, the format of the decoding instruction and the vector register are read, and the pipeline conflict is determined to decide whether to dispatch the vector instruction.

[0013] Preferably, in step S3, the execution unit includes a read-write unit, a functional unit, and a data processing unit. The read-write unit is used to read and write source operands, the functional unit is used to execute the operation to be performed by the instruction, and the data processing unit processes the data of the functional unit to obtain the data to be finally written back.

[0014] Preferably, the pipeline conflict includes data conflict and resource conflict.

[0015] As a preferred solution to the pipeline conflict:

[0016] Solution to resource conflicts: block the currently dispatched instructions until the resource conflicts are resolved;

[0017] Solution to data conflict: There is no instruction in the instruction blocking register, and the vector instruction is a vector instruction that has just been received. If the required source operation data is being written back, the data can be read through the data bypass in the vector register module, otherwise the instruction is saved in the vector instruction register. For the vector instruction saved in the instruction blocking register, after the correlation is released, it is necessary to read the operand from the vector register module again. If the data is being written back, the data can be read through the data bypass in the vector register module, otherwise the value in the vector register module is read.

[0018] As a preferred write-back method, for vector instructions that write back scalar registers, sequential dispatch, sequential execution, and sequential write-back are adopted. Only one vector instruction that writes back to a scalar register can be executed at a time. For vector instructions that write back to vector registers, sequential dispatch, out-of-order execution, and out-of-order write-back are adopted. Multiple instruction execution is supported according to the size of the instruction execution.

[0019] The present invention provides a RISC-V vector processing unit implementation architecture, including:

[0020] The vector instruction decoding module decodes the vector instruction encoding rules of the RISC-V vector extension standard document 1.0 to generate different instruction type information and operand register index information;

[0021] The vector instruction dispatch module is used to dispatch vector instructions. It uses an instruction blocking register group to save the vector instruction information that has pipeline conflicts in the vector unit when the scalar processor resolves data dependencies. It receives instruction information from the vector decoding module and sends it to the vector pipeline judgment module to determine whether there is a pipeline conflict. If not, the vector instruction can be dispatched. If there is a pipeline conflict, the vector instruction is blocked and the decoding information of the vector instruction and the operands read from the vector register are saved in the instruction blocking register group. It waits for the pipeline conflict to be resolved, dispatches it and removes the value saved in the instruction blocking register.

[0022] Vector pipeline conflict judgment module, this module is used to judge pipeline conflicts and vector instruction delivery, and uses an instruction execution register group to save the information of the vector instruction being executed and the order of executing instructions. When the vector instruction information that needs to be dispatched by the dispatch module is received, it is judged with the vector instruction being executed whether a pipeline conflict occurs. If there is a pipeline conflict, a signal that it cannot be dispatched is generated to the dispatch module. When there is no pipeline conflict, a signal that it can be dispatched is generated to the dispatch module, and the instruction information and execution order are saved in the instruction execution register group. Vector instruction delivery, when the signal from the end of the vector instruction is received, the instruction information saved in the instruction execution register group will be removed, and the delivery of the instruction will be completed;

[0023] The vector register module includes multiple read register port groups, a general register port group, an additional read register port group required for executing multiple instructions at the same time, and a write-back port group. The read register port group includes four read ports, and the write-back port group includes two write-back ports. It contains 32 general registers of VLEN length. The read port logic generally reads data according to the input register index value, but a data bypass is added at the read port. When the register index of the write-back data is the same as the source operand index to be read, it is directly sent to the output port instead of reading the register value. The write port logic generally uses one write-back port to write back vector instructions. The additional write-back port is for writing back double-width instructions. Since the register index differs by 1, it will not cause the same register file to be written. It is only necessary to judge that the register index values ​​are different in the write-back logic.

[0024] The vector control status register module is added and designed according to the RISC-V vector extension standard document, which is used to execute vector control status configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output the tasks performed by the vector control status register module to the execution unit;

[0025] A vector execution module, divided into a vector load and store unit, a vector integer operation unit, a vector integer multiply-add operation unit, a vector floating-point operation unit, a vector permute operation unit, a vector reduction unit and a vector mask unit according to the vector instruction type;

[0026] The vector write back module includes a write back scalar register module and a write back vector register module (VWBCK_VD).

[0027] Preferably, in the vector execution module: the vector integer operation unit is responsible for vector integer addition, subtraction, multiplication and division operation instructions; the vector integer multiplication and addition operation unit is responsible for vector integer multiplication and addition operation instructions; and the vector floating point operation unit is responsible for vector floating point instruction operations. The vector permutation operation unit is responsible for the execution of vector permutation instructions; the vector reduction unit is responsible for the instructions of vector reduction instructions; the vector mask unit is responsible for the execution of vector mask instructions; the vector execution module adopts SIMD pipeline design, including read-write unit, functional unit, data processing unit, the read-write unit is designed with a state machine, divided into two states 0 and 1, when the state machine is in state 0, waiting for the execution unit enable signal, if the vector instruction selects the execution unit, an enable signal will be generated, and if there is an enable signal, it will jump to state 1; write operation, the instruction information to be executed by the execution instruction is saved in the internal register, the instruction information includes register index, vector length, vector element width, operation object; read operation, it will determine whether the next operand needs to be read according to the vector length, when the state machine is in state 1, it will determine whether the instruction execution is completed, if it continues to be executed, it will maintain state 1, if it is completed, it will jump to state 0, the functional unit is equivalent to the SIMD execution unit, can support the execution of multiple vector elements with different bit widths, the maximum execution element bit width is VLEN, the data processing unit processes the output data of the functional unit to obtain the final write-back data.

[0028] As a preference: in the vector write-back module: if the current vector instruction needs to be written back to the scalar register, it is directly written back through the feedback port of the vector processing unit; if the vector instruction needs to be written back to the vector register, it can be directly written back when only one instruction is executed; when two instructions executed simultaneously need to be written back, they are arbitrated according to the execution instruction order saved in the instruction execution register group; the first one dispatched can be written back first, and the write-back data of the later one dispatched can be saved in its corresponding FIFO until there is no data to write back, and it is read from the FIFO and written back to the vector register; after the instruction execution is completed, the instruction execution register will determine whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located; if completed, the instruction information is removed to complete the delivery.

[0029] The present invention has the following characteristics and beneficial effects:

[0030] This design uses a coprocessor to vectorize the scalar processor. When designing the vector unit, firstly, only one instruction of this type is executed each time for the vector instruction that writes back to the scalar register, so that the strict sequential write-back can be achieved, that is, the signal of the main processor is not required to arbitrate the write-back, reducing the dependence on the scalar processor. Secondly, the vector instruction that writes back to the vector register is defined as a short-cycle instruction, so that the main processor does not need to feedback to the main processor when writing back the vector register, and the execution and delivery are completed directly in the vector unit, which improves the execution speed of the vector instruction and enhances its scalability. When another RISC-V scalar processor supports the coprocessor port design, it can be vectorized. Finally, the internal execution module design of the vector unit is a SIMD pipeline design. This design is superior to the multi-channel architecture design. The purpose is to minimize the pressure on the vector register, without the need to divide the vector register, simplify data transmission, and provide a unified execution method for vector instructions, avoiding the additional design caused by the cross-lane data problem, reducing the implementation complexity, and improving performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0032] Figure 1 The figure is a schematic diagram of an implementation method of an embodiment of the present invention.

[0033] Figure 2 Schematic diagram of a decoding module in an embodiment of the present invention.

[0034] Figure 3 Schematic diagram of a dispatch module in an embodiment of the present invention.

[0035] Figure 4 Schematic diagram of a pipeline conflict determination module in an embodiment of the present invention.

[0036] Figure 5 Schematic diagram of a vector register module in an embodiment of the present invention.

[0037] Figure 6 Schematic diagram of a vector control state module in an embodiment of the present invention.

[0038] Figure 7 It is a schematic diagram of an execution module in an embodiment of the present invention.

[0039] Figure 8 It is a schematic diagram of a write-back module in an embodiment of the present invention.

[0040] Fig. 9 Schematic diagram of a vector unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0042] The present invention provides a RISC-V vector processing unit implementation architecture, such as Fig. 9 As shown, it includes a vector instruction decoding module, such as Figure 2 As shown, decoding is performed according to the vector instruction encoding rules of the RISC-V vector extension standard document 1.0 to generate different instruction type information and operand register index information.

[0043] Vector instruction dispatch module, such as Figure 3 As shown, this module is used to dispatch vector instructions, and uses an instruction blocking register group to save the vector instruction information of the vector unit that has pipeline conflicts in the vector unit after the data is released in the scalar processor. Receive the instruction information of the vector decoding module, send it to the vector pipeline judgment module, and judge whether there is a pipeline conflict. If not, the vector instruction can be dispatched. If there is a pipeline conflict, the vector instruction is blocked, and the decoding information of the vector instruction and the operand read from the vector register are saved in the instruction blocking register group, waiting for the pipeline conflict to be released, dispatch it and remove the value saved in the instruction blocking register.

[0044] Vector pipeline conflict judgment module, such as Figure 4 As shown, this module is used to determine pipeline conflicts and vector instruction delivery, and uses an instruction execution register group to save the information of the vector instruction being executed and the order of executing instructions. When the vector instruction information that the dispatch module needs to dispatch is received, it is judged with the vector instruction being executed whether a pipeline conflict occurs. When there is a pipeline conflict, a signal that it cannot be dispatched is generated to the dispatch module. When there is no pipeline conflict, a signal that it can be dispatched is generated to the dispatch module, and the instruction information and execution order are saved in the instruction execution register group. When the vector instruction is delivered, when the signal from the end of the vector instruction is received, the instruction information saved in the instruction execution register group will be removed, that is, the delivery of the instruction is completed.

[0045] Vector register modules, such as Figure 5As shown, multiple read register port groups (one group contains four read ports), including a general register port group and an additional read register port group required for executing multiple instructions at the same time, and a write back port group (one group contains two write back ports), which contains 32 general registers of VLEN length. The read port logic generally reads out data according to the input register index value, but a data bypass is added here at the read port. When the register index of the write-back data is the same as the source operand index to be read, it is directly sent to the output port instead of reading the register value. Write port logic, generally vector instructions only need to use one write back port to write back, and the additional write back port is for writing back double width instructions. Since their register indexes differ by 1, it will not cause the same register file to be written. It is only necessary to judge that the register index values ​​are different in the write back logic.

[0046] Vector control status register module, such as Figure 6 As shown, it is added and designed according to the RISC-V vector extension standard document, which can be used to execute vector control state configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output the tasks performed by the vector control state register module to the execution unit.

[0047] Vector execution modules, such as Figure 7As shown, according to the vector instruction type, it is divided into a vector load and store unit (VLSU), a vector integer arithmetic unit (V_INT_ALU), a vector integer multiplication and addition arithmetic unit (V_INT_MAC), a vector floating-point arithmetic unit (V_FP), a vector permutation arithmetic unit (V_PERMUTE), a vector reduction unit (V_REDUCT), and a vector mask unit (VMASK). The vector integer arithmetic unit is responsible for the arithmetic instructions of vector integer addition, subtraction, multiplication, and division, and the vector integer multiplication and addition arithmetic unit is responsible for the arithmetic instructions of vector integer multiplication and addition. The vector floating-point arithmetic unit is responsible for the operation of vector floating-point instructions. The vector permutation arithmetic unit is responsible for the execution of vector permutation instructions. The vector reduction unit is responsible for the instructions of vector reduction instructions. The vector mask unit is responsible for the execution of vector mask instructions. The vector execution module adopts SIMD pipeline design, including read-write unit, function unit, and data processing unit. The read-write unit is designed with a state machine, which is divided into two states 0 and 1. When the state machine is in state 0, it waits for the enable signal of the execution unit. If the vector instruction selects the execution unit, an enable signal will be generated. If there is an enable signal, it will jump to state 1. For write operation, the instruction information (including register index, vector length, vector element width, and operation object) to be executed is saved in the internal register. For read operation, it will determine whether the next operand needs to be read based on the vector length. When the state machine is in state 1, it will determine whether the instruction execution has ended. If it continues to execute, it will maintain state 1, and if it ends, it will jump to state 0. The functional unit is equivalent to the SIMD execution unit, which can support the execution of multiple vector elements with different bit widths, and the maximum execution element bit width is VLEN. The data processing unit processes the output data of the functional unit to obtain the final write-back data.

[0048] Vector write-back modules such as Figure 8 As shown, it includes a write-back scalar register module (VWBCK_RD) and a write-back vector register module (VWBCK_VD). If the current vector instruction needs to write back the scalar register, it is directly written back through the feedback port of the vector processing unit. If the vector instruction needs to write back the vector register, it can be directly written back when only one instruction is executed. When two instructions executed at the same time need to be written back, they are arbitrated according to the execution instruction order saved by the instruction execution register group. The first dispatched one can be written back first, and the write-back data of the later dispatched one is saved in its corresponding FIFO until there is no data to write back. It is read from the FIFO and written back to the vector register. After the instruction execution is completed, the instruction execution register will determine whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located. If it is completed, the instruction information is removed to complete the delivery.

[0049] Among them, for pipeline conflict judgment, for resource conflicts, read-after-write dependency (WAR) and write-after-write dependency (WAW), the solution is: block the currently dispatched instruction until the resource conflict is resolved. For write-before-read dependency (RAW), true data dependency, the solution is: (1) There is no instruction in the instruction blocking register, and the vector instruction is the vector instruction that has just been received. If the required source operation data is being written back, the data can be read through the data bypass in the vector register module, otherwise the instruction is saved in the vector instruction register, the same as (2) below. (2) For the vector instruction that is saved in the instruction blocking register, after the dependency is resolved, it is necessary to read the operand from the vector register module again. If the data is being written back, the data can be read through the data bypass in the vector register module, otherwise the value in the vector register module is read.

[0050] Write-back mode, for vector instructions that write back scalar registers, sequential dispatch, sequential execution, and sequential write-back are adopted. Only one vector instruction that writes back to a scalar register can be executed at a time. This is done to avoid changing the scalar processor as much as possible and to achieve the versatility of the vector processing unit as much as possible. For vector instructions that write back to vector registers, sequential dispatch, out-of-order execution, and out-of-order write-back are adopted. Multiple instruction executions can be supported according to the size of the instruction execution.

[0051] The present invention also provides a RISC-V vector processing unit implementation method, which is based on the RISC-V processor vector extension set and implemented in a coprocessor mode. The vector processing unit includes four ports, namely, a main processor interaction port, a vector instruction request port, a vector instruction feedback port, and a vector instruction memory write port. The vector processing unit includes a three-level pipeline, supports sequential dispatch, out-of-order execution, and out-of-order write back, including decoding and dispatching, execution, write back and delivery, and its instruction fetching and partial decoding are completed in a scalar processor. The decoding and dispatching as the first-level pipeline decode and pipeline conflict judgment of the vector instruction when the vector unit receives the vector instruction of the main processor. If there is no pipeline conflict, it can be dispatched. The execution is used as a second-level pipeline for the execution of vector instructions, including a vector load and store unit (VLSU), a vector integer arithmetic unit (V_INT_ALU), a vector integer multiplication and addition arithmetic unit (V_INT_MAC), a vector floating-point arithmetic unit (V_FP), a vector permutation arithmetic unit (V_PERMUTE), a vector reduction simple element (V_REDUCT) and a vector mask unit (VMASK). The write-back is used as the write-back of the third-stage pipeline for vector instructions, including writing back scalar registers and writing back vector registers.

[0052] Specifically, Figure 1As shown, the decoding unit of the main processor decodes the opcode of the instruction fetched, determines whether it is a vector instruction, and determines whether a scalar source operand and a write-back result to a scalar register are required. If a scalar source operand is required, the general register group is read to read the source operand. If a write-back is required, the main processor stores the index information of the target register in the pipeline control module of the main processor until the write-back is completed. The main processor maintains data dependencies. If the vector instruction has data dependencies with the instruction being executed (including scalar instructions and vector instructions that need to write back to scalar registers), it needs to wait for the data dependency to be contacted before dispatching the vector instruction to the vector processing unit, including the vector instruction req_inst, the values ​​of two scalar source operands (req_rs1, req_rs2) and the vector instruction request signal req_valid.

[0053] The vector processing unit determines whether to receive the vector instruction through the request channel according to the dispatch module (disp_ready) and the pipeline conflict judgment module (pipc_ready) signals. If the vector instruction can be received, req_ready is set to 1 to respond to the vector instruction request signal sent by the main processor. Then the vector instruction is fully decoded in the decoding module, and the instruction format is decoded to determine the execution unit required, and two source operands (if it is a scalar source operand, the scalar source operand sent by the main processor is used, and if the value of the vector register is required, the vector register needs to be read) and the destination operand. The index value (dec_idx) of the vector register to be read is sent to the general port r0 of the vector register, and vrf_rd_r0 is read out, and it is sent to the dispatch module or the vector state control module together with the information dec_info required for instruction execution. According to the RISC-V vector extension instruction encoding, it will be divided into three categories: vector load and store instructions, vector state setting instructions (CSR setting instructions), and vector arithmetic instructions. The vector state setting instructions will be sent directly to the CSR module for execution after decoding, and there is no need to dispatch and check pipeline conflicts in the vector unit, because they do not need to interact with the vector register VRF. Its two source operands and destination operands are scalar register indexes, which have been checked for pipeline conflicts in the main processor. In addition, for these instructions, a write back to the main processor (csr_wbck_dat) can be requested immediately. Before executing the vector setting instruction, it must ensure that the previous instruction is executed or executed before updating the control status register. This operation is implemented in the vector unit by judging whether there is a blocking instruction. When an instruction in the vector unit is blocked, the vector unit does not receive instructions dispatched by the main processor, including CSR instructions. Only when the instruction waiting to be dispatched by the main processor is already executed or executed, can the CSR setting instruction be received and the CSR value be updated, which will not affect the previously executed instructions. The remaining instructions need to be sent to the execution module after decoding through the dispatch module.

[0054] The vector processing unit first sends the vector instruction information (disp_pipc_idx, disp_pipc_info) to the pipeline conflict module in the dispatch module to determine the pipeline conflict. If there is a conflict, the pipeline conflict module sets pipc_o_dep to 1, telling the dispatch module to block the instruction dispatch. If the instruction is a true data dependency, re_rd_rf must also be set to 1. When the pipeline conflict is resolved, the vector register is re-read to obtain the source operand when the instruction is dispatched.

[0055] The vector processing unit compares the vector information sent by the dispatch module with the vector instruction information being executed stored in the internal pipeline conflict judgment to determine whether there is a pipeline conflict. The module generates control signals sel_rd_itag and sel_wbck_itag. Sel_rd_itag is used to select the execution module to occupy the additional read port of the vector register and send the dispatched instruction information to the module that needs to execute the vector instruction. Sel_wbck_itag is used to control writeback.

[0056] The execution module receives the vector instruction information (disp_exu_idx, disp_exu_info, disp_exu_dat) from the dispatch module, and reads the vector state data csr_exu_dat of the current vector control state module, and sends it to the execution module of the vector instruction according to sel_rd_itag for execution, and finally outputs the write-back data. The vector load and store unit is responsible for the vector unit accessing the memory inside the scalar processor. The execution of the vector load instruction requires setting memory_read_ready and memory_read to 1, sending the required address information memory_addr and the read element size memory_size. After receiving the vector read access memory, the scalar processor will generate memory_read_valid and send the required read data memory_read_dat to the vector load and store unit. The execution of vector storage instructions requires setting memory_write_valid to 1 and memory_read to 0, sending the required address information memory_addr and the element size memory_size to be written. After receiving the vector read access memory, the scalar processor will generate memory_read_ready and send the required data memory_write_dat to the memory of the main processor. For the vector load and store unit, the load instruction and the store instruction cannot be executed at the same time. Unlike other execution units, each execution reads or writes a vector element size instead of a vector register width VLEN, but for the vector module (load instruction), the write back is a VLEN write back. Each vector element loaded is placed in a register of length VLEN until it is full or finished and read out and written back. Other executions include vector integer arithmetic unit, vector integer multiplication and addition arithmetic unit, vector floating-point arithmetic unit, vector permutation arithmetic unit, and vector reduction arithmetic unit. The vector integer arithmetic unit is responsible for the vector integer addition, subtraction, multiplication and division arithmetic instructions, and the vector integer multiplication and addition arithmetic unit is responsible for the vector integer multiplication and addition arithmetic instructions. The vector floating-point arithmetic unit is responsible for the vector floating-point instruction operation. The vector permutation unit is responsible for the execution of vector permutation instructions. The vector reduction unit is responsible for the instructions of vector reduction instructions. The vector mask unit is responsible for the execution of vector mask instructions. The vector execution module is designed with SIMD pipeline design, including read / write unit, function unit, and data processing unit. The read / write unit is designed with a state machine, which is divided into two states: 0 and 1. When the state machine is in state 0, it waits for the enable signal of the execution unit. If the vector instruction selects the execution unit, an enable signal will be generated. If there is an enable signal, it will jump to state 1.Write operation, 0 state, save the instruction information (disp_exu_info), index information (disp_exu_idx) and csr_data of the execution instruction sent by the first dispatch module in the internal register, 1 state, save the next operand to be read in the register. Read operation, determine whether to read the next operand according to the value of csr and the instruction, read the next operand through the register extra port r1 or r2. When the state machine is in state 1, it will determine whether the instruction execution is completed. If it continues to execute, it will maintain state 1, and if it ends, it will jump to state 0. The functional unit is equivalent to ALU, which is responsible for the instruction instruction. The data processing unit processes the output data of the functional unit to obtain the final write-back data.

[0057] Through the vector write back and delivery module, the output data of each functional unit of the execution module (vlsu_o, v_int_alu_o, v_int_mac_o, v_fp_o, v_permute_o, v_reduct_o, vmask_o) are divided into write back scalar registers (wbck_rd) and write back vector registers (wbck_vd) according to the write back method. Since the instructions to write back the scalar registers are written back sequentially, they can be directly written back to the scalar processor through the feedback channel of the vector processing unit and delivered by the scalar processor. For vector instructions that write back vector registers, they can generally be written back directly. However, when two instructions executed simultaneously need to be written back at the same time, arbitration is required according to their dispatch order sel_wbck_itag. The first dispatched instruction is written back first. In order not to block the pipeline, the data written back by the instruction dispatched later is cached in the FIFO, waiting for the first dispatched instruction to be written back or if there is no data to be written back, the data is read out from the FIFO and written back. When the vector instruction is written back, wbck_sign will be generated, and the pipeline conflict module will then determine whether the instruction is completed based on the status information exu_status of each module. If completed, the instruction information in the instruction save register is canceled, and the delivery of the instruction is completed.

[0058] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments including components are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A method for implementing a RISC-V vector processing unit, characterized in that: The steps include: S1, vector instruction preparation stage, executed in the scalar processor, fetch vector instructions, perform simple decoding on the vector instructions, determine whether a scalar source operand is required, read the scalar register, and the scalar processor FIFO, determine the scalar data correlation, and if it can be dispatched, save the vector instruction destination register index information that needs to be written back to the scalar register in the scalar processor FIFO, and generate a vector instruction request signal, waiting for the vector processing unit to respond; S2, vector instruction decoding and dispatching stage, judging whether to respond to the main processor vector request signal according to the vector unit's own state; S3, vector instruction execution stage, this stage is used to execute vector instructions, and indirectly realize the execution of all elements in the register group through multiple cycle execution. The total bit width of each element is VLEN bits, that is, the length of a vector register. Each execution unit adopts pipeline design, that is, SIMD pipeline; S4, vector instruction write back and delivery stage, vector instructions write back to scalar registers and write back to vector registers, the vector written back to the scalar register needs to generate feedback information to the scalar processor through the vector instruction feedback port, and wait for the scalar processor to respond. It can be directly written back to the scalar processor through the feedback port of the vector processing unit, and the instruction information saved in the scalar processor is removed, completing the delivery of the instruction. The vector instruction written back to the vector register is directly written back to the vector register through arbitration and the information saved in the dispatch stage is removed to complete the delivery of the vector instruction.

2. A RISC-V vector processing unit implementation method according to claim 1, characterized in that: In step S2, if a response is received, the vector instruction and the scalar source operand are received, and then the vector instruction is fully decoded, the format of the instruction is decoded and the vector register is read, and pipeline conflicts are determined to determine whether to dispatch the vector instruction.

3. A RISC-V vector processing unit implementation method according to claim 1, characterized in that: In step S3, the execution unit includes a read-write unit, a functional unit, and a data processing unit. The read-write unit is used to read and write source operands, the functional unit is used to execute the operations to be performed by the instruction, and the data processing unit processes the data of the functional unit to obtain the data to be written back.

4. A RISC-V vector processing unit implementation method according to claim 2, characterized in that: The pipeline conflicts include data conflicts and resource conflicts.

5. A RISC-V vector processing unit implementation method according to claim 2, characterized in that: The determination of the pipeline conflict includes: For resource conflicts, read-after-write dependencies, and write-after-write dependencies, the solution is: block the currently dispatched instruction until the resource conflict is resolved; For the write-before-read dependency and true data dependency, the solution is: Method (1) There is no instruction in the instruction blocking register, and the vector instruction is a vector instruction that has just been received. If the required source operation data is being written back, the data can be read through the data bypass in the vector register module, otherwise the instruction is saved in the vector instruction register, which is the same as the following method (2); Method (2) For the vector instruction that is a vector instruction saved in the instruction blocking register, after the dependency is released, it is necessary to read the operand from the vector register module again. If the data is being written back, the data can be read through the data bypass in the vector register module, otherwise the value in the vector register module is read; Write-back mode: For vector instructions that write back scalar registers, sequential dispatch, sequential execution, and sequential write-back are adopted. Only one vector instruction that writes back scalar registers can be executed at a time. For vector instructions that write back vector registers, sequential dispatch, out-of-order execution, and out-of-order write-back are adopted. Multiple instruction execution is supported according to the size of the instruction execution.

6. A RISC-V vector processing unit implementation device, the device is used to implement the method according to any one of claims 1 to 5, characterized in that: include: The vector instruction decoding module decodes the vector instruction encoding rules of the RISC-V vector extension standard document 1.0 to generate different instruction type information and operand register index information; A vector instruction dispatch module is used to dispatch vector instructions. It uses an instruction blocking register group to save vector instruction information that has pipeline conflicts in the vector unit after the scalar processor releases data dependencies. It receives instruction information from the vector decoding module and sends it to the vector pipeline judgment module to determine whether there is a pipeline conflict. If not, the vector instruction can be dispatched. If there is a pipeline conflict, the vector instruction is blocked. The decoding information of the vector instruction and the operand read from the vector register are saved in the instruction blocking register group. The pipeline conflict is waited for to be resolved, and the instruction is dispatched and the value saved in the instruction blocking register is removed. Vector pipeline conflict judgment module, this module is used to judge pipeline conflict and vector instruction delivery, use an instruction execution register group to save the information of the vector instruction being executed and the order of executing instructions, when receiving the vector instruction information that needs to be dispatched by the dispatch module, it is judged whether a pipeline conflict occurs with the vector instruction being executed, when there is a pipeline conflict, it generates a signal that cannot be dispatched to the dispatch module, when there is no pipeline conflict, it generates a signal that can be dispatched to the dispatch module, and saves the instruction information and execution order in the instruction execution register group; vector instruction delivery, when receiving the signal from the end of the vector instruction, it will remove the instruction information saved in the instruction execution register group, that is, complete the delivery of the instruction; The vector register module includes multiple read register port groups, a general register port group, an additional read register port group required for executing multiple instructions at the same time, and a write-back port group. The read register port group includes four read ports, and the write-back port group includes two write-back ports. It contains 32 general registers of VLEN length. The read port logic generally reads data according to the input register index value, but a data bypass is added at the read port. When the register index of the write-back data is the same as the source operand index to be read, it is directly sent to the output port instead of reading the register value. The write port logic generally uses one write-back port to write back vector instructions. The additional write-back port is for writing back double-width instructions. Since the register index differs by 1, it will not cause the same register file to be written. It is only necessary to judge that the register index values ​​are different in the write-back logic. The vector control status register module is added and designed according to the RISC-V vector extension standard document, which is used to execute vector control status configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output the tasks performed by the vector control status register module to the execution unit; A vector execution module, divided into a vector load and store unit, a vector integer operation unit, a vector integer multiply-add operation unit, a vector floating-point operation unit, a vector permute operation unit, a vector reduction unit and a vector mask unit according to the vector instruction type; The vector write-back module includes a write-back scalar register module and a write-back vector register module.

7. A RISC-V vector processing unit implementation device according to claim 6, characterized in that: In the vector execution module: the vector integer operation unit is responsible for the operation instructions of vector integer addition, subtraction, multiplication and division, and the vector integer multiplication and addition operation unit is responsible for the operation instructions of vector integer multiplication and addition; the vector floating-point operation unit is responsible for the operation of vector floating-point instructions, and the vector permutation operation unit is responsible for the execution of vector permutation instructions; the vector reduction element is responsible for the instructions of vector reduction instructions; the vector mask unit is responsible for the execution of vector mask instructions; the vector execution module adopts SIMD pipeline design, including a read-write unit, a functional unit, and a data processing unit. The read-write unit is designed with a state machine and is divided into two states, 0 and 1. When the state machine is in state 0, it waits for the execution unit enable signal. If the vector instruction selects the execution unit, an enable signal will be generated, and if there is an enable signal, it will jump to state 1; write operation, the instruction information to be operated by the execution instruction is saved in the internal register, and the instruction information includes register index, vector length, vector element width, and operation object; For read operations, it is determined whether the next operand needs to be read based on the vector length. When the state machine is in state 1, it determines whether the instruction execution is completed. If it continues to execute, it maintains state 1. If it is completed, it jumps to state 0. The functional unit is equivalent to a SIMD execution unit and can support the execution of multiple vector elements with different bit widths. The maximum execution element bit width is VLEN. The data processing unit processes the output data of the functional unit to obtain the final write-back data.

8. A RISC-V vector processing unit implementation device according to claim 6, characterized in that: In the vector write-back module: if the current vector instruction needs to be written back to the scalar register, it is directly written back through the feedback port of the vector processing unit. If the vector instruction needs to be written back to the vector register, it can be directly written back when only one instruction is executed. When two instructions executed simultaneously need to be written back, they are arbitrated according to the execution instruction order saved in the instruction execution register group. The first one dispatched can be written back first, and the write-back data of the later one dispatched can be saved in its corresponding FIFO until there is no data to write back, which is read from the FIFO and written back to the vector register. After the instruction execution is completed, the instruction execution register will determine whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located. If completed, the instruction information is removed to complete the delivery.

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