Apparatus, system, and method for programming data in a non-volatile memory device

Abstract

This application relates to apparatus, systems, and methods of programming data in a non-volatile memory device. A memory device includes a cell group and a control circuit. The cell group includes a plurality of non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plurality of non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plurality of non-volatile memory cells and a verify operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit to detect whether a threshold voltage distribution of the plurality of non-volatile memory cells satisfies a reference in a particular program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plurality of non-volatile memory cells in a next program loop after the particular program loop.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the disclosure described herein relate to a memory device, and more particularly, to an apparatus and method for programming data in a non-volatile memory device. BACKGROUND

[0002] A data processing system includes a memory system or a data storage device. The data processing system can be developed to store more mass data in the data storage device, store data in the data storage device faster, and read data stored in the data storage device faster. The memory system or the data storage device can include a non-volatile memory cell and / or a volatile memory cell for storing data. SUMMARY

[0003] Embodiments of the disclosure can provide an apparatus and method capable of improving a data input / output speed of a memory device.

[0004] Embodiments of the disclosure can reduce the number of verify operations and / or time taken for the verify operations by checking a threshold voltage distribution of a non-volatile memory cell using a current sensing circuit (CSC) during a process of programming data in a memory device.

[0005] In a memory device according to embodiments of the disclosure, an operation burden of a verify operation can be reduced, thereby reducing a wear of a non-volatile memory cell included in the memory device and interference between adjacent or neighboring memory cells. Accordingly, data security of the memory device can be improved or enhanced.

[0006] Further, in a memory device according to embodiments of the disclosure, even if an operation burden caused by a verify operation with respect to a plurality of non-volatile memory cells is reduced for each memory cell storing multi-bit data, a width of a threshold voltage distribution of the non-volatile memory cell can be narrowed.

[0007] In an embodiment, a memory device can include a cell group including a plurality of non-volatile memory cells capable of storing data, and a control circuit configured to: perform a program operation for programming data in the plurality of non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plurality of non-volatile memory cells and a verify operation for verifying a result of the unit program operation; use a current detection circuit to detect whether a threshold voltage distribution of the plurality of non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops, and terminate the program operation after applying a preset program pulse to the plurality of non-volatile memory cells in a next program loop after the specific program loop.

[0008] The control circuit can be configured to perform, in some of the plurality of program loops, an inspection operation for identifying a threshold voltage distribution at a time between a unit program operation and a verify operation.

[0009] The inspection operation can include establishing a comparison voltage having a level lower than a preset level corresponding to a program value targeted as the program operation, counting a number of nonvolatile memory cells having a threshold voltage having a level lower than the comparison voltage, and comparing the counted number with a reference.

[0010] The comparison voltage can have a level within a first range or within a second range, the first range being between the preset level and a level corresponding to another closest program value lower than the preset level, the second range being between the preset level and a level obtained by subtracting a degree of change in the threshold voltage by the second program mode from the preset level.

[0011] The inspection operation can inspect a threshold voltage distribution of the plurality of nonvolatile memory cells with respect to a plurality of program values corresponding to the program operation.

[0012] The unit program operation can be performed in a mode selected among a first mode, a second mode, and a third mode, the first mode being to apply a second program pulse to change or adjust a threshold voltage of the at least one nonvolatile memory cell by a first level equal to or greater than a change level of the threshold voltage caused by the first program pulse, the second mode being to apply the second program pulse to change or adjust the threshold voltage of the at least one nonvolatile memory cell by a second level smaller than the change level caused by the first program pulse, and the third mode being to apply the second program pulse to the at least one nonvolatile memory cell whose threshold voltage is prohibited from being changed.

[0013] The control circuit can be configured to change a value stored in a latch included in a page buffer coupled to a bit line coupled to the plurality of nonvolatile memory cells in response to the mode selected among the first mode, the second mode, and the third mode.

[0014] The control circuit can store a value "0" in a first latch for the unit program operation performed in the first mode, store a value "0" in a second latch for the unit program operation performed in the second mode and change the value "0" in the second latch to a value "1" at timing of turning on a transistor midway of the bit line and the page buffer, and store a value "1" in a third latch for the unit program operation performed in the third mode.

[0015] The control circuit can skip the verify operation of the certain program loop when the threshold voltage distribution satisfies the reference, and perform a next program loop with the second mode or the third mode.

[0016] The control circuit can apply a verification voltage to multiple non-volatile memory cells to check whether data has been programmed into the multiple non-volatile memory cells. The verification voltage corresponds to multiple programming values ​​that are the target of the programming operation.

[0017] The control circuit can determine the first, second, or third mode to be executed in the next programming cycle in response to the result of the verification operation.

[0018] In another embodiment, the memory system may include: a memory device configured to: perform programming operations for programming data into a plurality of non-volatile memory cells through a plurality of programming cycles, each programming cycle including a unit programming operation for applying a programming pulse to the plurality of non-volatile memory cells and a verification operation for verifying the result of the unit programming operation; using a current detection circuit to detect whether the threshold voltage distribution of the plurality of non-volatile memory cells meets a reference in a particular programming cycle of the plurality of programming cycles, and terminating the programming operation after applying a preset programming pulse to the plurality of non-volatile memory cells in the next programming cycle after the particular programming cycle; and a controller configured to send programming commands to the memory device and indicate the addresses of the plurality of non-volatile memory cells.

[0019] A memory device may include at least one memory wafer or at least one memory plane.

[0020] The memory device can be configured to perform a check operation for identifying the threshold voltage distribution in some of the programming cycles within a unit programming operation and a verification operation.

[0021] The inspection operation may include establishing a comparison voltage with a level lower than a preset level corresponding to the programming value as the target of the programming operation, counting the number of non-volatile memory cells with a level lower than a threshold voltage of the comparison voltage, and comparing the count with a reference.

[0022] The unit programming operation can be performed in a mode selected from a first mode, a second mode, and a third mode. The first mode is to apply a second programming pulse to change or adjust a first level of the threshold voltage of at least one non-volatile memory cell, the first level being equal to or greater than the change level of the threshold voltage caused by the first programming pulse. The second mode is to apply a second programming pulse to change or adjust a second level of the threshold voltage of at least one non-volatile memory cell, the second level being less than the change level caused by the first programming pulse. The third mode is to apply a second programming pulse to at least one non-volatile memory cell whose threshold voltage is prohibited from being changed.

[0023] The memory device can skip the verification operation of a specific programming cycle when the threshold voltage distribution meets the reference, and execute the next programming cycle in a second or third mode.

[0024] The memory device can determine the first, second, or third mode to be executed in the next programming cycle in response to the result of the verification operation.

[0025] In another embodiment, a method for operating a memory system may include: receiving a programming command, programming data, and location information therein where the data is to be stored; controlling bit lines connected to a plurality of non-volatile memory cells corresponding to the location information in response to the programming data, and applying programming pulses to word lines connected to the plurality of non-volatile memory cells; checking whether the threshold voltage distribution of the plurality of non-volatile memory cells meets a reference via a current detection circuit; and when the threshold voltage distribution meets the reference, skipping the verification operation of the plurality of non-volatile memory cells and performing a second programming mode on some of the plurality of non-volatile memory cells.

[0026] The method may further include: performing a verification operation on multiple non-volatile memory cells when the threshold voltage distribution does not meet the reference; and determining, based on the result of the verification operation, a programming mode to be performed on the multiple non-volatile memory cells from among the first programming mode, the second programming mode, and the third programming mode.

[0027] In another embodiment, the memory device may include: memory cells coupled to word lines; and control circuitry configured to execute a programming cycle, each including a programming pulse operation that applies a programming pulse to the word line. Each programming cycle, except the last programming cycle, further includes a check operation that applies a check voltage to the word line to identify the number of active cells based on the check voltage. When the number is greater than a reference, each programming cycle selectively includes a verification operation that verifies the programming pulse operation. When the number is less than a reference, the control circuitry executes the final programming cycle to program the memory cells according to a dual-verification programming (DPGM) mode. Attached Figure Description

[0028] The description herein refers to the accompanying drawings, in which similar reference numerals refer to similar parts throughout the drawings.

[0029] Figure 1 A memory device according to an embodiment of the present disclosure is illustrated.

[0030] Figure 2 A data processing system according to an embodiment of the present disclosure is illustrated.

[0031] Figure 3A and Figure 3BAn incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0032] Figure 4 A method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0033] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0034] Figure 6 The programming and verification operations of an incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure are illustrated.

[0035] Figure 7 The target level corresponding to a plurality of programming pulses according to an embodiment of the present disclosure is illustrated.

[0036] Figure 8 Programming operations according to embodiments of the present disclosure are illustrated.

[0037] Figure 9 Another incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0038] Figure 10 The relationship between the results of a current sensing circuit (CSC) in a memory device according to an embodiment of the present disclosure and the threshold voltage distribution is illustrated.

[0039] Figure 11 An example of a memory device for performing programming operations according to an embodiment of the present disclosure is shown.

[0040] Figure 12 An example of a current sensing circuit (CSC) according to an embodiment of the present disclosure is illustrated.

[0041] Figure 13 A method for operating a memory device according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0042] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0043] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not necessarily be combined in the same embodiment.

[0044] In this disclosure, the terms “comprising,” “including,” “containing,” and “included in” are open-ended. As used in the appended claims, these terms specify the presence of the mentioned element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0045] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured" to perform multiple tasks. In this context, "configured as" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component can be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not opened or not activated). Blocks / units / circuit / components used with the language "configured as" include hardware, such as circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured as" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the tasks in question. "Configured as" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0046] As used in this disclosure, the term "circuit" or "logic" means all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only), and (b) a combination of circuits and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions, and (c) circuits such as a microprocessor or a portion of a microprocessor that require software or firmware (even if the software or firmware is not physically present) to function. This definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claim). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of processors (or processors) only, or portions of processors, and their accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example, and if applicable to a particular claim element, an integrated circuit for a storage device.

[0047] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must precede the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0048] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, a determination may be based solely on those factors, or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely on B.

[0049] Here, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one implementation, a data item may include discrete objects. According to another implementation, a data item may include information units within a transmission packet between two different components.

[0050] The embodiments of this disclosure described herein provide a data processing system and a method for operating the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the usage of the components and resources.

[0051] The embodiments will now be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0052] Figure 1 An example of a memory device 150 including a memory cell array circuit formed in a memory chip is illustrated according to an embodiment of the present disclosure.

[0053] Reference Figure 1 The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1 connected to corresponding bit lines of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are disposed in respective columns of the memory bank 330, and each cell string 340 may include at least one drain select transistor (DST) and at least one source select transistor (or string select transistor (SST) SST. The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the non-volatile memory cells MC0 to MCn-1 may be configured to store a multi-level cell (MLC) with a data item having a plurality of bits per cell. The cell string 340 may be electrically connected to the corresponding bit lines of the bit lines BL0 to BLm-1.

[0054] In one embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as NOR flash memory, hybrid flash memory containing at least two different types of memory cells, or single-chip NAND flash memory in which the controller is embedded in a single memory chip. In another embodiment, memory group 330 may include flash memory cells including a charge trapping flash (CTF) layer comprising a conductive floating gate or an insulating layer.

[0055] Figure 2A memory system 110, which may include a memory device 150, is illustrated according to an embodiment of the present disclosure. In this embodiment, the memory group 330 in the memory device 150 may include one or more memory blocks 152, 154, 156. According to the embodiment, the memory device 150 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure, such as a vertical structure. Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first direction to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0056] Memory bank 330, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple string select lines (or source select lines) SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL (not shown), and multiple common source lines CSL. In an embodiment, memory bank 330 may include multiple NAND strings NS, for example, multiple NAND strings NS may each correspond to a cell string 340. Each NAND string NS may include multiple memory cells MC and can be connected to corresponding bit lines in the bit lines BL. Additionally, the string select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to the corresponding bit line BL. In each NAND string NS, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST.

[0057] Reference Figure 1 and Figure 2 The memory device 150 may include a voltage supply circuit 170, which supplies word line voltages (e.g., one or more predetermined voltages such as programming voltage, read voltage, and pass voltage) to corresponding word lines in the word lines according to an operating mode, or supplies voltage to the body portion (e.g., a well region) in which each memory block comprising memory cells MC is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of the control circuit 180. Additionally, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other.

[0058] In response to control by the control circuitry, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied separately to the selected word line and the unselected word line. The voltage supply circuitry 170 may include a voltage generation circuitry for generating target voltages with various levels (e.g., see reference 170). Figures 4 to 8 ).

[0059] In one embodiment, the voltage supply circuit 170 may be connected to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. The second power supply voltage VPP may have a voltage level higher than the first power supply voltage VCC (e.g., twice or more). For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V.

[0060] According to one embodiment, the voltage supply circuit 170 may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory bank 330. The voltage generation circuit may use a second power supply voltage VPP to generate the target voltage, which may have a voltage level higher than that of the second power supply voltage VPP.

[0061] The memory device 150 may further include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 may operate as a read amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 may operate as a read amplifier for reading data items from the memory cell array. In programming operations, the read / write circuit 320 may operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed into the cell array from a page buffer during programming operations. The read / write circuit 320 may drive bit lines based on the input data items. For this purpose, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column or each bit line, or each column pair or each bit line pair. According to an embodiment, each of the page buffers 322, 324, 326 may include a plurality of latches.

[0062] Page buffers 322, 324, and 326 can be connected to data input / output devices, such as serialization circuits or serializers, via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential delays in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without waiting time.

[0063] According to an embodiment, the memory device 150 can receive a write command, write data, and information about the location where the write data is to be stored, such as a physical address. The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., used for programming operations performed in response to the write command, and to generate one or more voltages used for verification operations performed after the programming operation.

[0064] When programming multiple data items into the non-volatile memory cells included in memory bank 330, the error rate may be higher than when storing a single data item in a non-volatile memory cell. For example, errors in non-volatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data items stored between non-volatile memory cells should be reduced.

[0065] To this end, the memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively narrow the threshold voltage distribution of the non-volatile memory cells. In one embodiment, the memory device 150 can use the ISPP operation for multi-step programming operations. For example, the memory device 150 can divide the programming operation into least significant bit (LSB) programming operations and most significant bit (MSB) operations according to a predetermined order between non-volatile memory cells or pages.

[0066] According to embodiments, an apparatus and method can be provided that reduces the time used to discharge bit lines or channels between programming pulse applications during data programming operations performed by applying multiple programming pulses to memory cells in a memory device. When the discharge time can be reduced, the speed of programming operations on the memory device can be increased. For example, to discharge bit lines or channels in the memory device, the memory device can control or adjust the voltage level of the bit line select line or drain select line (DSL) to prevent transistors from being in a floating state when controlled by the bit line select line or drain select line (DSL). Because the transistors may be in a floating state, the bit lines or channels cannot be properly discharged.

[0067] In an embodiment, the memory device can adjust and change the setup time for adjusting the bit line potential after the programming pulse is applied during a single programming operation of applying a programming pulse to a non-volatile memory cell in the memory device. As a result, apparatus and methods capable of improving the speed and / or efficiency of programming operations can be provided.

[0068] For example, during the operation of applying multiple programming pulses to a non-volatile memory cell in a memory device to program the non-volatile memory cell with multiple bits of data, the memory device can perform a unit programming operation in one of a variety of modes in which a second programming pulse is applied after a first programming pulse has been applied.

[0069] The programming operation modes can include a first programming mode, a second programming mode, and a third programming mode. In the first programming mode, the degree to which data is programmed in response to a second programming pulse (e.g., a change or shift in the threshold voltage of the non-volatile memory cell when the second programming pulse is applied) can be similar to or greater than the degree to which data is programmed in response to a first programming pulse. In the second programming mode, the degree to which data is programmed in response to a second programming pulse is less than the degree to which data is programmed in response to a first programming pulse. In the third programming mode, there is no degree to which data is programmed in response to a second programming pulse; for example, even when the second programming pulse is applied, the threshold voltage of the non-volatile memory cell does not change or shift. This mode can be implemented based on the potential of the bit line connected to the target memory cell when the programming pulse is applied. If the discharge time can be reduced, the memory device can improve the efficiency or speed of data programming operations by adjusting and changing the setup time used to change the bit line potential or to discharge the bit line potential.

[0070] According to an implementation, the memory device can change or adjust the control voltage applied via the bit line select line or drain select line (DSL) in response to the programming operating environment (e.g., temperature) and regarding the number or level (or magnitude) of programming pulses applied to the non-volatile memory cells during data programming operations. Therefore, the memory device can reduce the operating margin corresponding to each programming pulse during data programming operations by applying multiple programming pulses to the non-volatile memory cells. This can reduce the time spent performing data programming operations.

[0071] Refer again Figure 2 The memory device 150 is shown as being included in the data processing system 100. According to an embodiment, the data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as memory system 110. For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0072] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 may be considered as physically separate components or elements. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a path.

[0073] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented on a single chip or on multiple chips. The controller 130 may perform data input / output operations in response to a request from an external device. For example, when the controller 130 performs a read operation in response to a read request from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0074] exist Figure 2 In this configuration, memory device 150 may include one or more memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together in a single erase operation. Memory blocks 152, 154, and 156 may include at least one page, for example, a group of non-volatile memory cells that store data together during a single programming operation and / or output data together during a single read operation. For example, a memory block may include multiple pages.

[0075] In an embodiment, the memory device 150 may include a plurality of memory planes or one or more memory chips. According to an embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, a drive circuit capable of controlling an array of a plurality of non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0076] According to an implementation, each memory chip may include at least one memory plane and can be understood as a collection of components implemented on a physically separable substrate. Each memory chip can be connected to the controller 130 via a data path and may include an interface for exchanging data items and signals with the controller 130.

[0077] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory chip. The internal structure of the memory device 150 (e.g., Figure 1 (As shown) may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to...Figure 1 The internal structure is shown.

[0078] exist Figure 2 In this context, memory device 150 includes a voltage supply circuit 170 capable of supplying one or more voltages to memory blocks 152, 154, and 156. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages for memory blocks 152, 154, and 156, for example, as shown in reference... Figures 4 to 8 As described.

[0079] In this implementation, the voltage supply circuit 170 can supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the programming voltage Vprog to the selected non-volatile memory cell. During a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 can supply the pass voltage Vpass to the unselected non-volatile memory cell. During the erase operation used to erase data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, voltage supply circuit 170 can supply an erase voltage Vers to the memory blocks.

[0080] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on which operation is performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd can be used to identify or read multiple data items. Memory device 150 may include a table having information indicating multiple levels of read voltage Vrd corresponding to multiple data items. For example, the table may include bias values ​​stored in a register, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​for read voltage Vrd used for read operations may be limited to a predetermined range. Furthermore, in one embodiment, the bias values ​​may be quantized.

[0081] The host 102 may include a portable electronic device (e.g., a mobile phone, MP3 player, laptop, etc.) or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). According to an embodiment, the host 102 may include the central processing unit (CPU) found in both portable and non-portable electronic devices.

[0082] Host 102 may include at least one operating system (OS) capable of controlling the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operationally coupled to memory system 110, and users who wish to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further classified as personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to ensure and support high-performance computing.

[0083] The mobile operating system may include services or features that support mobility (e.g., power-saving features). Host 102 may include multiple operating systems. In response to a user request, host 102 may execute multiple operating systems interlocked with memory system 110. Host 102 may send multiple commands corresponding to the user request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0084] The controller 130 can control the memory device 150 in response to requests or commands from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or programming operation) to store data input from the host 102 into the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0085] According to an implementation, the controller 130 may include a host interface (I / F) 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. For example... Figure 2 The components in the controller 130 shown can vary depending on the structure, function, and operational performance of the memory system 110.

[0086] For example, memory system 110 can be implemented using any of a variety of storage devices (electrically connected to host 102) according to the host interface protocol. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini-SDs, micro-SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of memory system 110, components can be added to or omitted from controller 130.

[0087] Each of the host 102 and the memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 may include devices capable of sending signals, data, etc. to or receiving signals, data, etc. from the host 102.

[0088] Host interface 132 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can send and receive data between them using predetermined protocols. Examples of communication standards or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, host interface 132 is a layer for exchanging data with host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0089] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be classified as master and slave using the positions or DIP switches to which they are connected. The memory system 110 set as master can be used as the primary memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0090] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronic Devices (IDE) devices. The 40 wires in an IDE interface can be reduced to 6 wires in a SATA interface. For example, the 40 parallel signals of IDE can be converted into 6 serial signals in a SATA interface. The SATA interface has been widely used because it offers faster data transmission and reception rates and consumes fewer resources in the host 102 used for data transmission and reception. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. Furthermore, the SATA interface supports hot-plugging, which allows external devices to be attached to or detached from the host 102 even while data communication between the host 102 and another device is in progress. Therefore, the memory system 110 can be connected or disconnected as an attachment device (such as a device supported by Universal Serial Bus (USB)) even when the host 102 is powered on. For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0091] The Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in the host 102.

[0092] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. Furthermore, SAS can support the connection between the host 102 and peripheral devices using serial cables instead of parallel cables, making it easier to manage equipment using SAS and enhancing operational reliability and communication performance. Additionally, SAS can support connections from up to eight external devices to a single transceiver included in the host 102.

[0093] High-speed non-volatile memory (NVMe) is an interface based at least on the High-Speed ​​Peripheral Component Interconnect (PCIe), which is designed to increase the performance and design flexibility of hosts 102, servers, computing devices, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one line (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths of tens to hundreds of gigabits per second. NVMe can support faster operating speeds than hard drives for non-volatile memory systems 110 (such as SSDs).

[0094] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be coupled to a single transceiver included in host 102.

[0095] Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to generate encoded data with parity bits added. The encoded data can be stored in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs an indication signal, such as a correction success signal or a correction failure signal, based on the result of error correction decoding. Error correction circuit 138 can use parity bits generated during the ECC encoding process for data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may not correct the erroneous bits but instead may output a correction failure signal indicating that the error bit correction failed.

[0096] According to an implementation, the error correction circuit 138 can perform error correction operations based on coded modulation. Examples include low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above codes. In an implementation, the error correction circuit 138 may include... Figure 2 At least some of the components in the controller 130 shown.

[0097] The ECC decoder can perform either hard-decision decoding or soft-decision decoding on data sent from memory device 150. Hard-decision decoding can be understood as one of two methods broadly classified for error correction. Hard-decision decoding may include, for example, correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft-decision decoding.

[0098] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantized values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values ​​as a combination of information such as conditional probability or likelihood.

[0099] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes, which are part of a method designed for soft-decision decoding. Low-Density Parity-Generator (LDPC) codes use an algorithm that reads data values ​​from memory device 150 bit by bit based on reliability, rather than simply reading 1 or 0 data as in hard-decision decoding, and iteratively repeats this algorithm through message exchange to improve the reliability of the values. These values ​​are then ultimately determined to be 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from a non-volatile memory cell is decoded as 0 or 1.

[0100] Compared to hard-decision decoding, soft-decision decoding can determine the value stored in a non-volatile memory cell based on random information. Regarding bit flips that can be considered errors that may occur in memory device 150, soft-decision decoding can provide an improved probability of correcting errors and recovering data, and provides the reliability and stability of the corrected data. LDPC-GM codes can have schemes in which the internal low-density generator matrix (LDGM) code can be cascaded with high-speed LDPC codes.

[0101] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can correspond to schemes using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0102] According to the implementation, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a nonlinear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes (e.g., Hamming codes), and the decoding is repeated in both the row and column directions to improve the reliability of the values.

[0103] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, such as the voltage supplied to the controller 130, and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of its current state when the power supply to the memory system 110 is unstable. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0104] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so as to allow the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0105] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0106] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), a toggle mode, etc., for data input / output with the memory device 150. For example, ONFi may use a data path, such as a channel, path, etc., that includes at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0107] The memory 144 can serve as working memory for either the memory system 110 or the controller 130, while simultaneously temporarily storing transaction data for operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data that has been output from the memory device 150 in response to a read request from the host 102 before it is output to the host 102.

[0108] Additionally, the controller 130 can temporarily store write data in the memory 144 before programming write data input from the host 102 into the memory device 150. When the controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of the memory device 150, data transferred between the controller 130 and the memory device 150 of the memory system 110 can be temporarily stored in the memory 144.

[0109] In addition to reading or writing data, memory 144 may also store information for inputting or outputting data between host 102 and memory device 150, such as mapped data, read requests, programming requests, etc. According to embodiments, memory 144 may include one or more of a command queue, programming memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0110] In implementations, memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 The example illustrates that memory 144 is located within controller 130, but the implementation is not limited thereto. Memory 144 may be located inside or outside controller 130. For example, memory 144 may be implemented by an external volatile memory having a memory interface for transferring data and / or signals between memory 144 and controller 130.

[0111] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. The firmware may be, for example, a flash translation layer (FTL). According to embodiments, processor 134 can be implemented using a microprocessor, a central processing unit (CPU), or another processing device.

[0112] According to one embodiment, the memory system 110 can be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, considered to be distinct processing regions, are integrated. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to one embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0113] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent as setting commands from the host 102 can be considered foreground operations. Examples of background operations that can be performed without commands sent from the host 102 include the controller 130 performing garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0114] According to the implementation, both foreground and background operations can be performed with substantially similar operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102.

[0115] When the memory device 150 includes multiple wafers (or multiple chips), each containing multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups including at least some of the multiple planes, multiple wafers, or multiple chips included in the memory device 150, and the multiple groups of requests or commands can be processed individually or in parallel in each plane, each wafer, or each chip.

[0116] The memory interface 142 in controller 130 can be connected to multiple wafers or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data across multiple wafers via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel across multiple wafers or planes. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by operating in an interleaving method, the data I / O performance of memory system 110 can be improved.

[0117] By way of example, and not limitation, controller 130 can identify the state of multiple channels (or pathways) associated with multiple wafers included in memory device 150. Controller 130 can determine the state of each channel or pathway as one of busy, ready, active, idle, normal, and abnormal states. The determination by controller 130 regarding which channel or pathway is used to deliver instructions and / or data can be associated with a physical block address. Controller 130 can reference descriptors delivered from memory device 150. A descriptor may include a block or page containing parameters describing certain things about memory device 150. Descriptors may have a predetermined format or structure. For example, descriptors may include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 can refer to or use descriptors to determine which channel or pathway is used to exchange instructions or data.

[0118] As described above, the memory device 150 in the memory system 110 may include one or more memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, the memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0119] In one embodiment, each of the memory blocks 152, 154, and 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple wafers, each wafer including multiple planes, and each plane including memory blocks 152, 154, and 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0120] exist Figure 2 In this embodiment, memory device 150 includes memory blocks 152, 154, and 156. Based on the number of bits that can be stored in a single memory cell, memory blocks 152, 154, and 156 can be any type of memory block, such as a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block. An SLC memory block comprises multiple pages implemented with memory cells that store one bit of data per memory cell. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented with memory cells that store multiple bits of data (e.g., two or more bits of data) per memory cell. Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0121] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented by memory cells capable of storing 2 bits of data per memory cell. A TLC memory block may include multiple pages implemented by memory cells capable of storing 3 bits of data per memory cell. A QLC memory block may include multiple pages implemented by memory cells capable of storing 4 bits of data per memory cell. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented by memory cells capable of storing five or more bits of data per memory cell.

[0122] According to one implementation, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block that stores one bit of data in a memory cell. The data input / output speed of a Multilevel Cell (MLC) memory block can be slower than that of an SLC memory block. For example, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data, because a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0123] According to one embodiment, the controller 130 can program data multiple times in the MLC without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can utilize the characteristic of the MLC to store multiple bits of data to program one bit of data multiple times in the MLC. For an MLC overwrite operation, when programming one bit of data in the MLC, the controller 130 can store the number of programming times as separate operation information. According to one embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before programming another one bit of data in the same MLC where one bit of data has already been stored.

[0124] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory (e.g., NAND flash memory, NOR flash memory, etc.). In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0125] Figure 3A and Figure 3B An incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0126] Reference Figure 3A Data can be programmed into non-volatile memory cells in an erased state. When a programming pulse is supplied to a word line connected to a non-volatile memory cell, the threshold voltage distribution of the non-volatile memory cell can shift to the right (e.g., in the direction of increasing threshold voltage) from the erased state. If programming pulses are supplied continuously to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted to the right. Programming pulses can be supplied until most of the multiple non-volatile memory cells in the threshold voltage distribution have a value higher than the target voltage V. TARG Threshold voltage.

[0127] exist Figure 3B In the process of programming, when the programming operation begins (operation 212), the memory device 150 may apply programming pulses to a plurality of non-volatile memory cells to be programmed (operation 214). After applying the programming pulses, the memory device 150 may verify whether most of the plurality of non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH (Operation 216). When the verification result FAIL (failure) determines that most of the multiple non-volatile memory cells do not have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, memory device 150 applies another programming pulse to the corresponding non-volatile memory cell (operation 214). When it is determined, based on another verification result PASS, that most of the multiple non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, the memory device 150 can end the programming operation (operation 218).

[0128] To narrow the threshold voltage distribution of multiple non-volatile memory cells, it is advantageous to slightly shift the threshold voltage distribution of the multiple non-volatile memory cells to the right by, for example, a first amount, when a single programming pulse is applied, rather than shifting them significantly to the right by, for example, a second amount larger than the first amount. On the other hand, when the threshold voltage distribution of the multiple non-volatile memory cells is slightly shifted to the right, the number of programming pulses applied can be increased.

[0129] According to the implementation, the number of programming pulses applied can be three times or more the number of data bits that can be stored in the non-volatile memory cell. For example, when 2 bits of data can be stored in the non-volatile memory cell, the non-volatile memory cell can have four programming states corresponding to the 2 bits of data, such as "00", "01", "10", and "11". To form a denser threshold voltage distribution, such as a narrower distribution, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts to the right in response to a single programming pulse can be less than the difference between two adjacent programming states. For example, when two or more programming pulses are applied, it can be designed to shift according to the difference between two adjacent programming states. In this case, the number of programming pulses applied can be eight or more, which is more than four times the number of data bits.

[0130] According to the implementation method, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts when a single programming pulse is applied can be understood as the target level. For Figure 6 An example of the implementation method is described in more detail below for the target level.

[0131] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 4 The method may include programming operations performed in a memory device 150 comprising non-volatile memory cells each capable of storing 3 bits of data.

[0132] Data stored in non-volatile memory cells can be based on the threshold voltage V of the corresponding memory cell. TH The threshold voltage V of the memory cell is used to differentiate them. TH The threshold voltage V can vary depending on the number of electrons or charges injected into the floating gate of the corresponding memory cell. A single-level cell (SLC) can be divided into two ranges. TH It stores 1-bit data, either "0" or "1". On the other hand, the three-level cell (TLC) in the memory device 150 can have eight threshold voltage ranges.

[0133] Reference Figure 4To reduce the number of programming pulses applied during Incremental Step Pulse Programming (ISPP) operations, the application of programming pulses to the Level 3 Cell (TLC) in response to the data bits stored in the TLC can be controlled differently. The data stored in the TLC can be divided into LSB data, CSB data, and MSB data. When programming LSB data, the number of programming pulses applied can be minimized, while the number of programming pulses applied when programming CSB data can be greater than that applied when programming LSB data. When programming MSB data, the number of programming pulses applied can be maximized.

[0134] In a three-level cell (TLC) memory device, each physical page can be divided into three logical pages: an LSB page, a CSB page, and an MSB page. The programming pulse applied to each page can be different. For example, different positive threshold voltages (V) can be triggered during the programming of LSB data, CSB data, and MSB data. TH The distribution shifts. In the implementation, the threshold voltage V of multiple non-volatile memory cells. TH The maximum number of cells can be moved during LSB page programming, and the threshold voltage V of multiple non-volatile memory cells is [not specified]. TH Minimal movement is achieved during MSB page programming. According to the implementation, the shortest latency and lowest power consumption are achieved when the number of programming pulses applied during LSB page programming is minimized. Conversely, increasing the number of programming pulses applied during MSB page programming increases latency and power consumption.

[0135] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 5 As an example, the programming operation performed by a memory device 150, which includes a non-volatile memory cell capable of storing 3 bits of data, will be described.

[0136] Reference Figure 5 The memory device 150 may not sequentially divide the operation of storing 3 bits of data in the non-volatile memory cell into LSB programming operation, CSB programming operation, and MSB programming operation. In order to store 3 bits of data in the non-volatile memory cell without separation, the code values ​​of LSB, CSB, and MSB corresponding to the eight programming states can be... Figure 4The differences are shown below. The 3-bit data corresponding to the 8 programming states can be identified as Gray code, and the LSB, CSB, and MSB code values ​​can be set differently. Here, Gray code is a code created to change the value of only one bit between adjacent data when the data changes. For example, the data in the erase state can be understood as "111", while the data in the lowest programming state is "011". The data in the second lowest programming state adjacent to the lowest programming state data "011" can be "001".

[0137] Reference Figure 4 and Figure 5 The code values ​​of LSB, CSB, and MSB can vary depending on how multiple bits of data are stored in a non-volatile memory cell. For example, corresponding to... Figure 4 The MSB code value for the eight programming states shown can be "10101010", while Figure 5 The MSB code value for the eight programming states shown can be "11100001". According to the implementation method, Figure 4 and Figure 5 The code values ​​of the LSB and MSB described herein may vary depending on the implementation method.

[0138] Figure 6 The programming voltage application operation and verification operation of the ISPP operation according to an embodiment of the present disclosure are illustrated.

[0139] Reference Figure 6 After performing the programming voltage application operation Pgm during ISPP operation, the memory device 150 performs a verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can adjust the threshold voltage V of the non-volatile memory cell. TH Increase (i.e., shift to the right along the x-axis). For example, each programming voltage applied by operation Pgm will increase the threshold voltage V of the non-volatile memory cell. TH Increase the first potential difference ΔV.

[0140] After performing the programming voltage application operation Pgm, the threshold voltage V of the non-volatile memory cell can be applied during the verification operation. TH Compare with the verification voltage. When the threshold voltage V of the non-volatile memory cell... TH If the voltage drops below the verification voltage, another programming voltage application operation Pgm can be performed to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, a verification operation Ver is performed in response to the corresponding programming voltage application operation Pgm. Repeated programming voltage application operations Pgm can be performed until the threshold voltage V of the non-volatile memory cell is reached. TH To achieve the target voltage (e.g., the verification voltage).

[0141] According to the implementation method, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. When the threshold voltage V of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm... TH At this rate, the accuracy of the programming voltage application operation can be increased. However, with more programming voltage applications that can be performed, the latency can be longer and the power consumption can be greater. On the other hand, when the threshold voltage V of the non-volatile memory cell... TH By significantly increasing the power consumption of the programming voltage application operation Pgm, the operating time of Pgm can increase, but the operating time of Pgm can decrease. The operating time Δt of the programming voltage application operation Pgm and the verification operation Ver can be determined based on the target power of each programming voltage application operation Pgm (e.g., threshold voltage V). TH (Changes)

[0142] Reference Figure 4 and Figure 5 In a memory device comprising a three-level non-volatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently depending on the purpose and process of programming data in the least significant bit (LSB), center significant bit (CSB), and most significant bit (MSB) of the memory cell. Figure 4 As an example, a memory device including a three-level non-volatile memory cell (TLC) has been described, but the above programming operations can also be applied to memory devices including a four-level non-volatile memory cell (QLC) for storing 4 bits of data, or a non-volatile memory cell capable of storing 5 or more bits of data.

[0143] According to the implementation, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased according to a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same, for example, unchanged. In the verification operation Ver for each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can be changed. When the verification operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verification pulse.

[0144] Figure 7 The target level corresponding to a plurality of programming pulses is illustrated according to an embodiment of the present disclosure.Figure 7 The programming state of a non-volatile memory cell storing 2 bits of data is shown, along with the programming pulse and target level.

[0145] Reference Figure 7 The non-volatile memory cell may have an erase state P0 and three programming states P1 to P3. For example, the memory device 150 may apply a second reference voltage REF2 to the non-volatile memory cell to distinguish the erase state P0 and the first programming state P1 from the second programming state P2 and the third programming state P3. In the memory device 150, the first reference voltage REF1 may be used to distinguish the erase state P0 and the first programming state P1. The memory device 150 may use a third reference voltage REF3 to distinguish the second programming state P2 and the third programming state P3 from each other. For example, the erase state P0 may represent 2 bits of data "11", the first programming state P1 may represent 2 bits of data "10", the second programming state P2 may represent 2 bits of data "00", and the third programming state P3 may represent 2 bits of data "01". According to the embodiment, the number of data bits that can be stored in the non-volatile memory cell may vary. Furthermore, the number of reference voltages or reference voltage levels used to distinguish multiple bits of data may vary.

[0146] In the process of programming a non-volatile memory cell from an erase state P0 to one of the programming states from the first programming state P1 to the third programming state P3, multiple programming pulses can be applied. When a programming pulse is applied to a specific memory cell, the threshold voltage of the corresponding memory cell can be gradually increased. For example, to increase the threshold voltage of a specific non-volatile memory cell from the second programming state P2 to the third programming state P3, multiple programming pulses can be applied in stages. Figure 7 In this process, by applying 8 programming pulses or applying 8 programming pulses repeatedly, the threshold voltage distribution of a non-volatile memory cell can be gradually increased from the second programming state P2 to the third programming state P3. The greater the number of programming pulses applied to a specific memory cell to increase the preset level of the threshold voltage, the narrower the width of the threshold voltage distribution.

[0147] If the threshold voltage distribution of a non-volatile memory cell can be slightly shifted to the right by the programming pulse applied during the programming voltage application operation, a verification operation can be performed in response to the programming voltage application operation. For example, after applying the Nth programming pulse, the memory device 150 can perform a verification operation on the N target level corresponding to the Nth programming pulse. According to an embodiment, after applying the Nth programming pulse, verification operations are performed on multiple target levels (e.g., the N target level, N-1 target level, and N-2 target level corresponding to the Nth programming pulse, the (N-1)th programming pulse, and the (N-2)th programming pulse, respectively). If verification operations are performed on several target levels after applying a single programming pulse, the memory device 150 can more accurately determine the threshold voltage distribution of multiple non-volatile memory cells. Based on the verification, the memory device 150 can narrow the width of the threshold voltage distribution, each threshold voltage distribution corresponding to one of the first programming states P1 to the third programming states P3. Furthermore, the memory device 150 can more accurately determine the degree of wear or the operational result.

[0148] When multiple programming pulses are applied while storing data in multiple non-volatile memory cells included in memory group 330, reference Figure 1 The described control circuitry 180 may include information about the target level to be verified in response to each programming pulse. Additionally, based on the result of the verification operation performed in response to each programming pulse, the control circuitry 180 may include information about the level or duration of the next programming pulse applied to the plurality of non-volatile memory cells. According to an embodiment, this information may be stored in the form of a lookup table.

[0149] Figure 8 Programming operations in a memory device 150 according to an embodiment of the present disclosure are illustrated. Figure 8 In this context, the non-volatile memory cell of the memory device 150 can store a single bit (1 bit) of data, and the memory device 150 can be controlled to change the threshold voltage of the non-volatile memory cell to either an erase state E or a programmable state P. (Refer to...) Figure 6 During the described Incremental Step Pulse Programming (ISPP) operation, the threshold voltage of the non-volatile memory cell can change from the erase state E to the programming state P. Additionally, it should be noted that... Figure 6 In this context, a verification operation can be performed after the programming pulse is applied.

[0150] Reference Figure 8The verification operation can use two verification voltages, Vvfyp and Vvfym. For example, a data programming operation supporting Dual Verification Programming (DPGM) can be performed using two verification voltage levels during the verification operation. By using verification operations with two different verification voltage levels, the degree to which a non-volatile memory cell is programmed in response to the next programming pulse can be adjusted. For example, memory device 150 can determine the amount of change in threshold voltage that may be caused by a subsequent programming pulse.

[0151] According to the implementation, the verification voltage may include a pre-verification voltage Vvfyp and a main verification voltage Vvfym. The main verification voltage Vvfym may be a verification voltage corresponding to the target state of the data programming operation. The pre-verification voltage Vvfyp may have a level lower than the main verification voltage Vvfym. In the verification operation, the pre-verification voltage Vvfyp can be used to check the extent to which a data programming operation has been performed on the non-volatile memory cell. When the verification operation using the main verification voltage Vvfym detects that the threshold voltage of the non-volatile memory cell has been changed to a programming state P, further programming of the non-volatile memory cell is not required with subsequent programming pulses. Alternatively, when the threshold voltage of the non-volatile memory cell is lower than the pre-verification voltage Vvfyp, the non-volatile memory cell can be programmed with subsequent programming pulses.

[0152] If the threshold voltage of a non-volatile memory cell is within the range between the pre-verification voltage Vvfyp and the main verification voltage Vvfym, the non-volatile memory cell may be overprogrammed when it is normally programmed by subsequent programming pulses. For example, the threshold voltage of the non-volatile memory cell may be shifted too far to the right, in which case overprogramming may occur. Therefore, the memory device 150 can reduce the amount of change in the threshold voltage. In this case, the memory device 150 can control or adjust the degree of programming of the non-volatile memory cell, such as the amount of change in the threshold voltage, while subsequent programming pulses are applied. Therefore, the memory device 150 can control the potential of the bit line while performing the programming operation. (Refer to...) Figure 8 The length of the arrow in the diagram indicates that the change in threshold voltage caused by the first mode (PGM) is different from the change in threshold voltage caused by the second mode (DPGM).

[0153] In addition, Figure 8In this context, when multiple non-volatile memory cells are programmed using programming pulses, and then a verification operation is performed using a pre-verification voltage Vvfyp and a main verification voltage Vvfym, the multiple non-volatile memory cells may be in three different states MC1, MC2, and MC3. For a non-volatile memory cell in the first state MC1, which is lower than the pre-verification voltage Vvfyp, the memory device 150 can apply the next programming pulse to change or shift the threshold voltage of the corresponding memory cell by an amount corresponding to the corresponding programming pulse. This general programming mode (PGM mode) can be referred to as the first programming mode.

[0154] On the other hand, if a non-volatile memory cell has a third state MC3 that is higher than the main verification voltage Vvfym, then because the threshold voltage of the non-volatile memory cell has reached the programming state P, the memory device 150 can avoid or prevent further programming of the corresponding memory cell by subsequent programming pulses. In one embodiment, preventing non-volatile memory cells from being further programmed can be referred to as a programming-disabled mode.

[0155] When a non-volatile memory cell is in the second state MC2, the threshold voltage of the non-volatile memory cell may be excessively shifted when the corresponding non-volatile memory cell is programmed in the first programming mode (PGM mode). Therefore, when a subsequent programming pulse is applied, the change in threshold voltage caused by the second programming mode (DPGM mode) can be less than the change caused by the first programming mode (PGM mode).

[0156] The degree to which a non-volatile memory cell is programmed can be determined based on the timing of the applied programming pulse, the number of programming pulses applied, and / or the potential difference between programming pulses, for example, the amount of change in the threshold voltage. Although in some embodiments the programming pulses applied to multiple non-volatile memory cells connected to a single word line may be the same, the memory device 150 may vary or adjust the amount of threshold voltage change for each non-volatile memory cell. To increase the threshold voltage of the multiple non-volatile memory cells by different amounts, the memory device 150 may vary or adjust the potential of the bit lines connected to the multiple non-volatile memory cells.

[0157] For example, during the period when a programming pulse is applied to a word line, a reference (e.g., ground) voltage can be applied to the bit line connected to a first memory cell with a threshold voltage in a first state MC1, but the potential of another line connected to a second memory cell having a threshold voltage in a second state MC2 can be higher than the reference (e.g., ground) voltage. Because the potential difference between the word line and the bit line connected to the non-volatile memory cell is small, the amount of change in the threshold voltage caused by the programming pulse can be small.

[0158] When the potential difference between the word line and the bit line is lower than a preset level, the non-volatile memory cell will not be programmed. Because the potential difference of the second memory cell with the second state MC2 is less than the potential difference of the first memory cell with the first state MC1, the degree to which the second memory cell is programmed by subsequent programming pulses can be less than the degree to which the first memory cell is programmed by subsequent programming pulses.

[0159] Furthermore, even when a subsequent programming pulse is applied to the third memory cell with the third state MC3, a programming inhibit voltage can be applied to the bit line connected to the third memory cell. Because the potential difference between the programming pulse applied to the third memory cell with the third state MC3 and the programming inhibit voltage is lower than a preset level, the third memory cell with the third state MC3 can be further programmed without subsequent programming pulses.

[0160] The programming mode can be determined based on the verification result corresponding to the programming operation performed on the non-volatile memory cell. The programming mode can include a first programming mode (PGM mode), a second programming mode (DPGM mode), and a third programming mode (PGM disable mode). For example, a successful verification can indicate that the non-volatile memory cell is read as an off cell in response to a verification voltage. A failed verification can indicate that the non-volatile memory cell is read as an on cell in response to a verification voltage. For example, if the threshold voltage of the non-volatile memory cell is lower than the verification voltage on the left, the non-volatile memory cell can be read as an on cell. However, if the threshold voltage is equal to or higher than the verification voltage on the right, the non-volatile memory cell can be read as an off cell.

[0161] Reference Figure 8 Non-volatile memory cells programmed in the first programming mode (PGM mode) can be read as active cells by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. Another non-volatile memory cell programmed in the second programming mode (DPGM mode) can be read as deactivated by the pre-verification voltage Vvfyp and as active by the main verification voltage Vvfym. Another non-volatile memory cell programmed in the third programming mode (PGM disabled mode) can be read as deactivated by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. Furthermore, because the level of the pre-verification voltage Vvfyp is lower than the level of the main verification voltage Vvfym, it is impossible for a non-volatile memory cell to be read as active by the pre-verification voltage Vvfyp but as deactivated by the main verification voltage Vvfym.

[0162] Figure 9Examples of programming operations that can be modified based on the discharge of the serial and bit lines according to embodiments of the present disclosure are illustrated. For example, Figure 9 An example is illustrated by the discharge of the channel of series 340 through a first transistor before or simultaneously with the application of a programming pulse during a data programming operation. This first transistor is operated by a first control voltage applied via the drain select line DSL.

[0163] Reference Figure 9 When a programming pulse is applied to the selected word line Sel_WL, a pass voltage can be applied to the unselected word line Unsel_WL. Before applying the programming pulse, a first control voltage and a second control voltage can be applied separately to the drain select line DSL and the serial select line SSL. Subsequently, when the page buffer control signal PBSENSE is activated, the potential of each bit line BL can be maintained differently.

[0164] For reference Figure 8 As described, the page buffer control signal PBSENSE can be activated in response to one of three programming modes. For example, when the programming mode for the non-volatile memory cell is the first programming mode (PGM mode, general PGM mode, MPGM), the bit line connected to the non-volatile memory cell is maintained at a reference (e.g., ground) voltage. When the programming mode is the third mode (PGM disable mode), the potential of the bit line can be increased by a programming disable voltage. When the programming mode for the non-volatile memory cell is the second mode (DPGM), the potential of the bit line can increase with a time difference. To reduce the extent to which data is programmed in the non-volatile memory cell, the potential of the bit line is changed simultaneously with the application of the programming pulse. After the programming pulse is applied, the second control voltage applied via the serial select line SSL can be disabled.

[0165] Specifically, the programming operation can begin at a first time point t1. When the drain select line DSL and the source select line SSL are activated, charge can flow across the two ends of string 340. When the page buffer control signal PBSENSE is activated, the potential of the bit line BL connected to the non-volatile memory cell in the programming-disabled mode can be raised. Furthermore, the bit line BL connected to the non-volatile memory cell in the first programming mode (PGM mode) or the second programming mode (DPGM mode) can be kept at ground voltage.

[0166] At the second time point t2, a programming voltage can be applied to the selected word line Sel_WL, and a pass voltage can be applied to the unselected word line Unsel_WL.

[0167] At the third time point t3, the programming voltage potential can be increased, and the threshold voltage connected to the non-volatile memory cell of the selected word line Sel_WL can also be increased. When the potential of the bit line BL connected to the non-volatile memory cell corresponding to the programming disabled mode remains high, the threshold voltage of the corresponding non-volatile memory cell can remain unchanged.

[0168] At the fourth time point t4, the page buffer control signal PBSENSE can be adjusted to distinguish the first programming mode (PGM mode) and the second programming mode (DPGM mode) from each other. The level of the page buffer control signal PBSENSE can be lowered to halfway turn on the transistors used to connect the bit line BL or the page buffer to the non-volatile memory cells in which the second programming mode DPGM is executed. Previously, the page buffer control signal PBSENSE applied between the first time point t1 and the second time point t2 was to fully turn on the transistors, while a lower level of the page buffer control signal PBSENSE is applied to the transistors at the fourth time point t4. The transistors turned on or off by the page buffer control signal PBSENSE can be used as elements with resistors according to the level of the page buffer control signal PBSENSE. According to an embodiment, the value stored in the latch of the page buffer can be changed from "0" to "1" at the fourth time point t4. Even if a value of "1" is stored in the latch of the page buffer, the potential of the bit line can be maintained at a level lower than a preset level corresponding to the value of "1". Through this process, the memory device 150 can execute a second programming mode (DPGM mode) that differs from the first programming mode (PGM mode) or the programming disable mode (disabled mode). See below for further details. Figure 11 This describes the control in the second programming mode (DPGM mode). Here, executing the first programming mode (PGM mode) and the second programming mode (DPGM mode) may include executing or running programming operations in the first programming mode (PGM mode) and the second programming mode (DPGM mode), respectively.

[0169] When a programming operation is performed during a preset time period, the memory device 150 may stop applying a programming voltage to the selected word line Sel_WL at a fifth time point t5. Thereafter, at a sixth time point t6, the memory device 150 may stop applying a pass voltage to the unselected word line Unsel_WL.

[0170] Figure 10 The relationship between the results of the current sensing circuit (CSC) in the memory device and the threshold voltage distribution is illustrated.

[0171] Reference Figure 10The memory device 150 can operate programming data via ISPP and use a current sensing circuit (CSC) to perform check operations 432, 434 in at least some of the multiple programming cycles included in the ISPP operation. Check operations 432, 434 can be performed to check the threshold voltage distribution of multiple non-volatile memory cells.

[0172] Specifically, in Figure 10 In the ISPP operation, there are N programming loops, where N is a natural number. The number of programming loops executed by the memory device 150 can vary depending on the data stored in the non-volatile memory cell or the characteristics of the non-volatile memory cell.

[0173] Each programming cycle may include a unit programming operation (PGM) for applying programming pulses to non-volatile memory cells to program data, and a corresponding verification operation (program verification, PV). See reference. Figure 8 Bit lines (BL control) connected to non-volatile memory cells can be controlled before or during programming operations (PGM). For example, refer to... Figure 6 The threshold voltage of a non-volatile memory cell capable of storing 2 bits of data can change from the erase state P0 to the third programming state P3. The memory device 150 can monitor or track changes in the threshold voltage while repeatedly executing a programming cycle that includes unit programming operations and verification operations.

[0174] As the threshold voltage distribution for non-volatile memory cells with various programming states becomes narrower, the security of data stored in non-volatile memory cells can be improved or enhanced.

[0175] According to the implementation, when the programming level increased by a specific programming cycle executed by the memory device 150 differs significantly from the target programming state of the non-volatile memory cell, the verification operation following the unit programming operation may not be performed. On the other hand, when one of the three programming states P1 to P3 is the target programming state of the non-volatile memory cell and the programming level is expected to reach the target programming state, a verification operation for the non-volatile memory cell may be performed. Verification operations may also be performed on other non-volatile memory cells connected to the same word line as the non-volatile memory cell.

[0176] When the threshold voltage of a non-volatile memory cell approaches the target programming value (N-2 cycles, N-1 cycles, N cycles), the memory device 150 can perform a check operation using a current sensing circuit (CSC). The programming value can indicate the threshold voltage level between adjacent programming states (see [link to documentation]). Figure 7During the check operation, the memory device 150 may establish a comparison voltage that is lower than a preset level corresponding to a programming state or programming value that is the target of the programming operation. For example, the comparison voltage may correspond to one of the target programming values ​​in the previous programming cycle performed on the non-volatile memory cells. The memory device 150 may count the number of non-volatile memory cells whose threshold voltage is lower than the comparison voltage. The memory device 150 may then compare the count with a reference to output a pass signal (PASS) or a failure signal (FAIL) as the result of the check operation.

[0177] According to the implementation, the memory device 150 can perform a programming operation 422 and a bit line control 452. Then, the memory device 150 can perform a check operation 432. When the result of the check operation is a failure signal FAIL (N-2 cycles), the memory device 150 can perform a verification operation 442 corresponding to the programming operation 422. During the verification operation, the memory device 150 can apply verification voltages corresponding to multiple programmed values ​​to multiple non-volatile memory cells. For example, as... Figure 6 As shown, when multiple programming pulses are sequentially applied to a non-volatile memory cell several times (e.g., n+2, n+1, n, n-1, or n-2 cycles), the memory device 150 can identify or estimate which non-volatile memory cell has a threshold voltage corresponding to the programming value targeted by the multiple programming pulses. (Refer to...) Figure 8 In response to the result of the verification operation, the memory device 150 can determine which of the following modes—a first programming mode (PGM mode), a second programming mode (DPGM mode), and a programming prohibition mode (prohibition)—is to be performed on the non-volatile memory cell.

[0178] According to the implementation, when the result of the check operation is a pass signal (PASS) (N-1 cycle), the memory device 150 may not perform a verification operation on the non-volatile memory cell. After executing bit line control 454 together with programming operation 424, the memory device can determine whether the threshold voltage distribution in a specific programming cycle (N-1 cycle) meets the reference (PV*CSC passes) through check operation 434. When the threshold voltage distribution is met, the memory device 150 may not perform the verification operation corresponding to programming operation 424, and then may execute the next programming cycle (N cycle).

[0179] When the result of the check operation in a specific programming cycle (N-1 cycle) is a pass signal (PV*CSC pass), the memory device 150 can perform a second programming mode (DPGM) or a third programming mode (programming disabled) on the non-volatile memory cell during the next programming cycle (N cycle) as programming operation 426. In this cycle (N cycle), the memory device 150 may not perform the first programming mode (PGM mode) on the non-volatile memory cell. Furthermore, after performing programming operation 426 in the second programming mode (DPGM) and programming disabled mode in the next programming cycle (N cycle), the verification operation corresponding to programming operation 426 may be skipped (not performed).

[0180] As a result, when the result of the check operation is a pass signal (PV*CSC pass), the memory device 150 can skip the verification twice. For example, the two verification operations corresponding to the two programming operations 424 and 426 can be skipped. Through this process, the memory device 150 can reduce the time spent on the ISPP operation. In the following, it will be described how the memory device 150 performs the programming operation differently when the result of the check operation 432 is a failure signal (PV*CSC failure) and when the result of the check operation 434 is a pass signal (PV*CSC pass).

[0181] Figure 11 An example of a memory device for performing programming operations according to an embodiment of the present disclosure is shown.

[0182] Reference Figure 11 After performing a programming operation corresponding to a specific programming value PV, the threshold voltage distribution of the plurality of non-volatile memory cells can have a Gaussian distribution. The width D_W1 of the threshold voltage distribution can vary depending on the characteristics of the plurality of non-volatile memory cells. For a checking operation, the memory device 150 can apply a comparison voltage PV* having a level less than the specific programming value PV to the plurality of non-volatile memory cells.

[0183] If the result of the reference check operation is a failure signal (PV*CSC failure), the number of non-volatile memory cells with a threshold voltage lower than the comparison voltage (PV*) in the threshold voltage distribution of multiple non-volatile memory cells may be greater than the first reference. In this case, the memory device 150 can perform a verification operation. Based on the result of the verification operation, the memory device 150 can execute a first programming mode (PGM mode) on some of the non-volatile memory cells with a threshold voltage lower than the comparison voltage PV* in the next cycle to cause a larger change in the threshold voltage of the corresponding non-volatile memory cells. Furthermore, the memory device 150 can execute a second programming mode (DPGM) on other non-volatile memory cells with a threshold voltage greater than the comparison voltage PV* but lower than the programming value PV in the next cycle to cause a smaller change in the threshold voltage of the corresponding non-volatile memory cells. The memory device 150 can determine, based on the result of the verification operation, which of the first programming mode (PGM mode) and the second programming mode (DPGM) will be executed for each of the plurality of non-volatile memory cells in the next cycle. Furthermore, the memory device 150 can, based on the result of the verification operation, execute a programming disable mode for non-volatile memory cells having a threshold voltage greater than a specific programming value PV in the next cycle.

[0184] After performing at least one programming operation in the memory device 150, the result of the check operation may be a pass signal (PV*CSC pass). When the result of the check operation is a pass signal (PV*CSC pass), the number of non-volatile memory cells with a threshold voltage lower than the comparison voltage PV* in the threshold voltage distribution of the plurality of non-volatile memory cells may be less than the second reference. The second reference may be the same as or different from the first reference. In this case, the memory device 150 may determine that a verification operation is not required. Furthermore, the memory device 150 may determine that the deviation of the threshold voltage distribution of the plurality of non-volatile memory cells becomes smaller relative to a specific programming value PV. That is, the width (D_W2) of the threshold voltage distribution when the result of the check operation is a pass signal (PV*CSC pass) may be narrower than the width (D_W1) of the threshold voltage distribution when the result of the check operation is a failure signal (PV*CSC failure). According to an embodiment, when the memory device 150 performs a second programming mode DPGM on non-volatile memory cells with a threshold voltage lower than the comparison voltage PV*, the width of the threshold voltage distribution of the plurality of non-volatile memory cells may become smaller. Furthermore, through the second programming mode DPGM, the memory device 150 can determine that the data corresponding to a specific programming value PV is stored in multiple non-volatile memory cells. Therefore, the memory device 150 can skip the verification operation for the multiple non-volatile memory cells based on the result of the check operation.

[0185] Furthermore, the memory device 150 can establish a comparison voltage PV* for checking operations. According to an embodiment, the comparison voltage PV* can be set based on a programming value. For example, the memory device 150 sets a comparison voltage PV* having a level within a range between the programming value PV and a preset level, which is obtained by subtracting the change in the threshold voltage of the non-volatile memory cell caused by the second programming mode DPGM from the programming value PV. In another example, the memory device 150 can determine a comparison voltage PV* within a range between the programming value PV_n and the programming value PV_n-1 of the previous cycle following the programming value PV_n. (See also...) Figure 1 For ISPP operation, the control circuit 180 in memory device 150 can store both the programming value PV used to apply the programming pulse in each programming cycle and the comparison voltage PV* used to check the operation in a register or table.

[0186] Figure 12 An example of a current sensing circuit (CSC) according to an embodiment of the present disclosure is illustrated.

[0187] Reference Figure 12The memory device 150 may include a string 340, which includes a plurality of non-volatile memory cells. The string 340 may include: a first transistor connected to a bit line BL for operation in response to a first control voltage applied via a drain select line DSL; a second transistor connected to a source line SL for operation in response to a second control voltage applied via a string select line SSL; and at least one non-volatile memory cell connected between the first and second transistors. At least one non-volatile memory cell can be programmed by a programming pulse applied via a word line. Figure 12 The source line SL shown can correspond to the reference. Figure 1 The described common source line CSL, the first transistor may correspond to the drain selection transistor DST, and the second transistor may correspond to the string selection transistor SST. According to the implementation, the first transistor and / or the second transistor may each be implemented as a plurality of transistors connected in series with each other.

[0188] As the storage space of the memory device 150 increases, the number of non-volatile memory cells connected in series between the first transistor and the second transistor can be increased. (Refer to...) Figure 12 Multiple bits of data can be programmed sequentially in a preset order (PGM order), from one non-volatile memory cell connected to the first transistor to another non-volatile memory cell connected to the second transistor. The multiple non-volatile memory cells included in string 340 can be divided into programming states (P1, P2, P3, see...) Figure 7 The programmed non-volatile memory cell 342 and the data therein which is erased to maintain the erased state (P0, see P0). Figure 7 The erased nonvolatile memory cell 344. When the next programming operation is performed, a programming pulse can be applied to the selected word line Sel_WL connected to the nonvolatile memory cell located adjacent to the programmed nonvolatile memory cell 342. When the programming pulse is applied to the selected word line Sel_WL, a plurality of memory cells connected to the selected word line Sel_WL can be selectively programmed (e.g., in response to the potential of the bit line).

[0189] Serial 340 can be connected to page buffer 322 via bit line BL. The connection between bit line BL and page buffer 322 can be controlled by bit line select signal SEL_BL and page buffer control signal PB_SENSE. Page buffer 322 may include multiple latches. The multiple latches may include a programming latch (P_LAT, 414) capable of storing different or changed values ​​according to the programming mode, a check latch (C_LAT, 412) capable of storing data output from serial 340, etc. According to the implementation, the programming latch 414 may be used differently depending on the operation performed on serial 340. When a read operation is performed, data is transferred from serial 340 via bit line BL and can be stored in page buffer 322. Multiple latches can be used to temporarily store data before data output. When a programming operation is performed, the data stored in multiple latches can be used to control the potential of bit line BL connected to serial 340. Furthermore, the number of latches may vary depending on the number of bits of data stored in the non-volatile memory cell. Because each latch can store 1 bit of data, the four latches connected to the page buffer 322, which includes a string 340 capable of storing 4 bits of non-volatile memory, can be used for read or program operations. According to an embodiment, the page buffer 322 may include multiple latches separately partitioned for data input / output operations.

[0190] ISPP operations may include programming operations, checking operations, and verification operations. Some of the latches in page buffer 322 can be used as latches for checking and verification operations to store data transferred from string 340 as if it were a read operation, while other latches are used to control the potential of bit line BL for programming operations. Furthermore, page buffer 322 may also include at least one switching element for selectively connecting latches to bit line BL.

[0191] exist Figure 10 In the inspection operations 432 and 434 described in the document, the comparison can be based on a single comparison voltage PV* (see [reference]). Figure 11 This determines the number of non-volatile memory cells. However, in Figure 10 In the verification operation 442 described herein, it may be based on multiple comparison voltages used to verify multiple programming states (e.g., Figure 7 The comparison of REF1 to REF3 shown in the figure determines the number of non-volatile memory cells. (Refer to...) Figure 11 The checks 432 and 434 can be used to determine whether the second programming mode (DPGM) is ultimately executed for at least one non-volatile memory cell. However, the verification operation 442 can be used to determine whether the first programming mode (PGM) and / or the second programming mode (DPGM) are executed for multiple programming states programmed in multiple non-volatile memory cells.

[0192] According to one embodiment, the page buffer 322 can be connected to a current sensing circuit (CSC) 432. The current sensing circuit CSC 432 can be connected to a check latch C_LAT 412 capable of storing values ​​corresponding to a single target level transferred from a non-volatile memory cell during a check operation. Unlike a check operation, when performing a verification operation based on multiple programming levels P0 to P4, the values ​​corresponding to each programming level P0, P1, P2, P3 can be stored in multiple check latches 412 within the page buffer 322. (See also...) Figure 12 The current sensing circuit CSC 432 can determine the value transferred from the non-volatile memory cell based on the comparison voltages PV* and PV. The current sensing circuit 432 can be connected to multiple strings 340 and can compare the value transferred from multiple non-volatile memory cells connected to the selected word line Sel_WL with the comparison voltages PV* and PV. The number of non-volatile memory cells having a threshold voltage lower than the comparison voltages PV* and PV can be counted. When the number of non-volatile memory cells having a threshold voltage lower than the comparison voltages PV* and PV is less than a reference, the current sensing circuit (CSC) 432 can output a pass signal PASS to the control circuit 180. Otherwise, it can output a failure signal FAIL to the control circuit 180.

[0193] Figure 13 A method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0194] Reference Figure 13 The method for operating the memory device may include starting a programming operation (operation 710), controlling the potential of the bit line and applying a programming pulse for the programming operation (operation 712), and performing a check operation via a current sensing circuit CSC after the programming pulse is applied (operation 714).

[0195] When the check operation fails ("No" in operation 714), the method for operating the memory device may include verifying the programming operation (operation 718) and determining whether to terminate the programming operation based on the verification result (operation 720). Because the check operation failed ("No" in operation 714), the memory device may estimate that additional programming pulses should be applied to at least some of the plurality of non-volatile memory cells. In operation 720, the memory device may determine, based on the verification result, whether to execute a first programming mode (PGM) or a second programming mode (DPGM) on the plurality of non-volatile memory cells. Thereafter, the memory device 150 may execute operation 712, which involves controlling the bit lines and applying programming pulses to execute the next programming cycle (cycle increment).

[0196] When the check operation passes ("Yes" in operation 714), the memory device 150 may execute a second programming mode (DPGM) on at least some non-volatile memory cells as the next programming cycle (operation 716). After executing the second programming mode DPGM (operation 716), the memory device 150 may terminate the programming operation (operation 722).

[0197] When the check operation passes ("Yes" in operation 714), the memory device 150 may not execute operation 718, which verifies the result of operation 712 corresponding to the applied programming pulse. Furthermore, the memory device 150 may not execute another verification operation corresponding to the second programming mode DPGM (operation 716) executed as the next programming cycle. This process reduces the time spent on programming operations and the operational margin. It also alleviates the burden caused by verification operations performed on multiple non-volatile memory cells.

[0198] The memory device according to the embodiments of this disclosure can improve data input / output speed.

[0199] Furthermore, according to the embodiments of this disclosure, the data security of the memory device can be improved, and the wear and tear on the memory device can be reduced.

[0200] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0201] In addition, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be volatile or non-volatile memory or other storage device, which may be removably or permanently coupled to a computer, processor, controller, or other signal processing device that will execute the code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0202] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can, for example, be implemented in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of the following integrated circuits, including but not limited to: application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

[0203] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions, for example, to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those other than those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method implementation can transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0204] While the teachings have been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0205] Cross-references to related applications

[0206] This patent application claims priority to Korean Patent Application No. 10-2021-0119093, filed on September 7, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A cell group, which includes multiple non-volatile memory cells capable of storing data; as well as A control circuit performs programming operations to program data into a plurality of non-volatile memory cells through multiple programming cycles. Each programming cycle includes a unit programming operation for applying a programming pulse to the plurality of non-volatile memory cells and a verification operation for verifying the result of the unit programming operation. The control circuit uses a current detection circuit to detect whether a threshold voltage distribution of the plurality of non-volatile memory cells meets a reference in a specific programming cycle of the plurality of programming cycles. When the threshold voltage distribution meets the reference, the verification operation of the specific programming cycle is skipped, and the programming operation is terminated after a preset programming pulse is applied to the plurality of non-volatile memory cells in the next programming cycle following the specific programming cycle.

2. The memory device according to claim 1, wherein, The control circuit performs a check operation to identify the threshold voltage distribution during the time between the unit programming operation and the verification operation in some of the plurality of programming cycles.

3. The memory device according to claim 2, wherein, The inspection operation includes establishing a comparison voltage with a level lower than a preset level corresponding to a programming value that is the target of the programming operation, counting the number of non-volatile memory cells with a level lower than the comparison voltage, and comparing the count with the reference.

4. The memory device according to claim 3, wherein, The comparison voltage has a level within a first range or a second range, the first range being between the preset level and a level corresponding to the closest other programmed value below the preset level, and the second range being between the preset level and a level obtained by subtracting the degree to which the threshold voltage changed by the second mode is subtracted from the preset level.

5. The memory device according to claim 2, wherein, The inspection operation examines the threshold voltage distribution of the plurality of nonvolatile memory cells with respect to a plurality of programming values ​​corresponding to the programming operation.

6. The memory device according to claim 1, in, The unit programming operation is performed in a mode selected from the first mode, the second mode, and the third mode. In this mode, a second programming pulse is applied to change or adjust the threshold voltage of at least one of the plurality of non-volatile memory cells to a first level, wherein the first level is equal to or greater than the change level of the threshold voltage caused by the first programming pulse. The second mode involves applying the second programming pulse to change or adjust the threshold voltage of at least one non-volatile memory cell to a second level, the second level being less than the change level caused by the first programming pulse. The third mode involves applying the second programming pulse to at least one non-volatile memory cell whose threshold voltage is prohibited from being changed.

7. The memory device according to claim 6, wherein, The control circuit changes the value stored in a latch included in a page buffer in response to the mode selected among the first mode, the second mode, and the third mode. The page buffer is connected to bit lines coupled to the plurality of non-volatile memory cells.

8. The memory device according to claim 7, wherein, For the unit programming operation performed in the first mode, the control circuit stores the value "0" in a first latch; for the unit programming operation performed in the second mode, it stores the value "0" in a second latch and changes the value "0" in the second latch to the value "1" at a timing when the transistor connecting the bit line and the page buffer is turned on; and for the unit programming operation performed in the third mode, it stores the value "1" in a third latch.

9. The memory device according to claim 1, wherein, The control circuit executes the next programming cycle in either the second or third mode.

10. The memory device according to claim 1, wherein, The control circuit applies a verification voltage to the plurality of non-volatile memory cells to check whether data has been programmed into the plurality of non-volatile memory cells, the verification voltage corresponding to a plurality of programming values ​​that are the target of the programming operation.

11. The memory device according to claim 1, wherein, The control circuit determines the first mode, second mode, or third mode to be executed in the next programming cycle in response to the result of the verification operation.

12. A memory system comprising: A memory device performs a programming operation to program data into a plurality of non-volatile memory cells through a plurality of programming cycles. Each programming cycle includes a unit programming operation for applying a programming pulse to the plurality of non-volatile memory cells and a verification operation for verifying the result of the unit programming operation. The memory device uses a current detection circuit to detect whether a threshold voltage distribution of the plurality of non-volatile memory cells meets a reference in a specific programming cycle of the plurality of programming cycles. When the threshold voltage distribution meets the reference, the verification operation of the specific programming cycle is skipped, and the programming operation is terminated after a preset programming pulse is applied to the plurality of non-volatile memory cells in the next programming cycle following the specific programming cycle. as well as A controller that sends programming commands to the memory device and indicates the addresses of the plurality of non-volatile memory cells.

13. The memory system according to claim 12, wherein, The memory device includes at least one memory chip or at least one memory plane.

14. The memory system according to claim 12, wherein, The memory device performs a check operation to identify the threshold voltage distribution during the time between the unit programming operation and the verification operation in some of the plurality of programming cycles.

15. The memory system according to claim 14, wherein, The inspection operation includes establishing a comparison voltage with a level lower than a preset level corresponding to a programming value that is the target of the programming operation, counting the number of non-volatile memory cells with a level lower than the comparison voltage, and comparing the count with the reference.

16. The memory system according to claim 12, wherein, The unit programming operation is performed in a mode selected from a first mode, a second mode, and a third mode. The first mode is to apply a second programming pulse to change or adjust a first level of the threshold voltage of at least one of the plurality of non-volatile memory cells. The first level is equal to or greater than the change level of the threshold voltage caused by the first programming pulse. The second mode is to apply the second programming pulse to change or adjust the threshold voltage of at least one non-volatile memory cell to a second level, the second level being less than the change level caused by the first programming pulse; The third mode is to apply the second programming pulse to at least one non-volatile memory cell whose threshold voltage is prohibited from being changed.

17. The memory system according to claim 12, wherein, The memory device executes the next programming cycle in either a second or a third mode.

18. The memory system according to claim 12, wherein, The memory device determines a first mode, a second mode, or a third mode to be executed in the next programming cycle in response to the result of the verification operation.

19. A method for operating a memory system, the method comprising the steps of: Receive programming commands, programming data, and the location information where the data will be stored; In response to the programming data, the bit lines connected to a plurality of non-volatile memory cells corresponding to the location information are controlled, and programming pulses are applied to the word lines connected to the plurality of non-volatile memory cells; The threshold voltage distribution of the plurality of non-volatile memory cells is checked by a current detection circuit to see if it meets the reference. as well as When the threshold voltage distribution meets the benchmark in a specific programming cycle, the verification operation of the plurality of non-volatile memory cells is skipped and a second programming mode is executed on some of the plurality of non-volatile memory cells in the next programming cycle after the specific programming cycle.

20. The method of claim 19, further comprising the step of: When the threshold voltage distribution does not meet the benchmark, a verification operation is performed on the plurality of non-volatile memory cells; as well as Based on the results of the verification operation, determine one of the first programming mode, second programming mode and third programming mode to be executed on the plurality of non-volatile memory cells.

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