Bit error rate measuring device and code word error display method

Abstract

The present invention can grasp the presence or absence of errors in FEC symbol length units for each codeword. The bit error rate measuring device (1) comprises: an operating unit (4) for setting the codeword length, FEC symbol length and FEC symbol error threshold according to the communication standard of the object under test (W); an error counting mechanism (7b) for counting FEC symbol errors and uncorrectable codewords detected at intervals of one FEC symbol; a display unit (6) for identifying and displaying bit string data in FEC symbol length units based on the counting result and the presence or absence of FEC symbol errors; and a display control mechanism (7d) for setting one area of ​​the display area for identification display to one FEC symbol length, making the area length of the horizontal axis of the display area consistent with one codeword length, and performing display control in a new row in codeword length units so that the start of one codeword for identification display is located at the left end of the display area and the end is located at the right end of the display area.

Description

Technical Field

[0001] The present invention relates to a bit error rate measuring device and a codeword error display method for measuring whether a FEC (Forward Error Correction) action of the object under test can be performed, when a known waveform (NRZ signal or PAM4 signal) is sent to the object under test as a test signal while the object under test is transferred to a signal waveform return state, and the bit error rate of input data returned and received from the object under test accompanying the sending of the test signal is measured. Background Art

[0002] Conventionally, a bit error rate measuring device is known as a device that sends a test signal of a known waveform containing fixed data to a device under test, and compares the signal under test that is returned and received from the device under test along with the sending of the test signal with a reference signal serving as a benchmark in units of bits to measure the bit error rate (BER).

[0003] As disclosed in Patent Document 1 listed below, this bit error rate measurement device has, for example, a function of coloring each bit or PAM4 symbol of the captured data according to the presence or absence of an error (occurrence / non-occurrence) and enabling visual confirmation of error distribution through error mapping.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2007-274474

[0005] According to the bit error rate measuring device of the above-mentioned patent document 1, the position of the bit error can be displayed in the bit waveform string, but it is not easy to judge the presence or absence of errors (occurrence / non-occurrence) or the distribution of errors for each FEC symbol length in units of codewords. That is, when an error occurs in the object under test due to a specific input waveform, it is not easy to understand where the error is likely to occur or the occurrence of uncorrectable codewords (codewords that cannot perform forward error correction) for each codeword. In addition, there is no function to count the position of the codeword that becomes uncorrectable or the number of errors in the uncorrectable codeword, so there is a problem that the error of the object under test cannot be effectively debugged.

[0006] That is, in the conventional error mapping function, it is not possible to segment the captured FEC symbol data according to the codeword length based on the selected communication standard, so the operation for determining the end point of the codeword length is not only troublesome, but also laborious and time-consuming. As a result, even if an uncorrectable codeword appears, it takes time to investigate the cause of the malfunction of the DUT, and there is a problem that effective debugging cannot be performed. Summary of the invention

[0007] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a bit error rate measurement device and a codeword error display method that can grasp the presence or absence of errors in FEC symbol length units for each codeword.

[0008] In order to achieve the above-mentioned object, the bit error rate measuring device according to the first embodiment of the present invention is a bit error rate measuring device 1 which inputs an NRZ signal of a known waveform as a test signal into a device under test W, receives a signal from the device under test accompanying the input of the test signal, and determines whether an FEC (Forward Error Correction) operation of the device under test can be performed based on a comparison result between the received signal and the test signal. The bit error rate measuring device comprises:

[0009] An operating unit 4 is configured to set the FEC codeword length, FEC symbol length and FEC symbol error threshold according to the communication standard of the object under test;

[0010] an error counting mechanism 7b, which counts FEC symbol errors detected at one FEC symbol interval according to a comparison result of comparing each bit of the bit string data received and converted from the signal of the object under test with the error data, and when the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, counts it as an Uncorrectable codeword for which forward error correction cannot be performed; and

[0011] The display unit 6 identifies and displays the bit string data in FEC symbol length units based on the counting result of the error counting mechanism and the presence or absence of FEC symbol errors,

[0012] The bit error rate measuring device is characterized by comprising:

[0013] The display control mechanism 7d sets a region of the display area of ​​the identification display of the display unit to the length of one FEC symbol, so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and performs display control in a new row in units of codeword length, so that the start of one codeword of the identification display is located at the left end of the display area, and the end of one codeword of the identification display is located at the right end of the display area.

[0014] The bit error rate measuring device according to the second embodiment of the present invention is a bit error rate measuring device 1 which inputs a PAM4 signal of a known waveform as a test signal into a device under test W, receives a signal from the device under test accompanying the input of the test signal, and measures whether the FEC operation of the device under test can be performed based on a comparison result between the received signal and the test signal. The bit error rate measuring device comprises:

[0015] An operating unit 4 is configured to set the FEC codeword length, FEC symbol length and FEC symbol error threshold according to the communication standard of the object under test;

[0016] an error counting mechanism 7b, which counts FEC symbol errors detected at one FEC symbol interval of the most significant bit string data and the least significant bit string data of the symbol string data received and converted from the signal of the object under test according to a comparison result of comparing the most significant bit string data and the least significant bit string data of the symbol string data with the error data, and when the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, counts it as an Uncorrectable codeword for which forward error correction cannot be performed; and

[0017] The display unit 6 identifies and displays the symbol string data in FEC symbol length units according to the counting result of the error counting mechanism and the presence or absence of FEC symbol errors,

[0018] The bit error rate measuring device is characterized by comprising:

[0019] The display control mechanism 7d sets a region of the display area of ​​the identification display of the display unit to the length of one FEC symbol, so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and performs display control in a new row in units of codeword length, so that the start of one codeword of the identification display is located at the left end of the display area, and the end of one codeword of the identification display is located at the right end of the display area.

[0020] The bit error rate measurement device according to claim 3 of the present invention is characterized in that, in the bit error rate measurement device according to claim 1 or 2,

[0021] The display unit 6 includes a multi-line display area 33 in which numbers are assigned corresponding to the respective lines of the identification display and which is linked to the scrolling display of the identification display.

[0022] The display control mechanism 7d sets the codeword of the row in which the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold as the Uncorrectable codeword, and controls the display unit 6 to identify and display the display area of ​​the row corresponding to the Uncorrectable codeword.

[0023] The bit error rate measurement device according to claim 4 of the present invention is characterized in that, in the bit error rate measurement device according to claim 3,

[0024] The display control unit 7d controls the display unit 6 to display a result of the total number of code words and the number of Uncorrectable code words.

[0025] The codeword error display method described in scheme 5 of the present invention is a codeword error display method of a bit error rate measuring device 1, wherein the bit error rate measuring device 1 inputs an NRZ signal of a known waveform as a test signal into a test object W, and receives a signal from the test object accompanying the input of the test signal, and determines whether the FEC action of the test object can be performed based on the comparison result between the received signal and the test signal. The codeword error display method comprises the following steps:

[0026] By means of the operating unit 4, the FEC codeword length, the FEC symbol length and the FEC symbol error threshold are set according to the communication standard of the object under test;

[0027] By the error counting mechanism 7b, the FEC symbol errors detected at 1 FEC symbol interval are counted based on the comparison result of comparing each bit of the bit string data received and converted from the signal of the test object with the error data;

[0028] When the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism counts the codeword as an Uncorrectable codeword for which forward error correction cannot be performed; and

[0029] According to the counting result of the error counting mechanism and the presence or absence of FEC symbol errors, the symbol string data is identified and displayed on a display unit (6) in units of FEC symbol length,

[0030] The code word error display method of the bit error rate measuring device is characterized by comprising the following steps:

[0031] A region of the display area of ​​the identification display of the display unit is set to the length of one FEC symbol so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and the display control mechanism 7d is used to start a new row in units of codeword length so that the start of one codeword of the identification display is located at the left end of the display area and the end of one codeword of the identification display is located at the right end of the display area.

[0032] The codeword error display method described in solution 6 of the present invention is a codeword error display method of a bit error rate measuring device 1, wherein the bit error rate measuring device 1 inputs a PAM4 signal of a known waveform as a test signal into a device under test W, and receives a signal from the device under test accompanying the input of the test signal, and determines whether the FEC action of the device under test can be performed based on a comparison result between the received signal and the test signal. The codeword error display method comprises the following steps:

[0033] By means of the operating unit 4, the FEC codeword length, the FEC symbol length and the FEC symbol error threshold are set according to the communication standard of the object under test;

[0034] By means of the error counting mechanism 7b, the FEC symbol errors detected at one FEC symbol interval of the most significant bit string data and the least significant bit string data of the symbol string data received and converted from the signal of the object under test are counted according to the comparison result of comparing the most significant bit string data and the least significant bit string data with the error data respectively;

[0035] When the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism counts the codeword as an Uncorrectable codeword for which forward error correction cannot be performed; and

[0036] According to whether there is an FEC symbol error, the symbol string data received from the signal of the test object and converted is identified and displayed on the display unit (6) in FEC symbol length units,

[0037] The code word error display method of the bit error rate measuring device is characterized by comprising the following steps:

[0038] A region of the display area of ​​the identification display of the display unit is set to the length of one FEC symbol so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and the display control mechanism 7d is used to start a new row in units of codeword length so that the start of one codeword of the identification display is located at the left end of the display area and the end of one codeword of the identification display is located at the right end of the display area.

[0039] The code word error display method described in solution 7 of the present invention is characterized in that, in the code word error display method of solution 5 or 6, it includes the following steps:

[0040] Displaying a multi-line display area (33) on the display unit (6) with numbers corresponding to the lines of the identification display and linked to the scrolling display of the identification display; and

[0041] The codeword in the row in which the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold is set as the Uncorrectable codeword, and the display unit 6 is controlled by the display control mechanism 7d to identify and display the display area of ​​the row corresponding to the Uncorrectable codeword.

[0042] The code word error display method described in solution 8 of the present invention is characterized in that, in the code word error display method of solution 7, it includes the following steps:

[0043] The display control unit 7d controls the display unit 6 to display the total number of code words and the number of Uncorrectable code words.

[0044] Effects of the Invention

[0045] According to the present invention, one codeword is displayed in one row, so that the user can easily determine the segmentation of the codeword and can easily confirm the error occurrence status of the FEC symbol length unit of each codeword. In addition, when the number of FEC symbol errors in the data segmented by each codeword exceeds the FEC symbol error threshold, it is easy to understand the position of the row of the Uncorrectable codeword. In addition, the occurrence ratio of the Uncorrectable codeword relative to all codewords can be known. As a result, the user can easily find out the cause of the bad condition of the object under test, so that effective troubleshooting can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a block diagram showing a schematic configuration of a bit error rate measurement device according to the present invention.

[0047] Figure 2 This is a diagram showing an example of a screen for capturing an error map when a PAM4 signal is input to a device under test in the bit error rate measurement device according to the present invention.

[0048] Figure 3 This is a diagram showing an example of a screen for capturing an error map when an NRZ signal is input to a device under test in the bit error rate measurement device according to the present invention.

[0049] Figure 4 This is a flowchart of processing operations when a PAM4 signal is input to a device under test in the bit error rate measurement device according to the present invention.

[0050] Figure 5 This is a flowchart of processing operations when an NRZ signal is input to a device under test in the bit error rate measurement device according to the present invention. DETAILED DESCRIPTION

[0051] Hereinafter, a mode for carrying out the present invention will be described in detail with reference to the drawings.

[0052] The bit error rate measuring device according to the present invention transmits a test signal of a known waveform to the device under test while the device under test is in a state where the signal waveform is returned, and measures the bit error rate of a received signal returned from the device under test accompanying the transmission of the test signal.

[0053] like Figure 1As shown, the bit error rate measuring device 1 of the present embodiment has the function of measuring whether the FEC (Forward Error Correction) operation of the object under test W can be performed based on the comparison result of the received signal from the object under test W when an NRZ (Non Return to Zero) signal with a known waveform inserted with an error or a PAM4 (Pulse Amplitude Modulation 4) signal with a 4-value symbol value is input as a test signal to the object under test W and the test signal, and is roughly constructed to include a signal generator 2, a bit error detector 3, an operation unit 4, a storage unit 5, a display unit 6 and a control unit 7.

[0054] In addition, in this embodiment, the configuration and processing contents for realizing the function of determining whether the FEC operation of the object W to be measured is possible are mainly described.

[0055] The signal generator 2 generates an NRZ signal in which bits do not return to 0 between each other or a PAM4 signal consisting of desired symbol string data (symbol string data consisting of symbol values ​​of 0, 1, 2, and 3) as reference data based on a multi-value signal.

[0056] When generating a PAM4 signal, such as Figure 1 As shown, the signal generator 2 is roughly configured to include a first signal generating section 2a, a second signal generating section 2b, and a signal synthesis output section 2c.

[0057] The amplitude of the PAM4 signal is divided into four types for each symbol, with four voltage levels of different amplitudes. The overall amplitude voltage range H is divided into a low voltage range, a medium voltage range, and a high voltage range from the low voltage level side, and is composed of a continuous range based on three eye diagram openings.

[0058] When generating a desired PAM4 symbol string composed of a known waveform including fixed data, the first signal generating unit 2a generates a most significant bit string signal (MSB: Most Significant Bit) for superimposing with the least significant bit string signal (LSB: Least Significant Bit) generated by the second signal generating unit 2b to generate a PAM4 signal.

[0059] The second signal generating section 2 b generates a least significant bit string signal for superimposing the least significant bit string signal with the most significant bit string signal generated by the first signal generating section 2 a to generate a PAM4 signal.

[0060] As specific bit sequence signals generated by the first signal generating unit 2a and the second signal generating unit 2b, there is PRBS7 (waveform length: 2 7 -1), PRBS9 (waveform length: 29 -1), PRBS10 (waveform length: 2 10 -1), PRBS11 (waveform length: 2 11 -1), PRBS15 (waveform length: 2 15 -1), PRBS20 (waveform length: 2 20 -1) and other periodic waveforms such as various pseudo-random waveforms (PRBS: Pseudo Random Bit Sequence); PRBS13Q, PRBS31Q, SSPRQ and other evaluation waveforms for evaluating PAM; scrambled idle waveforms with RS-FEC (Reed-Solomon Forward Error Correction) code.

[0061] The signal synthesis output unit 2c outputs a PAM4 signal by superimposing the most significant bit string signal generated by the first signal generating unit 2a and the least significant bit string signal generated by the second signal generating unit 2b. When measuring the bit error rate of the object under test W, the PAM4 signal is input to the object under test W as a test signal with a known waveform.

[0062] In addition, the errors inserted into the test signal are arbitrary. For example, when checking the FEC error tolerance of the object under test W, an arbitrary FEC symbol error is inserted. Also, when confirming the tolerance of the object under test W, an error is inserted, and when the object under test W confirms the error through another arbitrary test signal, the error is not inserted and confirmed through the capture function.

[0063] When the reference data, i.e., the NRZ signal or the PAM4 signal, is input from the signal generator 2 as a test signal of a known waveform to the object under test W, the bit error detector 3 receives the signal output from the object under test W accompanying the input of the NRZ signal or the PAM4 signal and measures the bit error rate, etc. Figure 1 As shown, the error detector 3 includes a signal receiving unit 3a, a synchronization detecting unit 3b, a position information storage unit 3c, a data comparing unit 3d, and a data storage unit 3e.

[0064] When the test signal input to the object under test W is an NRZ signal, the signal receiving unit 3a samples the NRZ signal received from the object under test W at a predetermined sampling period and converts it into bit string data (bit string data consisting of 0 and 1). The bit string data converted by the signal receiving unit 3a is input to the synchronization detection unit 3b.

[0065] When the test signal input to the object under test W is a PAM4 signal, the signal receiving unit 3a samples the PAM4 signal received from the object under test W at a predetermined sampling period and converts it into symbol string data (symbol string data consisting of symbol values ​​of 0, 1, 2, and 3). The symbol string data converted by the signal receiving unit 3a is input to the synchronization detection unit 3b.

[0066] When the test signal input to the object under test W is an NRZ signal, the synchronization detection unit 3b obtains the data of the bit string of the NRZ signal serving as a reference read from the storage unit 5, i.e., the reference data, and synchronizes and reads in the bit string data of the NRZ signal received from the object under test W and output from the signal receiving unit 3a according to the set timing pre-set by the operating unit 4, and outputs the read bit string data serving as input data to the data comparison unit 3d.

[0067] When the test signal input to the object under test W is a PAM4 signal, the synchronization detection unit 3b obtains the synchronization of the symbol string data of the PAM4 signal serving as a reference read from the storage unit 5, i.e., the reference data, and the symbol string data of the PAM4 signal received from the object under test W and output from the signal receiving unit 3a, and reads them in according to the set timing pre-set by the operating unit 4, and outputs the read symbol string data serving as input data to the data comparison unit 3d.

[0068] The set timing is pre-set, for example, on a setting screen (not shown) of the display unit 6 through the operation unit 4, and is the timing for generating a trigger signal according to a user's command, the timing for generating a specified number of FEC symbol errors in 1 codeword length (for example, 1 codeword = 544 FEC symbols, when the user wants to capture at the timing when 16 FEC symbol errors are generated, synchronization is achieved at the timing when 16 / 544 FEC symbol errors are generated), and the timing when a specified number of FEC symbol errors are generated continuously (regardless of the codeword, synchronization is achieved at the timing when a number of consecutive FEC symbol errors specified by the user are generated).

[0069] The synchronization detection unit 3b detects the alignment mark information based on the bit string data or symbol string data received by the signal receiving unit 3a, obtains the code word start symbol information based on the detected alignment mark information, and notifies the position information storage unit 3c of the obtained code word start symbol information.

[0070] The alignment mark information can be obtained by detecting an alignment mark waveform included in a scrambled code idle waveform appearing at a predetermined period as a waveform for channel identification in a well-known order in accordance with the communication standard.

[0071] The codeword start symbol information is a value indicating how many FEC symbols before the FEC symbol position data the start symbol of the codeword exists.

[0072] The FEC symbol position, that is, the start of one FEC symbol of the bit sequence data or the symbol sequence data is detected by automatically running the counter of the data comparison unit 3d to assume the start.

[0073] Furthermore, the codeword start symbol information can be pre-stored in the storage unit 5 as FPGA information based on a fixed value by the bit error rate measurement device 1, and read by the control unit 7 as needed.

[0074] When synchronization is achieved, the synchronization detection unit 3b notifies the data comparison unit 3d of the fact, and stores the synchronization position indicating the position of a bit or symbol in the reference data when synchronization is achieved in the position information storage unit 3c.

[0075] When the synchronization detection unit 3b obtains synchronization between the reference data and the bit string data of the NRZ signal or the symbol string data of the PAM4 signal from the signal receiving unit 3a, the position information storage unit 3c stores the synchronization position indicating the position of the bit or symbol in the reference data when synchronization is obtained. In addition, the position information storage unit 3c stores the codeword start symbol information notified by the synchronization detection unit 3b.

[0076] When the test signal input to the object under test W is an NRZ signal, the data comparison unit 3d captures the start of one FEC symbol (10 bits or 20 bits) of the bit string data that is synchronized with the reference data (test signal) at the set timing and read by the synchronization detection unit 3b, compares each bit with the error data ("1"), and detects errors for each code word length based on the code word start position calculated by the code word start position calculation mechanism 7a described later. That is, if the bit of the bit string data is "1", it is detected as an error. In addition, the start of one FEC symbol of the bit string data is detected by automatically running the counter of the data comparison unit 3d and assuming the start.

[0077] When the test signal input to the object under test W is an NRZ signal, the data comparison unit 3d segments the bit string data which is synchronized with the reference data (test signal) at the set timing and read by the synchronization detection unit 3b in units of one FEC symbol length (10 bits or 20 bits), and detects FEC symbol errors at intervals of one FEC symbol. For example, if the length of one FEC symbol is 10 bits, the bit string data is segmented in units of 10 bits, and even if an error occurs in one bit within 10 bits, it is detected as one FEC symbol error.

[0078] When the test signal input to the object under test W is a PAM4 signal, the data comparison unit 3d captures the start of one FEC symbol (10 bits or 20 bits) of the symbol string data which is synchronized with the reference data (test signal) at the set timing and read by the synchronization detection unit 3b, and segments it into the most significant bit string data (hereinafter referred to as MSB data) and the least significant bit string data (hereinafter referred to as LSB data) by the data segmentation unit 3da, and compares the MSB data and the LSB data with the error data ("1"), respectively, and detects the most significant bit error (hereinafter referred to as MSB error) and the least significant bit error (hereinafter referred to as LSB error) of each codeword length respectively with the codeword start position calculated by the codeword start position calculation unit 7a described later as a reference. That is, if the segmented MSB data is "1", it is detected as an MSB error and counted, and if the segmented LSB data is "1", it is detected as an LSB error. The start of one FEC symbol of the symbol sequence data is detected by automatically running the counter of the data comparison unit 3d to assume the start.

[0079] When the test signal input to the test object W is a PAM4 signal, the data comparison unit 3d segments the MSB data and LSB data in units of one FEC symbol length (10 bits or 20 bits), and detects FEC symbol errors in the MSB data and LSB data at intervals of one FEC symbol. For example, if the length of one FEC symbol is 10 bits, the MSB data and LSB data are segmented in units of 10 bits, and even if an error occurs in 1 bit within 10 bits, it is detected as an FEC symbol error.

[0080] In addition, Figure 1 In the description, for the sake of convenience, the data comparison unit 3d is described as including the data segmentation mechanism 3da. However, the data segmentation mechanism 3da can be constituted by, for example, a well-known PAM decoder.

[0081] The data storage unit 3e stores bit string data or symbol string data synchronized with reference data, as well as comparison result data compared by the data comparison unit 3d and FEC symbol position data indicating the start of one FEC symbol of the bit string data or symbol string data.

[0082] The operation unit 4 also functions as a setting mechanism. Figure 1The bit error rate measuring device 1 is composed of a user interface such as an operation knob, various keys, switches, buttons, and soft keys on the display screen of the display unit 6. The operation unit 4 sets the FEC codeword length, FEC symbol length, and setting timing based on the communication standard; sets the FEC symbol error threshold; specifies the code block of the captured data (bit string data or symbol string data) displayed on the display screen of the display unit 6, sets the baud rate, and the bit string or symbol string generation conditions; and sets various settings related to the bit error rate measurement such as commands for starting and ending the bit error rate measurement.

[0083] In addition, the FEC symbol error threshold can be arbitrarily set to a positive integer value including 0 by operating the operating unit 4. However, when performing FEC evaluation based on communication standards such as IEEE802.3ck, when the test signal input to the object under test W is an NRZ signal, the FEC symbol error threshold is set to "8", and when the test signal input to the object under test W is a PAM4 signal, the FEC symbol error threshold is set to "16", and it is possible to evaluate whether the test signal input to the object under test W complies with the communication standard.

[0084] The storage unit 5 stores the symbol string data read from the signal receiving unit 3a in units of code blocks according to the preset setting timing with the pre-allocated storage capacity under the control of the control unit 7. In the present embodiment, a symbol string data block that can be displayed in one display area (including the display size of the scrolling display) of the display unit 6 is set as one code block. For example, when the allocated storage capacity is 8 Mbits (equivalent to 4 Msymbols of the symbol string data) and the symbol string data block that can be displayed in one display area of ​​the display unit 6 is set as one code block, as one code block = 65536 bits = 32768 symbols, the 4 Msymbol symbol string data is segmented with a pre-set specified number of segments (any of 1, 2, 4, 8, 16, 32, 64, 128) and stored in the storage unit 5.

[0085] The maximum number of segments of the symbol string data is determined by the storage capacity allocated to the storage unit 5. For example, if the storage capacity allocated to the storage unit 5 is 8 Mbits, the maximum number of segments of the symbol string data is 128 segments.

[0086] The storage unit 5 stores the bit string of the NRZ signal or the symbol string of the PAM4 signal (a symbol string consisting of symbol values ​​of 0, 1, 2, and 3) input to the device under test W as the test signal of the known waveform from the signal synthesis output unit 2c. The bit string of the NRZ signal or the symbol string of the PAM4 signal input to the device under test W as the test signal of the known waveform becomes reference data to be compared with input data generated based on the signal received from the device under test W.

[0087] The storage unit 5 stores the counting result of the error counting mechanism 7b described later by the control unit 7. The storage unit 5 stores information such as setting timing, baud rate, bit string, and symbol string generation conditions. These information can be appropriately selected and set by the operation unit 4 through the user interface.

[0088] In addition, it can be constructed as follows: in the control unit 7 or the signal generator 2, when the bit string of the NRZ signal or the symbol string of the PAM4 signal that becomes the test signal can be grasped, the test signal of a known waveform, i.e., the bit string of the NRZ signal or the symbol string of the PAM4 signal, i.e., the reference data, is stored from the control unit 7 or the signal generator 2 to the storage unit 5.

[0089] The display unit 6 is composed of Figure 1 The bit error rate measuring device 1 is provided with a liquid crystal display, etc., and displays the setting screen related to the bit error rate measurement, various conformity tests including the bit error rate measurement (a test to determine whether the object W under test conforms to the communication standard), and the captured screen, etc., under the control of the display control mechanism 7d described later. In addition, the display unit 6 also has the operation functions of the operation unit 4, such as the soft keys on the display screen.

[0090] Furthermore, the display unit 6 is controlled by a display control mechanism 7d described later, for example, Figure 2 or Figure 3 The captured error map screen (hereinafter referred to as map screen) 21 is displayed in the manner shown. Figure 2 The mapping screen 21 shows the case where a PAM4 signal is input to the object under test W. Figure 3 The mapping screen 21 shows a case where an NRZ signal is input to the object W under test.

[0091] Here, as the map screen 21, Figure 2 For example, Figure 3 In the mapping screen 21, Figure 2 The same components are denoted by the same reference numerals, and their description is omitted.

[0092] Figure 2 FIG. 2 shows an example of a map screen 21 of the display unit 6 when a PAM4 signal is input to the object under test W. Figure 2A mapping area 22 is formed in the mapping diagram screen 21 to identify and display symbol string data in units of FEC symbol length according to whether there is an FEC symbol error. "Block No.", "Block Length", "Trigger Position" and "View Length" are displayed in the upper right area of ​​the error mapping area 22. An input box 23 is displayed in "Block No.", and a numerical value is input for inputting the code block number of the data displayed in the error mapping area 22. The size (length) of the data for one code block is displayed in "Block Length". The trigger position is displayed in "Trigger Position". Figure 2 In the example, "1" is entered in the "BlockNo." input box 23, "Block Length" is displayed as "32760" PAM4 Symbol, and "TriggerPosition" is displayed as "1" Codeword "0" FEC Symbol. An input box 24 is displayed in "View Length", and the length of one row of the displayed data is entered as a numerical value. Figure 2 In the example shown in FIG. 2 , “256” is input in the “View Length” input box 24, and the area length of one line of display data is “256”. In addition, the number of segments (e.g., 1 to 128) input to the code block determined according to the storage capacity of the storage unit 5 can be set in the “Block No.” input box 23.

[0093] The area below "View Length" on the map screen 21 displays "Position", which indicates the position of the cursor 25 in the error map area 22. In "Position", "Codeword" and "Pos." indicate which FEC symbol of which codeword the cursor 25 has selected, and "Row" and "Column" indicate the coordinate position of the cursor 25 on the horizontal axis (row) and vertical axis (digit) on the error map area 22.

[0094] "FEC Symbol Error" is displayed in the area below "Position" on the map screen 21. "FEC Symbol Error" is displayed by color differentiation to identify whether there is an FEC symbol error. Figure 2 In the example of Figure 2 In the right slash part), when there is an FEC symbol error only in the LSB, for example, it is displayed in yellow (in Figure 2 In the left slash part), when there is an FEC symbol error in both the MSB and the LSB, for example, it is displayed in orange (in Figure 2 in the figure, blackened part).

[0095] In addition, if Figure 3 As shown, in the "FEC Symbol Error" of the mapping diagram screen 21 when an NRZ signal is input to the object under test W, only when there is an FEC symbol error, for example, it is displayed in red (in Figure 3 (in the figure, the right slash part).

[0096] In the area below “FEC Symbol Error” on the map screen 21 , up, down, left, and right arrow keys 26 are displayed as “FEC Symbol Error Search” for searching for FEC symbol errors starting from the position of the cursor 25 and moving the cursor 25 to the searched position.

[0097] In the area below "FEC Symbol Error Search" on the map screen 21, "Uncorrectable Codewords Search" is displayed to move the cursor 25 by searching for the start error of the desired codeword that becomes an Uncorrectable codeword through the search mechanism 7c described later of the control unit 7. In "Uncorrectable Codewords Search", a soft key 27 for moving the cursor 25 to the position of the start error of the first Uncorrectable codeword in the code block, a soft key 28 for moving the cursor 25 to the position of the start error of the previous Uncorrectable codeword in the code block with the position of the cursor 25 as the starting point, a soft key 29 for moving the cursor 25 to the position of the start error of the next Uncorrectable codeword in the code block with the position of the cursor 25 as the starting point, and a soft key 30 for moving the cursor 25 to the position of the start error of the last Uncorrectable codeword in the code block are displayed.

[0098] A magnifying glass button 31 is displayed in the area below "Uncorrectable Codewords Search" on the map screen 21 to enlarge / reduce the screen.

[0099] In the error map area 22 of the map screen 21, the presence or absence of FEC symbol errors in the symbol string data is identified and displayed in units of FEC symbol length. To further explain, the display area of ​​the identification display of the error map area 22 sets one area to one FEC symbol length, and the area length on the horizontal axis is made consistent with the codeword length. For example, if the codeword length is set to 544 and the FEC symbol length is set to 10 bits, then since one area is set to one FEC symbol, the "View Length" is set to 544. That is, the "View Length" is fixed to one codeword length.

[0100] Therefore, in the case of a mode in which the PAM4 signal is input to the object under test W, if the FEC symbol length is 10 bits, one region is represented by 20 bits of the FEC symbol calculated by summing up the MSB / LSB. If the FEC symbol length is 20 bits, one region is represented by 40 bits of the FEC symbol calculated by summing up the MSB / LSB.

[0101] Furthermore, in the case of a mode in which an NRZ signal is input to the device under test W, if the FEC symbol length is 10 bits, one area is represented by a 10-bit FEC symbol, and if the FEC symbol length is 20 bits, one area is represented by a 20-bit FEC symbol.

[0102] Furthermore, the captured symbol string data is displayed in a separate row in codeword length units, and one codeword is displayed in one row, so that the start of the codeword is located at the left end of the error mapping area 22 when the FEC symbol length unit is used to identify whether there is an FEC symbol error, and the end of the codeword is located at the right end of the error mapping area 22. For example, Figure 2 The 5th row of codewords indicates that an FEC symbol error exists only in the LSB of the symbol string data of the 1st and 2nd FEC symbols from the left end represented by the left slash; indicates that an FEC symbol error exists only in the MSB of the symbol string data of the 5th to 7th and the 251st to 254th FEC symbols from the left end represented by the right slash; and indicates that an FEC symbol error exists in both the MSB and LSB of the symbol string data of the 11th to 20th FEC symbols from the left end represented by the blackening.

[0103] In addition, data segmented for each code word that cannot be completely displayed in the error mapping area 22 can be checked by scrolling using the scroll bar 32 on the right side so that the data is displayed in the error mapping area 22 .

[0104] "Codeword Number" is displayed on the left side of the error mapping area 22. "Codeword Number" is composed of a plurality of display areas 33 arranged in parallel in the digit direction (column direction) corresponding to the code words in each row of the error mapping area 22. In "Codeword Number", the display area 33 corresponding to the row of the code word counted as the Uncorrectable code word by the error counting mechanism 7b described later is identified. Figure 2 In the example, the codeword counts of the 5th and 11th rows of the error mapping area 22 are Uncorrectable codewords, so the display area 33 of the 5th and 11th rows of the "Codeword Number" corresponding to these rows is identified and displayed in red (in Figure 2 In this way, the row of code words counted as Uncorrectable code words can be easily confirmed.

[0105] In addition, when the data segmented for each codeword displayed in the error map area 22 is scrolled using the scroll bar 32, the display area 33 of "Codeword Number" is scrolled in conjunction with the scroll bar 32. In addition, in the display area 33 of "Codeword Number", the row that is not an Uncorrectable codeword is identified and displayed in water color, for example, and the row that has less than one codeword is identified and displayed in a predetermined color such as gray. At this time, if the display area 33 corresponding to the codeword of the row counted as the Uncorrectable codeword is highlighted in a conspicuous color such as red, the position of the codeword counted as the Uncorrectable codeword can be confirmed at a glance.

[0106] Furthermore, the display area 33 of "Codeword Number" can also be displayed by marking numbers in sequence from the top corresponding to the codewords of each row of the error mapping area 22. Figure 2 As shown in the figure, the display area 33 of "Codeword Number" is marked with numbers from the top, such as setting the display area 33 corresponding to the first row of codewords in the error mapping area 22 to "00000", setting the display area 33 corresponding to the second row of codewords in the error mapping area 22 to "00001", and setting the display area 33 corresponding to the third row of codewords in the error mapping area 22 to "00002". Thus, when the display area 33 corresponding to the codeword of the row counted as the Uncorrectable codeword is identified and displayed, it is possible to easily confirm which codeword it is based on the numerical value by observing the number assigned to the display area 33.

[0107] Alternatively, the code words in each row of the error map area 22 may be numbered sequentially from the top, and all numbers corresponding to the rows of code words counted as uncorrectable code words may be displayed in a blank area of ​​the map screen 21 or on another screen.

[0108] Furthermore, when the error map area 22 is displayed at a reduced size of more than 1 times using the magnifying glass button 31 and the number of the display area 33 is difficult to read, it is preferable not to display the number of the display area 33. At this time, if the cursor 25 is moved to the codeword of the row counted as the Uncorrectable codeword, the row whose codeword is counted as the Uncorrectable codeword can be determined based on the "Codeword" and "Pos." of the "Position".

[0109] Displayed at the bottom of the error mapping area 22 in the mapping screen 21 are a soft key 34 for commanding the display of the data of the initial code block in the error mapping area 22, a soft key 35 for commanding the display of the data of the previous code block in the error mapping area 22, a soft key 36 for commanding the display of the data of the next code block in the error mapping area 22, and a soft key 37 for commanding the display of the data of the last code block in the error mapping area 22.

[0110] In the lower area of ​​the map screen 21, "Captured Codewords" and "Uncorrectable Codewords" are displayed as the total result of the Uncorrectable codewords. In "Captured Codewords", as the total result, the total number of captured codewords "xxx" is displayed in one display frame 38, and the number of Uncorrectable codewords "yyy" is displayed in another display frame 39. Thus, the number of Uncorrectable codewords relative to the total number of captured codewords can be visually confirmed.

[0111] The control unit 7 is composed of storage elements such as a central processing unit (CPU), ROM, RAM, etc., for example, in order to measure the bit error rate of the PAM4 signal, and centrally controls the signal generator 2, the bit error detector 3, the operating unit 4, the storage unit 5 and the display unit 6, and has a code word starting position calculation mechanism 7a, an error counting mechanism 7b, a search mechanism 7c and a display control mechanism 7d.

[0112] The codeword start position calculation unit 7a calculates the codeword start position based on the setting information based on the operation unit 4, the codeword start symbol information stored in the position information storage unit 3c, and the FEC symbol position stored in the data storage unit 3e.

[0113] To further explain, the codeword starting position calculation mechanism 7a calculates the codeword starting position by the calculation formula of FEC symbol position - (codeword starting symbol information: FEC symbol length) ... formula (1) based on the FEC symbol length (10 bits or 20 bits) set by the operating unit 4, the codeword starting symbol information stored in the position information storage unit 3c through the notification from the synchronization detection unit 3b, and the FEC symbol position stored in the data storage unit 3e through the notification from the data comparison unit 3d.

[0114] When the test signal input to the object under test W is an NRZ signal, the error counting mechanism 7b counts the errors detected by the data comparison unit 3d (including the count of codewords). Furthermore, the error counting mechanism 7b counts the FEC symbol errors detected by the data comparison unit 3d at intervals of one FEC symbol. Furthermore, when the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism 7b counts it as an Uncorrectable codeword for which forward error correction cannot be performed.

[0115] When the test signal input to the object under test W is a PAM4 signal, the error counting mechanism 7b counts the MSB errors and LSB errors (including the count of the codeword) detected by the data comparison unit 3d. In addition, the error counting mechanism 7b counts the FEC symbol errors detected by the data comparison unit 3d at an interval of one FEC symbol. In addition, when the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism 7b counts it as an Uncorrectable codeword that cannot perform forward error correction.

[0116] Search for agency 7c in Figure 2 or Figure 3 In the mapping screen 21 of FIG. 2 , with the cursor 25 at any position in the error mapping area 22 (any position in the row of any codeword) as the starting point, any of the four soft keys 27, 28, 29, and 30 of the aforementioned "Uncorrectable Codewords Search" is operated to search for the starting error of the uncorrectable codeword, and the cursor 25 is moved to the searched position. For example, in Figure 2 In the mapping diagram screen 21, if the soft key 29 is pressed when the cursor 25 is located at the starting error of the 5th row of code words counted as Uncorrectable code words, the starting error of the next Uncorrectable code word, i.e., the 11th row of code words, is searched starting from the position of the cursor 25, and the cursor 25 is moved to the searched position.

[0117] The display control mechanism 7d performs, for example, Figure 2 or Figure 3In addition to the display control of the mapping diagram screen 21, the display control of the display screen of the display unit 6 is also performed, including a setting screen for various settings required for bit error rate measurement, a capture screen of bit string data or symbol string data obtained from the object under test W as a result of inputting a PAM4 signal or an NRZ signal to the object under test W, and display control of movement of the cursor 25 based on the operation of the operating unit 4 (soft keys 34, 35, 36, 37).

[0118] Next, as a processing operation until the bit error rate measurement device 1 configured as above counts FEC symbol errors in FEC symbol units and identifies and displays them on the map screen 21, refer to Figure 4 The following description will be given by taking the case where a test signal of a PAM4 signal is input to a test object W as an example.

[0119] like Figure 4 As shown, first, the setting parameters for the received signal from the object under test W are set through the operating unit 4 (ST1). Specifically, in the setting screen of the display unit 6, one codeword length, one FEC symbol length and FEC symbol error threshold are set according to the communication standard of the object under test W, or a preset setting corresponding to the communication standard of the object under test W is selected (for example, 50GPAM4, etc.).

[0120] After the above settings are completed, a PAM4 signal (such as 50G PAM4 matching the set parameters) with an erroneous known waveform inserted by the signal generator 2 is input as a test signal to the object under test W (ST2).

[0121] Then, a signal returned from the device under test W accompanying the input of the test signal to the device under test W is received by the signal receiving unit 3a and converted into symbol string data, and the converted symbol string data is stored in the storage unit 5 (ST3).

[0122] Next, the codeword starting position (ST4) is calculated according to the calculation formula of formula (1), which is a calculation formula based on the FEC symbol length set by the operation unit 4, the codeword starting symbol information stored in the position information storage unit 3c, and the FEC symbol position stored in the data storage unit 3e.

[0123] Next, the start of one FEC symbol (10 bits or 20 bits) of the symbol string data read from the storage unit 5 in synchronization with the reference data (test signal) at the set timing is captured and segmented into MSB data and LSB data by the data segmentation mechanism 3da (ST5). In addition, the start of one FEC symbol of the symbol string data is detected by automatically running the counter of the data comparison unit 3d to assume the start.

[0124] Next, the data comparison unit 3d compares the MSB data and the LSB data with the error data ("1"), and detects the MSB error and the LSB error for each codeword length based on the codeword start position calculated by the codeword start position calculation unit 7a, and counts the detected MSB error and the LSB error for each codeword length by the error counting unit 7b (ST6). At this time, the number of codewords is also counted.

[0125] In addition, the error data ("1") is segmented into error data for comparison with the MSB data and error data for comparison with the LSB data. If the MSB data is "1", it is detected as an MSB error and counted. If the LSB data is "1", it is detected as an LSB error and counted.

[0126] Then, the MSB data and the LSB data are segmented in units of one FEC symbol length, and FEC symbol errors are detected in the MSB data and the LSB data at one FEC symbol interval, and the detected FEC symbol errors are counted by the error counting mechanism 7b (ST7). For example, if the length of one FEC symbol is 10 bits, the MSB data and the LSB data are segmented in units of 10 bits, and even if an error occurs in one bit within 10 bits, it is detected as one FEC symbol error and counted.

[0127] Then, if Figure 2 As shown, as a code word error display, the captured symbol string data is controlled by the display control mechanism 7d to identify and display whether there is an FEC symbol error in the unit of FEC symbol length, and one code word is displayed in a new line in the unit of code word length, so that the start of the code word calculated by the code word starting position calculation mechanism 7a is located at the left end of the error mapping area 22, and the end of the code word is located at the right end of the error mapping area 22 (ST8).

[0128] Next, as a processing operation until the bit error rate measurement device 1 configured as above counts FEC symbol errors in FEC symbol units and identifies and displays them on the map screen 21, refer to Figure 5 The following description will be given by taking as an example the case where a test signal of an NRZ signal is input to the object under test W.

[0129] like Figure 5 As shown, first, the setting parameters for the reception signal from the object under test W are set through the operation unit 4 (ST11). Specifically, in the setting screen of the display unit 6, one codeword length, one FEC symbol length and FEC symbol error threshold are set according to the communication standard of the object under test W, or a preset setting corresponding to the communication standard of the object under test W is selected and set (for example, 25GNRZ, etc.).

[0130] After the above settings are completed, an NRZ signal (such as 25G NRZ matching the setting parameters) with a known waveform into which an error is inserted is input as a test signal to the object under test W by the signal generator 2 (ST12).

[0131] Then, a signal returned from the device under test W accompanying the input of the test signal to the device under test W is received by the signal receiving unit 3a and converted into bit string data, and the converted bit string data is stored in the storage unit 5 (ST13).

[0132] Next, the codeword starting position is calculated (ST14) according to the calculation formula of formula (1), which is a calculation formula based on the FEC symbol length set by the operating unit 4, the codeword starting symbol information stored in the position information storage unit 3c, and the FEC symbol position stored in the data storage unit 3e.

[0133] Next, the start of one FEC symbol (10 bits or 20 bits) of the bit string data read from the storage unit 5 in synchronization with the reference data (test signal) at the set timing is captured, and each bit is compared with the error data ("1") by the data comparison unit 3d. The error of each code word length is detected based on the code word start position calculated by the code word start position calculation unit 7a, and the detected errors of each code word length are counted by the error counting unit 7b (ST15). At this time, the number of code words is also counted. In addition, the start of one FEC symbol of the bit string data is detected by automatically running the counter of the data comparison unit 3d and assuming the start.

[0134] Next, the bit string data is segmented in units of one FEC symbol length, FEC symbol errors are detected at one FEC symbol interval, and the detected FEC symbol errors are counted by the error counting mechanism 7b (ST16). For example, if one FEC symbol length is 10 bits, the bit string data is segmented in units of 10 bits, and even if an error occurs in one bit within the 10 bits, it is detected as one FEC symbol error and counted.

[0135] Then, if Figure 3 As shown, as a code word error display, the captured bit string data is controlled by the display control unit 7d to identify and display whether there is an FEC symbol error in the unit of FEC symbol length, and one code word is displayed in a new line in the unit of code word length, so that the start of the code word calculated by the code word starting position calculation unit 7a is located at the left end of the error mapping area 22, and the end of the code word is located at the right end of the error mapping area 22 (ST17).

[0136] Then, in Figure 2 or Figure 3In the map screen 21, when the cursor 25 is moved to a codeword that becomes an Uncorrectable codeword, any one of the four soft keys 27, 28, 29, and 30 of "Uncorrectable Codewords Search" arranged on the map screen 21 is operated.

[0137] For example, Figure 2 or Figure 3 As shown in the mapping diagram screen 21, if the soft key 29 is pressed when the cursor 25 is located at the position of the starting error of the 7th row of code words that becomes the Uncorrectable code words in the code block of the error mapping area 22, the cursor 25 moves to the position of the starting error of the next Uncorrectable code word in the code block of the error mapping area 22, that is, the starting error of the 11th row of code words that becomes the Uncorrectable code words.

[0138] In addition, when the cursor 25 is located Figure 2 or Figure 3 When the soft key 27 is pressed in the state of the position shown in the mapping diagram screen 21, the cursor 25 moves to the position of the start error of the first Uncorrectable codeword (the 5th line codeword) in the code block of the error mapping area 22. And, when the soft key 28 is pressed, the cursor 25 moves to the position of the start error of the previous Uncorrectable codeword (the 5th line codeword) in the code block of the error mapping area 22. And, when the soft key 30 is pressed, the cursor 25 moves to the position of the start error of the last Uncorrectable codeword in the code block of the error mapping area 22.

[0139] However, in the above embodiment, if Figure 1 As shown in the figure, the bit error rate measuring device 1 is configured to integrally include the signal generator 2, the bit error detector 3, the operating unit 4, the storage unit 5, the display unit 6, and the control unit 7, but the present invention is not limited to this configuration. For example, the signal generator 2 and the bit error detector 3 may be modularized or provided as separate housings, and the operating unit 4 and the display unit 6 may be configured by an external device such as a personal computer connected to the outside.

[0140] Thus, according to the present embodiment, in the map screen 21 of the error mapping, the captured data (bit string data or symbol string data) is identified and displayed in FEC symbol length units according to whether or not there is an FEC symbol error (occurrence / non-occurrence of an FEC symbol error). At this time, a new line is started in the codeword length unit and display control is performed so that the start of one codeword identified and displayed is located at the left end of the error mapping area 22, and the end of one codeword identified and displayed is located at the right end of the error mapping area 22. Thus, one codeword is displayed in one line, so that the user can easily determine the segmentation of the codeword and can also easily confirm the error occurrence status of the FEC symbol length unit of each codeword.

[0141] Furthermore, the codewords in the row where the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold are set as Uncorrectable codewords for which forward error correction cannot be performed, and the row of the display area 33 corresponding to and linked to the row of the Uncorrectable codeword is identified and displayed. Thus, when the number of FEC symbol errors in the data segmented per codeword exceeds the FEC symbol error threshold, it is possible to easily understand where the row of the Uncorrectable codeword is located.

[0142] Furthermore, the total number of codewords and the number of Uncorrectable codewords are displayed on the display unit 6. Thus, the occurrence ratio of Uncorrectable codewords relative to all codewords can be known. In addition, in summary, the user can easily find out the cause of the defect of the object under test, thereby being able to perform effective troubleshooting.

[0143] The above describes the preferred embodiment of the bit error rate measuring device and the codeword error display method according to the present invention, but the present invention is not limited to the description and drawings based on the embodiment. That is, it is obvious that other embodiments, examples and application technologies implemented by those skilled in the art according to the embodiment are all included in the scope of the present invention.

[0144] Explanation of symbols

[0145] 1-bit error rate measuring device, 2-signal generator, 2a-first signal generating unit, 2b-second signal generating unit, 2c-signal synthesis output unit, 3-bit error detector, 3a-signal receiving unit, 3b-synchronization detection unit, 3c-position information storage unit, 3d-data comparison unit, 3da-data segmentation mechanism, 3e-data storage unit, 4-operation unit, 5-storage unit, 6-display unit, 7-control unit, 7a-code word starting position calculation mechanism, 7b-error counting mechanism, 7c-search mechanism, 7d-display control mechanism, 21-mapping screen (capturing error mapping screen), 22-error mapping area, 23, 24-input box, 25-cursor, 26-arrow keys, 27, 28, 29, 30-soft keys, 31-magnifying glass button, 32-scroll bar, 33-display area, 34, 35, 36, 37-soft keys, 38, 39-display box, W-measured object.

Claims

1. A bit error rate measuring device, which inputs an NRZ signal of a known waveform as a test signal into a device under test (W), receives a signal from the device under test accompanying the input of the test signal, and determines whether a FEC operation of the device under test can be performed based on a comparison result between the received signal and the test signal, the bit error rate measuring device (1) comprising: An operating unit (4) is configured to set the FEC codeword length, FEC symbol length and FEC symbol error threshold according to the communication standard of the object under test; an error counting mechanism (7b) for counting FEC symbol errors detected at one FEC symbol interval based on a comparison result of comparing each bit of the bit string data received and converted from the signal of the object under test with the error data, and counting the number of FEC symbol errors in one codeword as an Uncorrectable codeword for which forward error correction cannot be performed when the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold; and A display unit (6) identifies and displays the bit string data in FEC symbol length units based on the counting result of the error counting mechanism and the presence or absence of FEC symbol errors, The bit error rate measuring device is characterized by comprising: The display control mechanism (7d) sets a region of the display area of ​​the identification display of the display unit to the length of one FEC symbol, so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and performs display control in a new row in units of codeword length, so that the beginning of one codeword of the identification display is located at the left end of the display area, and the end of one codeword of the identification display is located at the right end of the display area.

2. A bit error rate measuring device, which inputs a PAM4 signal of a known waveform as a test signal into a device under test (W), receives a signal from the device under test accompanying the input of the test signal, and determines whether a FEC operation of the device under test can be performed based on a comparison result between the received signal and the test signal, the bit error rate measuring device (1) comprising: An operating unit (4) is configured to set the FEC codeword length, FEC symbol length and FEC symbol error threshold according to the communication standard of the object under test; an error counting mechanism (7b) for counting FEC symbol errors detected at one FEC symbol interval of the most significant bit string data and the least significant bit string data of the symbol string data received and converted from the signal of the object under test according to a comparison result of comparing the most significant bit string data and the least significant bit string data of the symbol string data with the error data, and when the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, counting it as an Uncorrectable codeword for which forward error correction cannot be performed; and A display unit (6) identifies and displays the symbol string data in FEC symbol length units based on the counting result of the error counting mechanism and the presence or absence of FEC symbol errors, The bit error rate measuring device is characterized by comprising: The display control mechanism (7d) sets a region of the display area of ​​the identification display of the display unit to the length of one FEC symbol, so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and performs display control in a new row in units of codeword length, so that the beginning of one codeword of the identification display is located at the left end of the display area, and the end of one codeword of the identification display is located at the right end of the display area.

3. The bit error rate measuring device according to claim 1 or 2, characterized in that: The display unit (6) has a multi-line display area (33) which is numbered corresponding to each line of the identification display and is linked to the scrolling display of the identification display. The display control mechanism (7d) sets the codeword of a row in which the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold as the Uncorrectable codeword, and controls the display unit (6) so that it identifies and displays the display area of ​​the row corresponding to the Uncorrectable codeword.

4. The bit error rate measuring device according to claim 3, characterized in that: The display control means (7d) controls the display unit (6) to display a total result based on the total number of code words and the number of Uncorrectable code words.

5. A code word error display method, which is a code word error display method of a bit error rate measuring device (1), wherein the bit error rate measuring device (1) inputs an NRZ signal of a known waveform as a test signal into a device under test (W), and receives a signal from the device under test accompanying the input of the test signal, and determines whether a FEC operation of the device under test can be performed based on a comparison result between the received signal and the test signal, the code word error display method comprising the following steps: By means of an operating unit (4), the FEC codeword length, FEC symbol length and FEC symbol error threshold are set according to the communication standard of the object under test; By means of an error counting mechanism (7b), FEC symbol errors detected at one FEC symbol interval are counted based on a comparison result of comparing each bit of the bit string data received and converted from the signal of the object under test with the error data; When the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism counts the codeword as an Uncorrectable codeword that cannot perform forward error correction; and According to the counting result of the error counting mechanism and the presence or absence of FEC symbol errors, the symbol string data is identified and displayed on a display unit (6) in units of FEC symbol length, The code word error display method of the bit error rate measuring device is characterized by comprising the following steps: A region of the display area of ​​the identification display of the display unit is set to the length of one FEC symbol so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and display control is performed by starting a new line in units of codeword length through a display control mechanism (7d) so that the start of one codeword of the identification display is located at the left end of the display area and the end of one codeword of the identification display is located at the right end of the display area.

6. A codeword error display method, which is a codeword error display method of a bit error rate measuring device (1), wherein the bit error rate measuring device (1) inputs a PAM4 signal of a known waveform as a test signal into a device under test (W), and receives a signal from the device under test accompanying the input of the test signal, and determines whether a FEC operation of the device under test can be performed based on a comparison result between the received signal and the test signal, the codeword error display method comprising the following steps: By means of an operating unit (4), the FEC codeword length, FEC symbol length and FEC symbol error threshold are set according to the communication standard of the object under test; By means of an error counting mechanism (7b), FEC symbol errors detected at one FEC symbol interval of the most significant bit string data and the least significant bit string data of the symbol string data received and converted from the signal of the object under test are counted according to the comparison result of comparing the most significant bit string data and the least significant bit string data with the error data respectively; When the number of the FEC symbol errors in one codeword exceeds the FEC symbol error threshold, the error counting mechanism counts the codeword as an Uncorrectable codeword that cannot perform forward error correction; and According to whether there is an FEC symbol error, the symbol string data received from the signal of the test object and converted is identified and displayed on the display unit (6) in FEC symbol length units, The code word error display method of the bit error rate measuring device is characterized by comprising the following steps: A region of the display area of ​​the identification display of the display unit is set to the length of one FEC symbol so that the length of the horizontal axis of the display area is consistent with the length of one codeword, and display control is performed by starting a new line in units of codeword length through a display control mechanism (7d) so that the start of one codeword of the identification display is located at the left end of the display area and the end of one codeword of the identification display is located at the right end of the display area.

7. The codeword error display method according to claim 5 or 6, characterized in that: The steps include: Displaying a multi-line display area (33) on the display unit (6) with numbers corresponding to the lines of the identification display and linked to the scrolling display of the identification display; and The codeword of a row in which the number of FEC symbol errors in one codeword exceeds the FEC symbol error threshold is set as the Uncorrectable codeword, and the display unit (6) is controlled by the display control mechanism (7d) so that it identifies and displays the display area of ​​the row corresponding to the Uncorrectable codeword.

8. The codeword error display method according to claim 7, characterized in that: The steps include: The display control unit (7d) controls the display unit (6) so as to display a total result based on the total number of code words and the number of Uncorrectable code words.

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