Low dropout regulators for low-voltage applications

Abstract

A low-dropout regulator (1) for low-voltage applications includes a buffer circuit (500) disposed between the output terminal (O100) of an error amplifier (100) and the control node (C200) of a pass device (200). The buffer circuit (500) includes a driver comprising a first transistor (11) implemented as an NMOS transistor. The output terminal (O100) of the error amplifier (100) is coupled to the control node (C11) of the first transistor (11). The control node (C200) of the pass device (200) is coupled to an internal node (N1) comprising a first current path (10) of the first transistor (11). The low-dropout regulator (1) exhibits high load capacity even when the input supply voltage is very low.

Description

Technical Field

[0001] This invention relates to a low-dropout regulator for low-voltage applications, and a communication device including a low-dropout regulator that provides a regulated output voltage for powering electronic circuitry within the communication device. Background Technology

[0002] Low-dropout regulators (LDOs) are used for power management in most battery-powered portable devices. Most integrated circuits require internal LDOs to convert the battery voltage into a stable internal power supply, a requirement of modules within the integrated circuit. The future development of electronic circuits increasingly favors the use of low supply voltages to drive high loads, thereby reducing standby power consumption and extending battery life.

[0003] The aim is to provide a design for a low-dropout regulator for low-voltage applications that can operate over a wide range of load currents and input supply voltages. Summary of the Invention

[0004] Claim 1 specifies an embodiment of a low-dropout regulator that can be used to provide a stable output voltage in low-voltage applications with a wide input power supply voltage range and a wide load current range.

[0005] The low-dropout regulator includes an input power terminal for providing an input power supply voltage and a reference power terminal for providing a reference power supply voltage. The low-dropout regulator also includes an error amplifier having a first input terminal, a second input terminal, and an output terminal. The low-dropout regulator includes a pass device with a control node for controlling the conductivity of a pass device, and a buffer circuit disposed between the output terminal of the error amplifier and the control node of the pass device.

[0006] The buffer circuit includes a first current path disposed between an input power supply terminal and a reference power supply terminal. The first current path includes a driver that includes a first transistor having a control node to control the conductivity of a first transistor. The first transistor is implemented as an NMOS transistor. The output terminal of the error amplifier is coupled to the control node of the first transistor. The control node of the pass device is coupled to a first internal node of the first current path located between the first transistor and the reference power supply terminal.

[0007] Even if the LDO specifications require a wide input voltage range and a wide load range with small output capacitance, the proposed LDO design can still be used. Furthermore, the proposed low-dropout regulator design enables circuit stabilization of the internal LDO with high efficiency and high load capacity; for example, it can drive an output load current greater than 100mA even when the output voltage needs to be very close to the input supply voltage and even when the input supply voltage is very low. In particular, the LDO design allows the use of low-dropout regulators in devices with low input supply voltage ranges (e.g., 1.1V, ..., 1.8V).

[0008] The first transistor has a drain node coupled to an input power supply terminal and a source node coupled to an internal node of a first current path. According to a preferred embodiment of the low-dropout regulator, the first transistor is configured as a source follower transistor. Specifically, the first transistor can be implemented as a native NMOS transistor.

[0009] According to another possible embodiment of the low-dropout regulator, the buffer circuit includes a second transistor disposed between a power supply terminal and an internal node of a first current path. The second transistor is configured as a PMOS transistor. The second transistor has a source node coupled to the power supply terminal and a drain node coupled to a first internal node of the first current path.

[0010] The second transistor is positioned between the power supply terminal and the first internal node of the first current path, enabling a buffer circuit with dynamic bias shunt feedback to reduce output resistance under different load currents.

[0011] According to an embodiment of the low dropout regulator, the first current path includes a current source disposed in the first current path between the power supply terminal and the first transistor.

[0012] According to an embodiment of a low-dropout regulator, the second transistor has a control node connected to a second internal node of the first current path. The second internal node of the first current path is disposed between the current source of the first current path and the first transistor.

[0013] According to a possible embodiment of a low-dropout regulator, the low-dropout regulator includes a third transistor disposed between a power supply terminal and a second internal node of a first current path. The third transistor has a source node connected to the power supply terminal and a drain node connected to the second internal node of the first current path. The third transistor has a control node for applying a control signal to control the conductivity of the third transistor.

[0014] A buffer circuit is configured to generate a control signal for controlling the conductivity of the third transistor in response to the amount of load current from the low-dropout regulator. Specifically, the buffer circuit is configured to sense the load current of the low-dropout regulator and compare the sensed load current with a constant current. Then, when the load current is very low, the comparison result is used to turn on the third transistor. The third transistor is configured as a PMOS switch. Therefore, since the source node of the third transistor is coupled to the control node of the second transistor, the second transistor is turned off when a low load current is detected to keep the first transistor in saturation.

[0015] According to a possible embodiment of a low-dropout regulator, the snubber circuit includes a current mirror configured to provide a bias current in a first current path of the snubber circuit. The snubber circuit includes a second current path. The current mirror is configured to provide a bias current in the first current path of the snubber circuit in response to a current in the second current path.

[0016] According to a possible embodiment of the low-dropout regulator, the buffer circuit includes a fourth transistor. The second current path includes a second current source disposed between the power supply terminal and the current mirror. The fourth transistor is disposed between the power supply terminal and the second current path, at a third internal node located between the second current source and the current mirror.

[0017] This configuration allows the snubber circuit's bias current to be adjusted in response to the sensed load current. In particular, this configuration allows the snubber circuit to operate with a higher bias current as the load current increases.

[0018] According to an embodiment of a low-dropout regulator, the low-dropout regulator includes an output current path that includes a pass device and an output terminal to provide a regulated output voltage. The low-dropout regulator also includes a feedback path that includes a capacitor disposed between the output terminal of an error amplifier and a third input terminal.

[0019] A capacitor is placed in the feedback path between the output terminal and the third input terminal of the error amplifier to provide Miller frequency compensation for the low dropout regulator, thereby achieving stability over the entire range of load current.

[0020] Claim 15 specifies an embodiment of a communication device including a low-dropout regulator.

[0021] In particular, low-dropout regulators can be used to provide regulated output voltage in multiple communication devices, such as sensors or battery-powered devices.

[0022] Additional features and advantages of the low-dropout regulator are set forth in the detailed description below. It should be understood that the foregoing general description and the following detailed description are merely exemplary and intended to provide an overview or framework for understanding the nature and features of the claims. Attached Figure Description

[0023] The accompanying drawings are intended to provide a further understanding and are incorporated in and form part of this specification. Therefore, this disclosure will be more fully understood through the following detailed description, taken in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 The basic structure of a low-dropout regulator is shown.

[0025] Figure 2 The configuration of a low-dropout regulator is shown, in which a buffer circuit is positioned between the error amplifier and the regulator's path device;

[0026] Figure 3 The structure of the buffer circuit of the low dropout regulator is shown;

[0027] Figure 4 An embodiment of a low-dropout regulator for low-voltage applications is shown; and

[0028] Figure 5 A communication device including a low-dropout regulator is shown. Detailed Implementation

[0029] Figure 1 A basic structural schematic of a low-dropout regulator is shown, comprising a path device 200 disposed between an input power terminal IN for providing the input power supply voltage Vin and an output terminal OUT for providing the regulated output voltage Vout. A load 300, represented by capacitor 310 and resistor 320, can be coupled to the output terminal OUT. The path device 200 is controlled by an error amplifier 100, which generates a control signal for the path device 200 based on a comparison of a reference voltage Vref and a feedback voltage Vf. The reference voltage Vref can be provided by a voltage source 400, such as a voltage source for providing a bandgap voltage. The feedback voltage Vf has a level responsive to the regulated output voltage Vout. The feedback voltage Vf is tapped at a voltage divider including resistors 210 and 220 and applied to the error amplifier via a feedback path.

[0030] Figure 1 The LDO structure shown can be used in many applications to provide a regulated output voltage Vout, which can be used as a stable internal power supply for other electronic blocks in electronic circuits or devices.

[0031] like Figure 1As shown, resistor 230 is connected in series with path device 200, and capacitor 240 is connected to the drain node and feedback path of path device 200. Resistor 230 and capacitor 240 can be introduced to generate a low-frequency zero for frequency compensation. However, if a low-frequency zero is required, as shown... Figure 1 The low-dropout regulator shown is used to drive high load currents, such as up to 200mA. Therefore, the voltage drop across resistor 230 will significantly limit the minimum input supply voltage Vin. Figure 1 The basic approach to low-dropout regulators shown is only applicable to LDOs operating within a limited load current range. Furthermore, larger load currents require larger path devices 200, thus making frequency compensation difficult.

[0032] Figure 2 It shows the relationship with Figure 1 Another embodiment of a low-dropout regulator with a similar structure differs in that a buffer circuit / stage 500 is provided between the error amplifier 100 and the path device 200. The error amplifier 100 is configured to compare a scaled-down output signal Vf derived from the output signal / voltage Vout with a reference voltage Vref provided by the (bandgap) voltage source 400. The control node of the path device 200, implemented as a transistor, is connected to the output of the intermediate buffer circuit / stage 500 to drive the path device 200. The buffer circuit / stage 500 is capable of driving the path device 200 under conditions of high load current due to the larger path device.

[0033] Basically, different solutions can be used for the error amplifier 100 and the buffer circuit 500, depending on the required specifications.

[0034] Figure 3 A possible method for implementing a low-dropout regulator using an intermediate buffer circuit is shown. The design of the intermediate buffer circuit 500' is illustrated by IEEE members Mohammad Al Shoukh, Hoi Lee, and Raul Perez in "A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation" (IEEE Journal of Solid-State Circuits, vol. 42, no. 8, August 2007). Except for nodes T1 and T2, Figure 3 The components of the buffer circuit 500' shown are referenced to the markings in the aforementioned document. Node T1 of the buffer circuit 500' is connected to the output node of the error amplifier 100, and node T2 of the buffer circuit 500 is connected to the control node of the transistor in the pass device 200.

[0035] refer to Figure 3 Transistor M21, configured as a source follower, is coupled to the output node T1 of error amplifier 100 via its control / gate node. Source follower M21 provides negative feedback. Specifically, npn transistor Q20, configured as a feedback device, is connected in parallel to the output of source follower M21 to reduce the output resistance of the buffer circuit through shunt feedback. The buffer circuit is implemented using a technique called buffer impedance attenuation (BIA), in which two PMOS transistors M24 and M25 and npn transistor Q20 implement dynamic bias shunt feedback to reduce the output resistance of the buffer circuit under different load current conditions.

[0036] The proposed BIA technique effectively reduces the output impedance of the buffer circuit through dynamic bias shunt feedback. As a result, even when using large path devices to achieve low dropout voltage and generate high load current, the pole at the gate of the path device Mp is pushed far beyond the unity-gain frequency of the LDO regulation loop, across the entire load current range.

[0037] However, despite the absence of a series resistor connected to the circuitry, this regulator still cannot operate at very low input supply voltages, such as 1.1V to 1.8V, due to the additional gate-source voltage introduced by the PMOS transistor M21 in the buffer.

[0038] Transistors Mp and M21 of the path device 200 require gate-source voltages higher than their respective threshold voltages. Both are implemented as PMOS transistors such that the potential at node T1 is lower than the input supply voltage Vin by at least two threshold voltages of the PMOS transistor.

[0039] In summary, even with a high-performance solution using the 500' buffer circuit, there are significant limitations. If the input supply voltage Vin is very low, and the potential at the output node T1 of the error amplifier is even two threshold voltages below, the NMOS transistors in the error amplifier structure no longer have headroom.

[0040] Figure 4 An improved method for a low-dropout regulator 1 is shown to achieve a stable internal LDO with high efficiency and high load capacity. For example, the LDO is capable of driving loads exceeding 100mA even when the output voltage Vout needs to be very close to the input supply voltage Vin, and even when the input supply voltage Vin is very low. This provides the possibility of implementing an LDO even with specifications covering a wide input voltage range and a wide load range.

[0041] refer to Figure 4The illustrated embodiment of a low-dropout regulator 1 for low-voltage applications includes an input power terminal IN for providing an input power supply voltage Vin and a reference power supply terminal G for providing a reference power supply voltage VSS. The reference power supply voltage can be ground potential or a negative power supply potential. The low-dropout regulator 1 includes an error amplifier 100 having a first input terminal I100a and a second input terminal I100b for applying a reference signal Vref, and an output terminal O100. The low-dropout regulator also includes a path device 200 with a control node C200 for controlling the conductivity of the path device 200. The path device 200 can be configured as a PMOS transistor. The buffer circuit 500 is disposed between the output terminal O100 of the error amplifier 100 and the control node C200 of the path device 200.

[0042] The path element 200 is positioned in the output current path 40 and connected in series with a resistor divider including resistors 210 and 220. The LDO 1 provides a regulated output voltage Vout at the output terminal OUT. Figure 4 Also shown is a capacitive load 310 coupled to the output terminal OUT. A feedback path 60 is coupled between the output current path 40 and the second input terminal I100b of the error amplifier to feed back the feedback signal Vf to the error amplifier 100, which is derived from the output signal Vout.

[0043] The buffer circuit 500 includes a first current path 10 disposed between an input power supply terminal IN and a reference power supply terminal G. The first current path 10 includes a driver that includes a first transistor 11. The first transistor 11 has a control / gate node C11 to control the conductivity of the first transistor 11. Specifically, the first transistor 11 is implemented as an NMOS transistor. The output terminal O100 of the error amplifier 100 is coupled to the control node C11 of the first transistor 11 of the driver. The control node C200 of the pass device 200 is coupled to a first internal node N1 of the first current path 10. The first internal node N1 of the first current path 10 is located between the first transistor 11 and the reference power supply terminal G.

[0044] The first transistor 11 of the driver has a drain node D11 coupled to the input power supply terminal IN and a source node S11 coupled to the internal node N1 of the first current path 10. The first transistor of the driver is configured as a source follower transistor. In order to provide sufficient headroom for the error amplifier output under low load, according to an advantageous embodiment of the low dropout regulator 1, the first transistor 11 can be implemented as a native NMOS transistor.

[0045] If Figure 4 The design of the circuit buffer 500 shown is... Figure 3 By comparing the methods of the buffer circuits shown, it can be noted that the new buffer design is implemented by including or configuring a driver for an NMOS transistor 11 (specifically an NMOS source follower) connected to the output terminal O100 of the error amplifier 100, instead of using a PMOS transistor M21 as... Figure 3 The buffer circuit method 500' shown is used for the driver. The advantage of this is that the low-dropout regulator 1 can operate at low input supply voltages. Specifically, Figure 4 The low-dropout regulator 1 described herein can operate with an input supply voltage between 1.1V and 1.8V and a regulated output voltage Vout of 0.9V. The proposed design of the low-dropout regulator provides the possibility of using a wide range of input supply voltages and load currents.

[0046] According to an embodiment of the low dropout regulator 1, the buffer circuit 500 includes a second transistor 12. The second transistor 12 is disposed between the power supply terminal IN and the first internal node N1 of the first current path 10. The second resistor 12 is configured as a PMOS transistor. Specifically, the second transistor 12 has a source node coupled to the power supply terminal IN and a drain node coupled to the first internal node N1 of the first current path 10.

[0047] The second transistor 12 is positioned in the current path between the power supply terminal IN and the first internal node N1 of the first current path, enabling the buffer circuit 500 to be provided with dynamically biased shunt feedback to reduce the output resistance under different load currents, thereby achieving high stability of the LDO.

[0048] refer to Figure 4 The first current path 10 includes a current source 15 disposed in the first current path 10 between the power supply terminal IN and the first transistor 11. The second transistor 12 has a control node connected to a second internal node N2 of the first current path 10. The second internal node N2 is disposed between the current source 15 and the first transistor 11 in the first current path 10. The current source 15 includes a transistor having a source node connected to the power supply terminal IN and a drain node connected to the second internal node N2 of the first current path 10.

[0049] The low dropout regulator includes a third transistor 13 disposed between the power supply terminal IN and the second internal node N2 of the first current path 10. The third transistor 13 has a source node connected to the power supply terminal IN and a drain node connected to the second internal node N2 of the first current path 10.

[0050] Will Figure 3 The structure of the 500' buffer circuit and Figure 4 Comparing the design of the buffer circuit 500, Figure 3 The structure of the buffer circuit 500' is "flipped," meaning that the NMOS transistor 11 of the driver is used as a source follower transistor, and the PMOS transistor 12 is used as a local feedback transistor. This provides the possibility of implementing the buffer circuit in an efficient manner, even when the input supply voltage Vin is very low or the load is high.

[0051] The third transistor 13 is configured as a switch and has a control node to apply a control signal for controlling the conductivity of the third transistor 13. The buffer circuit 500 is configured to generate a control signal for controlling the conductivity of the second transistor 13 in response to the load current of the low-dropout regulator.

[0052] The buffer circuit is configured to generate a control signal for controlling the conductivity of the third transistor 13 based on the level of the load current of the low-dropout regulator. For this purpose, the low-dropout regulator 1 includes a current path 30 disposed between the power supply terminal IN and the reference power supply terminal G to apply a reference power supply voltage VSS. The current path 30 includes a current source 32 and a transistor 31 connected in series between the power supply terminal IN and the reference power supply terminal G. The current source 32 is configured as a transistor having a source node connected to the reference power supply terminal and a drain node connected to an internal node N4 of the third current path 30. The transistor 31 has a source node connected to the power supply terminal IN and a drain node connected to the internal node N4. The internal node N4 is connected to the control node of the third transistor 13.

[0053] The control / gate node of transistor 31 is coupled to the first internal node N1 of the first current path 10 in the same manner as the control / gate node C200 of the transmission transistor 200. This arrangement allows the buffer circuit 1 to be configured to sense the load current of the low-dropout regulator. Specifically, the load current is sensed and compared with a constant current supplied by current source 32. Therefore, the potential at node N4 depends on the level of the load current and the level of the constant current from current source 32. The third transistor 13 is configured as a PMOS switch. Since the potential at node N4 is used as the control signal for the third transistor 13, the comparison result of the load current and the constant current from current source 32 is used to turn the third transistor on or off.

[0054] Specifically, when the load current is very low, the third transistor 13 is turned on, i.e., operating in a low-resistance state. As a result, because the drain node of the third transistor 13 is coupled to the control / gate node of the second transistor 12, the second transistor 12 is turned off, i.e., operating in a high-resistance state, which allows the first / source follower transistor 11 to operate in a saturation state. This means that for low loads, the local feedback is turned off to keep the source follower transistor 11 in saturation. This provides greater headroom for the first transistor 11 at low loads, where the potential at the control / gate node of the path device 200 is close to the input supply voltage Vin under any circumstances.

[0055] On the other hand, under high load current, the potential at internal node N4 is close to the input supply voltage vin, and the third transistor 13 is turned off, i.e., it operates in a high-resistance state. Therefore, the second transistor 12 turns on, which reduces the output resistance of the buffer circuit, thus improving the stability of the LDO.

[0056] The buffer circuit 500 includes a current mirror 70 configured to provide a bias current in a first current path 10 of the buffer circuit 500. The buffer circuit 500 includes a second current path 20. The current mirror 70 is configured to provide a bias current in the first current path 10 based on the current in the second current path 20.

[0057] The second current path 20 includes a second current source 21 disposed between the power supply terminal IN and the current mirror 70. The low dropout regulator 1 also includes a fourth transistor 14. The fourth transistor 14 is disposed between the power supply terminal IN and the third internal node N3 of the second current path 20, located between the second current source 21 and the current mirror 70.

[0058] like Figure 4 As shown, the current mirror 70 includes transistors 71 and 72 connected to each other at their respective control / gate terminals. Transistor 71 is located in a first current path 10 between the first transistor 11 and the reference power supply terminal G. The second transistor 72 is located in a second current path 20 of a buffer circuit between the current source 21 and the reference power supply terminal G.

[0059] like Figure 4 As shown, the control / gate node of the fourth transistor 14 is coupled to the first internal node N1 in the same manner as the control / gate node C200 of the pass device / transistor 200. The control / gate node of the fourth transistor 14 is connected to the control / gate node C200 of the pass device / transistor 200. Therefore, the fourth transistor 14 is used to sense the load current and adjust the bias current of the snubber circuit so that the snubber circuit operates with a higher bias current when a higher load current is detected.

[0060] The low-dropout regulator 1 includes an output current path 40, which includes a pass device / transistor 200 and an output terminal OUT to provide a regulated output voltage Vout. The low-dropout regulator 1 also includes a feedback path 50, which includes a capacitor 51. The capacitor 51 is disposed between the output terminal OUT and the third input terminal I100c of the error amplifier 100.

[0061] Capacitor 51 provides Miller compensation to stabilize the LDO structure, enabling stability across the entire load current range. By employing Miller compensation in the low dropout regulator 1, only a single pole is achieved at the unity-gain frequency, and good phase margin is achieved across the entire load current range using a small compensation capacitor.

[0062] Figure 4 The proposed design for a low dropout regulator shown can be used in applications such as sensor applications, portable applications, or microprocessor applications. Figure 5 An exemplary use of a low-dropout regulator 1 in a communication device 2 to provide regulated output voltage is shown. The regulated output voltage can be used as a stable power supply for electronic components of the communication device, which can be implemented as, for example, sensors or battery-powered devices.

[0063] To familiarize the reader with the novel aspects of voltage regulator design, embodiments of the low-dropout regulators disclosed herein for low-voltage applications have been discussed. While preferred embodiments have been shown and described, many changes, modifications, equivalents, and substitutions of the disclosed concepts will be possible to those skilled in the art without departing from the scope of the claims.

[0064] In particular, the design of the low-dropout regulator is not limited to the disclosed embodiments, and examples of as many alternatives as possible to the features included in the discussed embodiments are given. However, this is intended to include any modifications, equivalents, and substitutions of the disclosed concepts within the scope of the appended claims.

[0065] Features described in the independent dependent claims can be advantageously combined. Furthermore, the reference numerals used in the claims are not intended to limit the scope of the claims.

[0066] Furthermore, as used herein, the term "comprising" does not exclude other elements. Additionally, as used herein, the term "a" is intended to include one or more components or elements, and is not limited to being interpreted as referring to only one.

[0067] This patent application claims priority to European Patent Application No. 20182918.1, the disclosure of which is incorporated herein by reference.

[0068] List of reference numerals

[0069] 1. Low dropout voltage regulator

[0070] 2. Communication equipment

[0071] Current paths of 10, 20, 30, and 40

[0072] 11 Driver / First Transistor

[0073] 12 Second transistor

[0074] 13 Third transistor

[0075] 14. Fourth transistor

[0076] 15 Current Source

[0077] 21 Current Source

[0078] 31 and 32 transistors

[0079] 40 Output Current Path

[0080] 50 Feedback Path

[0081] 51 Capacitor

[0082] 60 Feedback Path

[0083] 70 Current Mirror

[0084] Transistors 71 and 72

[0085] Internal nodes N1, N2, N3, and N4

[0086] 100 Error Amplifier

[0087] 200-channel devices

[0088] 210, 220, 230 resistors

[0089] 300 load

[0090] 310 Capacitive load

[0091] 320Ω resistive load

[0092] 400 bandgap reference

[0093] 500 buffer circuit

[0094] Vin Input power voltage

[0095] VSS Reference Supply Voltage

[0096] Vref reference voltage

[0097] Vf feedback voltage

[0098] Vout adjusts the output voltage.

Claims

1. A low-dropout regulator for low-voltage applications, comprising: - Input power terminal (IN), used to provide input power voltage (Vin). - Reference power supply terminal (G), used to provide reference power supply voltage (VSS). - An error amplifier (100) has a first input terminal (I100a), a second input terminal (I100b), and an output terminal (O100). -A pathway device (200) having a control node (C200) to control the conductivity of the pathway device (200), - A buffer circuit (500) is disposed between the output terminal (O100) of the error amplifier (100) and the control node (C200) of the pass device (200). The buffer circuit (500) includes a first current path (10) disposed between the input power supply terminal (IN) and the reference power supply terminal (G), wherein the first current path (10) includes a driver, the driver including a first transistor (11), the first transistor (11) having a control node to control the conductivity of the first transistor, the first transistor (11) being implemented as an NMOS transistor. -The output terminal (O100) of the error amplifier (100) is coupled to the control node (C11) of the first transistor (11). - wherein the control node (C200) of the path device (200) is coupled to the first internal node (N1) of the first current path (10) located between the first transistor (11) and the reference power supply terminal (G). -The buffer circuit (500) therein includes a second transistor (12) disposed between the power supply terminal (IN) and the first internal node (N1) of the first current path (10). -The first current path (10) includes a current source (15) disposed between the power supply terminal (IN) and the first transistor (11) in the first current path (10). -The second transistor (12) has a control node connected to a second internal node (N2) of the first current path (10), the second internal node (N2) being disposed between the current source (15) of the first current path (10) and the first transistor (11).

2. The low-dropout voltage regulator according to claim 1, The first transistor (11) has a drain node (D11) coupled to the input power terminal (IN) and a source node (S11) coupled to the first internal node (N1) of the first current path (10).

3. The low-dropout voltage regulator according to claim 1, The first transistor (11) is configured as a source follower transistor.

4. The low-dropout voltage regulator according to claim 1, The first transistor (11) is configured as a native NMOS transistor.

5. The low-dropout voltage regulator according to claim 1, The second transistor (12) is configured as a PMOS transistor.

6. The low-dropout voltage regulator according to claim 1, The second transistor (12) has a source node coupled to the power supply terminal (IN) and a drain node coupled to a first internal node (N1) of the first current path (10).

7. The low-dropout voltage regulator according to claim 1, comprising: The third transistor (13) is disposed between the power supply terminal (IN) and the second internal node (N2) of the first current path (10).

8. The low-dropout voltage regulator according to claim 7, -The third transistor (13) has a source node connected to the power supply terminal (IN) and a drain node connected to a second internal node (N2) of the first current path (10). -The third transistor (13) has a control node to apply a control signal for controlling the conductivity of the third transistor (13). -The buffer circuit (500) is configured to generate a control signal for controlling the conductivity of the third transistor (13) in response to the amount of load current of the low-dropout regulator.

9. The low-dropout voltage regulator according to claim 1, -The buffer circuit (500) includes a current mirror (70) configured to provide a bias current in the first current path (10) of the buffer circuit (500). -The buffer circuit (500) mentioned therein includes a second current path (20). - wherein the current mirror (70) is configured to provide the bias current in the first current path (10) in response to the current in the second current path (20).

10. The low-dropout voltage regulator according to claim 9, comprising: - Fourth transistor (14) -The second current path (20) includes a second current source (21) disposed between the power supply terminal (IN) and the current mirror (70). -The fourth transistor (14) is disposed between the power supply terminal (IN) and the third internal node (N3) of the second current path (20) located between the second current source (21) and the current mirror (70).

11. The low-dropout voltage regulator according to claim 1, comprising: - Output current path (40), which includes a pass device (200) and an output terminal (OUT) to provide a regulated output voltage (Vout). - Feedback path (50), which includes a capacitor (51) disposed between the output terminal (OUT) and the third input terminal (I100c) of the error amplifier (100).

12. A communication device, comprising: - The low dropout regulator (1) according to claim 1 is used to provide a regulated output voltage (Vout). -The communication device (2) is implemented as a sensor or a battery-powered device.

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