Test circuit, test method and test device

Abstract

The present disclosure provides a test circuit, a test method and a test device, and relates to the technical field of semiconductors. The test circuit comprises a ring oscillation circuit and a plurality of test units. The ring oscillation circuit comprises a plurality of logic gate units which are cascaded in sequence and form a ring loop. The test unit comprises a first transistor and a second transistor. The common gate of the first transistor and the second transistor is connected to the input end of the logic gate unit. The source of the first transistor is connected to a first ground end. The drain of the first transistor is connected to the drain of the second transistor. The substrate end of the first transistor or the substrate end of the second transistor is connected to a bias voltage source. The source of the second transistor is connected to a first power supply. The bias voltage source is used to provide a bias voltage for the substrate end of the first transistor or the substrate end of the second transistor when the level of the input end of the logic gate unit is inverted. The present disclosure can accurately measure the drive current of the transistor in the test unit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a test circuit, a test method and a test device. BACKGROUND

[0002] Metal-oxide-semiconductor field-effect transistor (MOS) is widely used in the field of semiconductor technology, and is divided into PMOS and NMOS according to the different channel materials. Among them, the inverter is a complementary metal oxide semiconductor (CMOS) logic gate with inverting effect.

[0003] In the existing CMOS technology, in order to obtain the best noise margin, the device width of PMOS and NMOS is usually adjusted to make the switching voltage of the logic gate composed of transistors at half of the working voltage. When measuring the driving current of PMOS, the gate, source and drain of PMOS are all separately led out to apply half of the working voltage at the source and gate. At this time, the channel current measured at the drain can be used as the driving current of PMOS. Similarly, the driving current of NMOS can also be measured.

[0004] However, the transconductance of different transistors is different, so that the midpoint of the transfer curve of the logic gate composed of transistors is not at half of the working voltage, and during the time of logic level flip, the transistor will experience the over-saturation region and the linear region in turn, so the single DC test under a certain fixed bias cannot reflect the accurate driving current. SUMMARY

[0005] The present disclosure provides a test circuit, a test method and a test device, which can improve the test accuracy of transistor driving current.

[0006] In a first aspect, the embodiments of the present disclosure provide a test circuit, comprising a ring oscillator circuit and a plurality of test units;

[0007] The ring oscillator circuit comprises a plurality of logic gate units cascaded in sequence and forming a ring loop;

[0008] The test unit comprises a first transistor and a second transistor, the channel types of the first transistor and the second transistor are different, the common gate of the first transistor and the second transistor is connected with the input end of the logic gate unit, the source of the first transistor is connected with a first ground end, the drain of the first transistor is connected with the drain of the second transistor, the substrate end of the first transistor or the substrate end of the second transistor is connected with a substrate bias voltage source, the source of the second transistor is connected with a first power supply, and the substrate bias voltage source is used to provide a substrate bias voltage for the substrate end of the first transistor or the substrate end of the second transistor when the level inversion occurs at the input end of the logic gate unit, so as to adjust the threshold voltage of the first transistor or the second transistor.

[0009] In some embodiments, each of the logic gate units comprises an inverter, and the inverter comprises a third transistor and a fourth transistor of different types, the third transistor is an NMOS, and the fourth transistor is a PMOS.

[0010] When the substrate end of the first transistor is connected with the substrate bias voltage source, the source of the fourth transistor is connected with a second power supply, and the second power supply is independent of the first power supply.

[0011] When the substrate end of the second transistor is connected with the substrate bias voltage source, the source of the third transistor is connected with a second ground end, and the second ground end is independent of the first ground end.

[0012] In some embodiments, the first-stage logic gate unit of the ring oscillator circuit is an NAND gate unit, and the NAND gate unit comprises a first input end and a second input end.

[0013] The first input end is used to receive an enable control signal, and the second input end is connected with the output end of the last-stage logic gate unit of the ring oscillator circuit.

[0014] In some embodiments, the test unit further comprises a load circuit.

[0015] The common drain of the first transistor and the second transistor is connected with the input end of the load circuit, and the output end of the load circuit is left unconnected.

[0016] In some embodiments, the load circuit comprises a plurality of logic gate units connected in cascade.

[0017] In some embodiments, a current measurement element is further included.

[0018] When the substrate end of the first transistor is connected with the substrate bias voltage source, the current measurement element is connected with the first power supply, and is used to measure the current value flowing out of the first power supply.

[0019] In some embodiments, the current measurement element is further included.

[0020] When the substrate end of the second transistor is connected to the substrate bias voltage source, the current measurement device is connected to the first ground end for measuring the current value flowing into the first ground end.

[0021] In some embodiments, the first selection switch is further included.

[0022] When the substrate end of the first transistor is connected to the substrate bias voltage source, the first selection switch is used to disconnect the connection between the second power source and the first power source, so that the second power source and the first power source are independent of each other.

[0023] In some embodiments, the second selection switch is further included.

[0024] When the substrate end of the second transistor is connected to the substrate bias voltage source, the second selection switch is used to disconnect the connection between the second ground end and the first ground end, so that the second ground end and the first ground end are independent of each other.

[0025] In some embodiments, when the substrate end of the first transistor is connected to the substrate bias voltage source, the substrate bias voltage source is used to provide a first substrate bias voltage for the substrate end of the first transistor when a level inversion occurs at the input end of the logic gate unit, and the first substrate bias voltage is a negative voltage.

[0026] In some embodiments, when the substrate end of the second transistor is connected to the substrate bias voltage source, the substrate bias voltage source is used to provide a second substrate bias voltage for the substrate end of the second transistor when a level inversion occurs at the input end of the logic gate unit, and the second substrate bias voltage is a positive voltage.

[0027] In some embodiments, the first transistor is an NMOS, and the second transistor is a PMOS.

[0028] In some embodiments, the number of test units is less than or equal to the number of logic gate units in the ring oscillator circuit.

[0029] In a second aspect, the embodiments of the present disclosure provide a test method applied to the test circuit provided in the first aspect, and the above method comprises:

[0030] An enable control signal is provided for the ring oscillator circuit.

[0031] When a level inversion occurs at the input end of the logic gate unit, a first substrate bias voltage is provided for the substrate end of the first transistor by using the substrate bias voltage source.

[0032] detecting a current value flowing out of the first power supply, and determining the current value flowing out of the first power supply as a driving current of the second transistor.

[0033] In a third aspect, the embodiments of the present disclosure provide a test method, applied to the test circuit provided in the first aspect, and the method comprises:

[0034] providing an enable control signal for the ring oscillator circuit;

[0035] when a level inversion occurs at an input end of the logic gate unit, providing a second substrate bias voltage for a substrate end of the second transistor by using the substrate bias voltage source;

[0036] detecting a current value flowing into the first ground end, and determining the current value flowing into the first ground end as a driving current of the first transistor.

[0037] In a fourth aspect, the embodiments of the present disclosure provide a test device, comprising at least one processor and a memory.

[0038] The memory stores computer-executed instructions.

[0039] The at least one processor executes the computer-executed instructions stored in the memory, so that the at least one processor executes the test method provided in the second aspect or the third aspect.

[0040] The test circuit, the test method and the test device provided by the present disclosure can measure the accurate driving current of the PMOS in each test unit at the first power supply by connecting the source of the PMOS in each test unit to the independent first power supply and adjusting the threshold voltage of the NMOS in each test unit when the level inversion occurs at the input end of the logic gate unit in the ring oscillator circuit; or can measure the accurate driving current of the NMOS in each test unit at the first ground end by connecting the source of the NMOS in each test unit to the independent first ground end and adjusting the threshold voltage of the PMOS in each test unit when the level inversion occurs at the input end of the logic gate unit in the ring oscillator circuit. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a structural schematic diagram of a ring oscillator circuit provided by the embodiments of the present disclosure;

[0042] Figure 2 is a current schematic diagram between adjacent inverters in the ring oscillator circuit shown in the embodiments of the present disclosure; Figure 1

[0043] Figure 3 is a current schematic diagram between adjacent inverters in the ring oscillator circuit shown in the embodiments of the present disclosure; Figure 1 ​Another current diagram between adjacent inverters in the ring oscillator circuit shown;

[0044] Figure 4 is a structural schematic diagram of a test circuit provided by an embodiment of the present disclosure;

[0045] Figure 5 is a structural schematic diagram of another ring oscillator circuit provided by an embodiment of the present disclosure;

[0046] Figure 6 is a structural schematic diagram of another test circuit provided by an embodiment of the present disclosure;

[0047] Figure 7 is a structural schematic diagram of yet another test circuit provided by an embodiment of the present disclosure;

[0048] Figure 8 is a step flowchart of a test method provided by an embodiment of the present disclosure;

[0049] Figure 9 is a step flowchart of another test method provided by an embodiment of the present disclosure;

[0050] Figure 10 is a hardware structural schematic diagram of a test device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present disclosure. In addition, although the disclosure is introduced according to one or more exemplary examples, it should be understood that each aspect of the disclosure can also constitute a complete embodiment independently.

[0052] It should be noted that the brief description of the terms in the present disclosure is only for the convenience of understanding the subsequently described embodiments, and is not intended to limit the embodiments of the present disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0053] The terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise specified. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, for example, those orders other than given in the embodiment illustration or description of the present disclosure can be implemented.

[0054] Furthermore, the terms "comprise", "comprising", "have", "having", "include", "including" and "contains", "containing", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or article that comprises a list of components does not include only those components but can include other components not expressly listed or inherent to such product or article.

[0055] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or / and software code that can perform the functions related to the element.

[0056] MOS can be divided into PMOS (P-channel type) and NMOS (N-channel type) according to the channel type. Among them, MOS includes four terminals such as gate (G), source (S), drain (D) and substrate (bulk). For NMOS, when the voltage Vgs between the gate (G) and the source (S) is greater than a certain value, the NMOS will be turned on. For PMOS, when the voltage Vgs between the gate (G) and the source (S) is less than a certain value, the PMOS will be turned on.

[0057] MOS is widely used in the field of semiconductor technology. For example, PMOS and NMOS in series can constitute an inverter (also known as a NOT gate), and the inverter is a CMOS with inversion function. Testing the drive current of PMOS and NMOS in CMOS can assist in analyzing CMOS, for example, the parasitic capacitance of CMOS can be analyzed according to the drive current of PMOS and NMOS, so as to determine the influence of ion doping on the parasitic capacitance of CMOS, and then obtain a faster circuit.

[0058] In the existing test circuit, the four terminals of MOS are separately led out, and the current of MOS device is tested under the working voltage condition. At the same time, in the existing CMOS technology, in order to obtain the best noise margin, the device width of PMOS and NMOS is usually adjusted to make the switching voltage of the logic gate composed of transistors at half of the working voltage.

[0059] At present, when measuring the drive current of PMOS, the source and gate of PMOS are usually applied with half of the working voltage, at which time the channel current measured at the drain can be used as the drive current of PMOS. Similarly, the drive current of NMOS can also be measured.

[0060] However, in the actual level conversion process, the midpoint of the transfer curve of the logic gate is not exactly at half of the working voltage because the transconductance of the NMOS and PMOS is not consistent. In addition, even if the level transition occurs at half of the working voltage, the corresponding time is short, and there is still considerable time in which the PMOS is in the linear region, the low Vgs and the high Vds over-saturation region. Therefore, when half of the working voltage is applied to the source and gate of the PMOS, the channel current measured at the drain cannot accurately reflect the driving current of the PMOS; the same is true for the NMOS. Wherein, Vds represents the voltage between the drain (D) and the source (S) of the MOS.

[0061] For example, in some conventional test methods, in order to test the driving current of the MOS at the level flip moment, a ring oscillator circuit can be used.

[0062] Referring to Figure 1 , a structure diagram of a ring oscillator circuit is provided. Figure 1

[0063] In some embodiments, the ring oscillator circuit described above can be obtained by connecting a plurality of inverters connected in series, Figure 1 For example, a ring oscillator circuit composed of five inverters connected in series is shown, but in actual application, the number of inverters included in the ring oscillator circuit is an odd number, which is not limited in the embodiments of the present disclosure.

[0064] It should be noted that Figure 1 The specific structure of one of the inverters is marked in detail, and the structures of the remaining inverters are the same as that of the inverter, so the structures of the remaining inverters are not marked in Figure 1 .

[0065] As can be seen from Figure 1 , the output end of each inverter is connected to the input end of the next inverter, thus forming a ring oscillator circuit with a ring-shaped loop.

[0066] Figure 1 Each inverter in is obtained by connecting a PMOS and an NMOS. The gate G of the PMOS is connected to the gate G of the NMOS, and the two connected gate Gs serve as the input end of the inverter. The drain D of the PMOS is connected to the drain D of the NMOS, and the two connected drain Ds serve as the output end of the inverter. The source S of the PMOS is connected to the second power supply VDD2, and the source S of the NMOS is connected to the second ground GND2.

[0067] Figure 1In the ring oscillator shown, the output of some inverters will have a level transition from high to low, and the output of some other inverters will have a level transition from low to high. Thus, the moment of level transition can be captured, and the current at that moment can be taken as the driving current of the PMOS or NMOS.

[0068] Referring to Figure 2 shown, Figure 2 is provided by the embodiment of the present disclosure Figure 1 Another current diagram between adjacent inverters in the ring oscillator shown.

[0069] In the process of the level V at the input of the previous inverter INV_1 transitioning from high to low, the PMOS in INV_1 gradually turns on and generates a current I1, which flows to the common gate of the NMOS and PMOS in the next inverter INV_2. Under the action of the current I1, the gate voltage of the NMOS in INV_2 rises to high. However, in this process, the NMOS in INV_1 is not completely closed, and there will still be a part of the current I2 flowing from the PMOS in INV_1 to the ground GND through the NMOS in INV_1 that is not completely closed.

[0070] In which, since the current I1 and the current I2 both flow out from the VDD terminal, the driving current of the PMOS measured at the VDD port will be larger than the actual driving current of the PMOS. This will lead to overestimating the equivalent capacitance of the ring oscillator and underestimating its equivalent resistance, and thus the influence of ion doping on the CMOS parasitic capacitance cannot be obtained.

[0071] Referring to Figure 3 shown, Figure 3 is provided by the embodiment of the present disclosure Figure 1 Another current diagram between adjacent inverters in the ring oscillator shown.

[0072] In the process of the level V at the input of the previous inverter INV_1 transitioning from low to high, the NMOS in INV_1 gradually turns on and generates a current I3, which makes the level of the common gate in the next inverter INV_2 decrease to 0. However, in this process, the PMOS in the previous inverter is not completely closed, and there will still be a part of the current I4 flowing from the PMOS in INV_1 that is not completely closed to the ground GND through the NMOS in the previous inverter.

[0073] Because currents I3 and I4 flow into GND together, the NMOS drive current measured at the GND port will be larger than the actual NMOS drive current. This will also lead to an overestimation of the equivalent capacitance of the ring oscillator and an underestimation of its equivalent resistance, thus failing to obtain the effect of ion doping on the CMOS parasitic capacitance.

[0074] To address the aforementioned technical problems, this disclosure provides a test circuit. By connecting the source of the PMOS in each test unit to an independent first power supply, and adjusting the threshold voltage of the NMOS in each test unit when the input of the logic gate in the ring oscillator circuit undergoes a level flip, the accurate drive current of the PMOS in each test unit can be measured at the first power supply. Alternatively, by connecting the source of the NMOS in each test unit to an independent first ground terminal, and adjusting the threshold voltage of the PMOS in each test unit when the input of the logic gate in the ring oscillator circuit undergoes a level flip, the accurate drive current of the NMOS in each test unit can be measured at the first ground terminal.

[0075] The following detailed examples illustrate the process.

[0076] Reference Figure 4 As shown, Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of the present disclosure. In one feasible implementation, the test circuit 100 includes a ring oscillation circuit 101 and a plurality of test units 1021 to test units 1025.

[0077] Reference Figure 4 As shown, the ring oscillator circuit 101 includes multiple logic gate units that are cascaded in sequence to form a ring loop, such as logic gate unit 1011 to logic gate unit 1015. Each logic gate unit includes an input terminal and an output terminal.

[0078] Optionally, the above logic gate unit can be a logic gate with inverting function, including but not limited to: NOT gate, NAND gate, NOR gate, XOR gate, XNOR gate, and controlled NOT gate, etc.

[0079] Optionally, the NOT gate mentioned above can be an inverter composed of PMOS and NMOS connected together.

[0080] Understandable, Figure 4 The ring oscillator circuit 101 in the example provides 5 logic gate units, but in actual applications, the number of logic gate units can be odd as long as it is not limited here.

[0081] Figure 4Five test units are exemplarily shown in the test circuit 100, which are test unit 1021 to test unit 1025, but the number of test units can be less than or equal to the number of logic gate units in actual application, and the number of test units is not limited in the embodiments of the present disclosure.

[0082] In some embodiments of the present disclosure, the ring oscillator circuit 101 can have two kinds, in one embodiment of the ring oscillator circuit, as shown in Figure 1 , each logic gate unit can be a NOT gate, which can also be called an inverter, so that the input end of each logic gate unit is the input end of the NOT gate, and the output end of each logic gate unit is the output end of the NOT gate. In this way, the output end of each NOT gate of the ring oscillator circuit 101 is connected with the input end of the next stage NOT gate.

[0083] In another embodiment of the ring oscillator circuit, the structure of the first stage logic gate unit can be different from that of the remaining logic gate units. As shown in Figure 5 , the first stage logic gate unit is a NAND gate, and the remaining logic gate units are NOT gates. Figure 5 is a structural schematic diagram of a ring oscillator circuit provided by the embodiments of the present disclosure.

[0084] In Figure 5 , the first stage logic gate unit 1011 of the ring oscillator circuit 101 can be a NAND gate, such as a two-input NAND gate (NAND2), and the remaining logic gate units can be NOT gates (hereinafter referred to as inverters).

[0085] In the above, one input end of the NAND gate is the enable input end En of the ring oscillator circuit 101, the other input end is the input end of the first stage logic gate unit 1011, and the output end of the NAND gate is the output end of the first stage logic gate unit 1011.

[0086] Referring to Figure 5 , the output end of the NAND gate is connected with the input end of the second stage logic gate unit, and the other input end of the NAND gate is connected with the output end of the last stage logic gate unit, thereby forming a ring oscillator circuit.

[0087] In some embodiments, the enable input end En is used to control the oscillation of the ring oscillator circuit 101. In the initial state, when the enable control signal input in the enable input end En is a low-level signal, Figure 5 , the ring oscillator circuit 101 does not oscillate; when the enable control signal input in the enable input end En is a high-level signal, Figure 5 , the ring oscillator circuit 101 starts to oscillate, that is, the first stage logic gate unit starts to work, and the level of the input end appears level inversion.

[0088] It can be seen that in the embodiments of the present disclosure, the NAND gate and the enable control signal can be combined to flexibly control the oscillation of the ring oscillator circuit 101. When the flip current does not need to be tested, the enable control signal can be used to control the ring oscillator circuit 101 to stop oscillation, thereby helping to save power.

[0089] In an optional embodiment, each logic gate unit in the ring oscillator circuit 101 includes a NAND gate, and the NAND gate includes a third transistor and a fourth transistor of different channel types, for example, the third transistor is an NMOS and the fourth transistor is a PMOS.

[0090] In some embodiments, the NAND gate can be composed of two PMOS and two NMOS. The common source of the two PMOS in the NAND gate can be connected to the second power supply VDD2 as the power supply terminal of the NAND gate.

[0091] Referring to Figure 5 , the power supply terminal of the NAND gate in the ring oscillator circuit 101 and the source of the fourth transistor of each NAND gate are connected to the same second power supply VDD2 to provide power supply for the ring oscillator circuit 101. Since the ring oscillator circuit 101 can oscillate without the NAND gate, the source of the fourth transistor of each NAND gate is connected to the same second power supply VDD2 when the NAND gate does not exist in the ring oscillator circuit 101.

[0092] In Figure 5 , in any NAND gate, the gate G of the fourth transistor PMOS is connected to the gate G of the third transistor NMOS and serves as the input terminal of the corresponding NAND gate. The drain D of the fourth transistor PMOS is connected to the drain D of the third transistor NMOS and serves as the output terminal of the corresponding NAND gate, and the source S of the third transistor NMOS is connected to the second ground terminal GND2.

[0093] Referring to Figure 6 , Figure 6 is another structure diagram of a test circuit provided by the embodiments of the present disclosure. In some embodiments, the test circuit includes Figure 1 or Figure 5 the ring oscillator circuit shown in the figure, and a plurality of test units.

[0094] Exemplarily, Figure 6 the structure of one of the test units 1021 is shown in the figure. It can be understood that the structures of the other test units are consistent with the structure of the test unit 1021.

[0095] The test circuit 100 comprises a plurality of test units, each of which comprises a first transistor NMOS and a second transistor PMOS, the common gate of the first transistor and the second transistor is connected to the input of the corresponding logic gate unit in the ring oscillator circuit, the source of the first transistor is connected to a first ground terminal GND1, the drain of the first transistor is connected to the drain of the second transistor, the substrate of the first transistor is connected to a substrate bias voltage source Vbs, and the source of the second transistor is connected to a first power supply VDD1.

[0096] The substrate bias voltage source Vbs is configured to provide a substrate bias voltage for the substrate of the first transistor when the level of the input of the logic gate unit is inverted, so as to adjust the threshold voltage of the first transistor.

[0097] In some embodiments, the substrate bias voltage source Vbs is configured to provide a first substrate bias voltage for the substrate of the first transistor when the level of the input of the logic gate unit is inverted, the first substrate bias voltage being a negative voltage, so as to increase the threshold voltage of the first transistor.

[0098] The first power supply VDD1 is independent of a second power supply VDD2 connected to each logic gate unit in the ring oscillator circuit 101. The first ground terminal GND1 can be independent of a second ground terminal GND2 connected to each logic gate unit in the ring oscillator circuit 101, or can be the same ground terminal.

[0099] In some embodiments, the test circuit 100 further comprises a first selection switch, which is configured to disconnect the connection between the second power supply VDD2 and the first power supply VDD1 during the test, so that the second power supply VDD2 and the first power supply VDD1 are independent of each other.

[0100] In addition, each of the test units further comprises a load circuit, the common drain of the first transistor and the second transistor is connected to the input of the load circuit, and the output of the load circuit is left floating.

[0101] Optionally, the load circuit comprises a plurality of logic gate units connected in cascade.

[0102] The logic gate units in the load circuit are consistent with the logic gate units in the ring oscillator circuit. For example, when the logic gate units in the ring oscillator circuit are NOT gates, the logic gate units in the load circuit are also NOT gates.

[0103] It can be understood that when the logic gate unit in the above load circuit is a NOT gate, the load circuit can simulate the Miller effect of the parasitic capacitance when the next logic gate unit is loaded as the load of the current logic gate unit. In addition, the load circuit can also adjust the time of level inversion of the logic gate unit. If the load circuit does not exist, the level inversion of the logic gate unit will be fast, which will cause it difficult to measure the drive current of the test unit, that is, the load circuit can be equivalent to a parasitic capacitance.

[0104] In the embodiments of the present disclosure, the source of the PMOS in each test unit is connected to a common first power supply VDD1, which is separate from the power supply of all other devices in the test circuit. The substrate end of the NMOS in each test unit is connected to a common substrate bias voltage source Vbs, and the voltage of the substrate bias voltage source Vbs is independently controlled by an external instrument.

[0105] When the input voltage of the test unit changes from high to low, the PMOS gradually opens. The substrate bias voltage source Vbs provides a substrate bias voltage for the substrate end of the NMOS. Due to the effect of the substrate bias voltage, the threshold voltage Vt of the NMOS is significantly increased, so the NMOS will be quickly turned off. At this time, the short-circuit current caused by the NMOS will be significantly suppressed.

[0106] When the input voltage of the test unit changes from low to high, the PMOS gradually closes. The substrate bias voltage source Vbs provides a substrate bias voltage for the substrate end of the NMOS. Due to the effect of the substrate bias voltage, the threshold voltage Vt of the NMOS is significantly increased, and the driving ability is poor, which causes the voltage of the source end common to the NMOS and the PMOS to decrease slowly. Therefore, when the gate voltage of the PMOS reaches the high level, the voltage of the source end of the PMOS is still maintained at a relatively high level. At this time, the short-circuit current caused by the PMOS will also be significantly suppressed. Moreover, at this time, the load circuit slowly discharges through the NMOS and finally returns to the initial state.

[0107] In some embodiments, the test circuit 100 can further include a current measurement element. When the input voltage of the test unit inverts, the current measurement element measures the current value of the current flowing out of the first power supply VDD1. The measured current value is the drive current of the PMOS in the test unit.

[0108] In some embodiments, when the input voltage of the test unit inverts, the proportion of the short-circuit current in the first power supply VDD1 port can be further reduced by continuously reducing the substrate bias voltage provided by the substrate end of the NMOS.

[0109] It can be understood that during the test, the multiple test units in the test circuit will be turned on in turn, so that the measured drive current is the average value of the PMOS in the multiple test units. In this way, the influence of process errors on the measurement result can be effectively eliminated.

[0110] The test circuit provided by the embodiments of the present disclosure can measure the accurate driving current of the PMOS in each test unit at the first power supply by connecting the source of the PMOS in each test unit to the independent first power supply and adjusting the threshold voltage of the NMOS in each test unit when the input end of the logic gate unit in the ring oscillator circuit occurs level inversion, thereby helping to obtain the influence of ion doping distribution on the effective current of the CMOS device and pointing out the direction for further improving the CMOS circuit delay.

[0111] Referring to Figure 7 , Figure 7 is a structural schematic diagram of another test circuit provided by the embodiments of the present disclosure. In some embodiments, the test circuit includes Figure 1 or Figure 5 the ring oscillator circuit, and a plurality of test units.

[0112] The structure of one of the test units 1021 is shown in an exemplary Figure 1 It can be understood that the structures of the other test units are consistent with the structure of the test unit 1021.

[0113] The test unit includes a first transistor NMOS and a second transistor PMOS, and the common gate of the first transistor and the second transistor is connected to the input end of the corresponding logic gate unit in the ring oscillator circuit; the source of the first transistor is connected to the first ground end GND1, the drain of the first transistor is connected to the drain of the second transistor, the substrate end of the second transistor is connected to the bias voltage source Vbs, and the source of the second transistor is connected to the first power supply VDD1.

[0114] The bias voltage source Vbs is used to provide a bias voltage for the substrate end of the second transistor when the input end of the logic gate unit occurs level inversion.

[0115] In some embodiments, the bias voltage source Vbs is used to provide a second bias voltage for the substrate end of the second transistor when the input end of the logic gate unit occurs level inversion, and the second bias voltage is a positive voltage to increase the absolute value of the threshold voltage of the second transistor.

[0116] The first ground end GND1 is independent of the second ground end GND2 connected to each logic gate unit in the ring oscillator circuit 101. The first power supply VDD1 can be independent of the second power supply VDD2 connected to each logic gate unit in the ring oscillator circuit 101, or can be the same power supply end.

[0117] In some embodiments, the test circuit 100 further comprises a second selection switch, which is used to disconnect the second ground terminal GND2 from the first ground terminal GND1 during the test, so that the second ground terminal GND2 is independent of the first ground terminal GND1.

[0118] In addition, each of the test units further comprises a load circuit, the common drain of the first transistor and the second transistor is connected to an input terminal of the load circuit, and an output terminal of the load circuit is left floating.

[0119] Optionally, the load circuit comprises a plurality of logic gate units connected in cascade.

[0120] The logic gate units in the load circuit are consistent with the logic gate units in the ring oscillator circuit. For example, when the logic gate units in the ring oscillator circuit are NOT gates, the logic gate units in the load circuit are also NOT gates.

[0121] It can be understood that, when the logic gate units in the load circuit are NOT gates, the load circuit can simulate the Miller effect of the parasitic capacitance when the next logic gate unit is used as the load of the current logic gate unit. In addition, the load circuit can also adjust the time of level inversion of the logic gate unit. If the load circuit does not exist, the level inversion of the logic gate unit will be very fast, which will result in difficulty in measuring the drive current of the test unit. That is, the load circuit can be equivalent to a parasitic capacitance.

[0122] In the embodiments of the present disclosure, the source of the NMOS in each test unit is connected to a common first ground terminal GND1, which is independent of the ground terminals of all other devices in the test circuit. The substrate terminal of the PMOS in each test unit is connected to a common substrate bias voltage source Vbs, the voltage of which is independently controlled by an external instrument.

[0123] When the input voltage of the test unit changes from low to high, the NMOS is gradually turned on. The substrate bias voltage source Vbs provides a substrate bias voltage for the substrate terminal of the PMOS. Due to the effect of the substrate bias voltage, the threshold voltage Vt of the PMOS is significantly increased, so the PMOS will be quickly turned off. At this time, the short-circuit current caused by the PMOS will be significantly suppressed.

[0124] As the input voltage of the test unit changes from high to low, the NMOS gradually turns off. The aforementioned substrate bias voltage source Vbs provides a substrate bias voltage to the substrate of the PMOS. Due to the influence of the substrate bias voltage, the threshold voltage Vt of the PMOS increases significantly, resulting in a decrease in its driving capability and a slower rate of rise of the common source voltage of the NMOS and PMOS. Therefore, when the gate voltage of the NMOS reaches a low level, its source voltage remains at a low level, and the short-circuit current caused by the NMOS is significantly suppressed. Moreover, the aforementioned load circuit is slowly charged through the PMOS and eventually returns to its initial state.

[0125] In some embodiments, the test circuit 100 may further include a current measuring element that measures the current value flowing into the first ground terminal GND1 when the input voltage of the test unit flips. The measured current value is the drive current of the NMOS in the test unit.

[0126] In some embodiments, when the input voltage of the test unit flips, the proportion of short-circuit current in the first ground terminal GND1 can be further reduced by continuously reducing the substrate bias voltage provided at the substrate end of the PMOS.

[0127] Understandably, during the testing process, since multiple test units in the above test circuit will be turned on sequentially, the measured drive current is the average value of the NMOS in multiple test units. This can effectively eliminate the influence of process errors on the measurement results.

[0128] The test circuit provided in this embodiment connects the source of the NMOS in each test unit to an independent first ground terminal, and adjusts the threshold bias voltage of the PMOS in each test unit when the input of the logic gate unit in the ring oscillator circuit undergoes a level flip. This allows for the accurate measurement of the NMOS driving current in each test unit at the first ground terminal, thereby helping to obtain the influence of ion doping distribution on the effective current of the CMOS device and pointing the way for further improvement of CMOS circuit delay.

[0129] Based on the test circuit 100 described in the above embodiments, this disclosure also provides a test method applied to the test circuit 100 described in the above embodiments, with reference to... Figure 8 As shown, Figure 8 This is a flowchart illustrating the steps of a testing method provided in an embodiment of this disclosure. The testing method includes:

[0130] S801 provides an enable control signal for the ring oscillator circuit.

[0131] In some implementations, after providing a high-level signal to the enable input En of the ring oscillator circuit, Figure 5The ring-shaped oscillation circuit 101 shown starts oscillation.

[0132] S802, when a level inversion occurs at the input end of the logic gate unit of the ring-shaped oscillation circuit, a first substrate bias voltage is provided for the substrate end of the first transistor by the substrate bias voltage source to adjust the threshold voltage of the first transistor.

[0133] In the embodiment, the first transistor is an NMOS, and the first substrate bias voltage is a negative voltage.

[0134] S803, the current value flowing out of the first power supply in the test circuit is detected, and the current value flowing out of the first power supply is determined as the driving current of the second transistor.

[0135] In the embodiment, the second transistor is a PMOS.

[0136] The test method provided by the embodiment can measure the accurate driving current of the PMOS in each test unit at the first power supply by adjusting the threshold voltage of the NMOS in each test unit when a level inversion occurs at the input end of the logic gate unit in the ring-shaped oscillation circuit.

[0137] Based on the test circuit 100 described in the above embodiment, a test method is also provided in the embodiment, which is applied to the test circuit 100 described in the above embodiment, and the test method comprises the steps of Figure 9 as shown in the above embodiment, Figure 9 is a step flow chart of another test method provided by the embodiment, and the test method comprises the steps of

[0138] S901, an enable control signal is provided for the ring-shaped oscillation circuit.

[0139] In some embodiments, after a high-level signal is provided for the enable input end En of the ring-shaped oscillation circuit, Figure 5 The ring-shaped oscillation circuit 101 shown starts oscillation.

[0140] S902, when a level inversion occurs at the input end of the logic gate unit of the ring-shaped oscillation circuit, a second substrate bias voltage is provided for the substrate end of the second transistor by the substrate bias voltage source to adjust the threshold voltage of the second transistor.

[0141] In the embodiment, the second transistor is a PMOS, and the second substrate bias voltage is a positive voltage.

[0142] S903, the current value flowing into the first ground end in the test circuit is detected, and the current value flowing into the first ground end is determined as the driving current of the first transistor.

[0143] In the embodiment, the first transistor is an NMOS.

[0144] The test method provided by the embodiment of the present disclosure can measure the accurate driving current of the NMOS in each test unit at the first ground end by connecting the source of the NMOS in each test unit to the independent first ground end and adjusting the threshold voltage of the PMOS in each test unit when the input end of the logic gate unit in the ring oscillator circuit occurs level inversion.

[0145] Further, based on the content described in the above embodiment, the embodiment of the present disclosure also provides a test device, which comprises at least one processor and a memory; wherein the memory stores computer execution instructions; and the at least one processor executes the computer execution instructions stored in the memory to realize each step in the test method described in the above embodiment, which will not be repeated here.

[0146] In order to better understand the embodiment of the present disclosure, refer to Figure 10 , Figure 10 The hardware structure schematic diagram of a test device provided by the embodiment of the present disclosure.

[0147] As Figure 10 shown, the test device of the embodiment comprises a processor 1001 and a memory 1002; wherein:

[0148] The memory 1002 is configured to store computer execution instructions.

[0149] The processor 1001 is configured to execute the computer execution instructions stored in the memory to realize each step in the test method described in the above embodiment, which can be referred to the related description in the foregoing method embodiment.

[0150] Optionally, the memory 1002 can be independent or integrated with the processor 1001.

[0151] When the memory 1002 is independently arranged, the device further comprises a bus 1003 for connecting the memory 1002 and the processor 1001.

[0152] It should be understood that, in several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the above-mentioned device embodiments are merely schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division mode, for example, a plurality of modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed ones can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0153] The modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0154] In addition, each functional module in each embodiment of the present disclosure can be integrated in one processing unit, or each module can exist physically alone, or two or more modules can be integrated in one unit. The unit of the above-mentioned modules can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0155] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A test circuit, characterized in that, It includes a ring oscillator circuit and several test units; The ring oscillator circuit includes multiple logic gate units that are cascaded in sequence to form a ring loop; The test unit includes a first transistor and a second transistor. The first transistor and the second transistor have different channel types. The common gate of the first transistor and the second transistor is connected to the input terminal of the logic gate unit. The source of the first transistor is connected to the first ground terminal. The drain of the first transistor is connected to the drain of the second transistor. The source of the second transistor is connected to the first power supply. The substrate of the first transistor is connected to a substrate bias voltage source, which provides a substrate bias voltage to the substrate of the first transistor when the input of the logic gate unit undergoes a level flip, so as to adjust the threshold voltage of the first transistor. Alternatively, the substrate of the second transistor is connected to a substrate bias voltage source, which provides a substrate bias voltage to the substrate of the second transistor when the input of the logic gate cell undergoes a level flip, so as to adjust the threshold voltage of the second transistor.

2. The test circuit according to claim 1, characterized in that, Each of the logic gate units includes an inverter, the inverter including a third transistor and a fourth transistor of different types, the third transistor being an NMOS and the fourth transistor being a PMOS; When the substrate of the first transistor is connected to the substrate bias voltage source, the source of the fourth transistor is connected to the second power supply, and the second power supply is independent of the first power supply. When the substrate of the second transistor is connected to the substrate bias voltage source, the source of the third transistor is connected to the second ground terminal, and the second ground terminal is independent of the first ground terminal.

3. The test circuit according to claim 1 or 2, characterized in that, The first-stage logic gate unit of the ring oscillator circuit is a NAND gate unit, which includes a first input terminal and a second input terminal. The first input terminal is used to receive an enable control signal; the second input terminal is connected to the output terminal of the last logic gate unit of the ring oscillator circuit.

4. The test circuit according to claim 1, characterized in that, The test unit also includes a load circuit; The common drain of the first transistor and the second transistor is connected to the input terminal of the load circuit, and the output terminal of the load circuit is left floating.

5. The test circuit according to claim 4, characterized in that, The load circuit includes a plurality of logic gate units cascaded in sequence.

6. The test circuit according to claim 2, characterized in that, It also includes current measuring elements; When the substrate of the first transistor is connected to the substrate bias voltage source, the current measuring element is connected to the first power supply to measure the current value flowing out of the first power supply, and the measured current value is used as the driving current of the second transistor in the test unit.

7. The test circuit according to claim 2, characterized in that, It also includes current measuring elements; When the substrate of the second transistor is connected to the substrate bias voltage source, the current measuring device is connected to the first ground terminal to measure the current flowing into the first ground terminal, and the measured current value is used as the driving current of the first transistor in the test unit.

8. The test circuit according to claim 2, characterized in that, It also includes a first selection switch; When the substrate of the first transistor is connected to the substrate bias voltage source, the first selection switch is used to disconnect the connection between the second power supply and the first power supply, so that the second power supply and the first power supply are independent of each other.

9. The test circuit according to claim 2, characterized in that, It also includes a second selection switch; When the substrate terminal of the second transistor is connected to the substrate bias voltage source, the second selection switch is used to disconnect the connection between the second ground terminal and the first ground terminal, so that the second ground terminal and the first ground terminal are independent of each other.

10. The test circuit according to claim 2, characterized in that, When the substrate terminal of the first transistor is connected to the substrate bias voltage source, the substrate bias voltage source is used to provide a first substrate bias voltage to the substrate terminal of the first transistor when the input terminal of the logic gate unit undergoes a level flip, and the first substrate bias voltage is a negative voltage. When the substrate of the second transistor is connected to the substrate bias voltage source, the substrate bias voltage source is used to provide a second substrate bias voltage to the substrate of the second transistor when the input of the logic gate unit undergoes a level flip, and the second substrate bias voltage is a positive voltage.

11. The test circuit according to any one of claims 6 to 10, characterized in that, The first transistor is an NMOS, and the second transistor is a PMOS.

12. The test circuit according to claim 1, characterized in that, The number of logic gates in the ring oscillator circuit is odd, and the number of test units is less than or equal to the number of logic gates.

13. A testing method, characterized in that, The method, applied to the test circuit according to any one of claims 1 to 12, comprises: Provide an enable control signal for the ring oscillator circuit; When the input of the logic gate unit undergoes a level flip, the substrate bias voltage source is used to provide a first substrate bias voltage to the substrate of the first transistor. The current value flowing out of the first power source is detected, and the current value flowing out of the first power source is determined as the driving current of the second transistor.

14. A testing method, characterized in that, The method, applied to the test circuit according to any one of claims 1 to 12, comprises: Provide an enable control signal for the ring oscillator circuit; When the input of the logic gate unit undergoes a level flip, the substrate bias voltage source is used to provide a second substrate bias voltage to the substrate of the second transistor. The current value flowing into the first ground terminal is detected, and the current value flowing into the first ground terminal is determined as the driving current of the first transistor.

15. A testing device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the test method as described in claim 13 or 14.

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