A radar digital processor test system

Abstract

This application belongs to the field of radar digital processor testing technology, specifically relating to a radar digital processor testing system, including a computer and a differential VAG converter, wherein the differential VAG converter is connected to a digital radar processor; the computer integrates: an interface driver module; a video acquisition board with a Mini PCIe interface, connected to the interface driver module and the differential VAG converter; a fiber optic bus board, a 1553B bus board, an ARINC429 bus board, a multi-protocol serial bus board, and a discrete signal board with a Mini PCIe interface, all connected to the interface driver module and the digital radar processor; a video acquisition module connected to the interface driver module; an interface communication module, an interface data processing module, and an internal bus testing module connected to the interface channel module; and a comprehensive display and control simulation module connected to the interface data processing module and the video acquisition module.

Description

Technical Field

[0001] This application belongs to the field of radar digital processor testing technology, and specifically relates to a radar digital processor testing system. Background Technology

[0002] The radar digital processor test system is used to conduct comprehensive tests on the various functions and performance of the radar digital processor, covering the entire life cycle of the radar digital processor, from scheme design and product development to final use and maintenance.

[0003] Currently, radar digital processor testing systems adopt a "PXI / PCI bus specification + hardware system + software development platform" solution, which is large in size and weight, making it difficult to troubleshoot in field tests.

[0004] This application is made in view of the aforementioned technical deficiencies.

[0005] It should be noted that the above background information is only used to assist in understanding the inventive concept and technical solution of this invention, and it does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above information was disclosed on the filing date of this application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0006] The purpose of this application is to provide a radar digital processor testing system to overcome or mitigate at least one of the known technical defects.

[0007] The technical solution of this application is:

[0008] A radar digital processor testing system includes a computer and a differential VAG converter, wherein...

[0009] The differential VAG converter is connected to the digital radar processor to perform differential VAG conversion on the video signal emitted from the digital radar processor;

[0010] The computer integrates:

[0011] Interface driver module;

[0012] The video capture board with a Mini PCIe interface is connected to the interface driver module and the differential VAG converter to receive video signals.

[0013] The Mini PCIe interface fiber optic bus board connects to the interface driver module and the digital radar processor to receive fiber optic signals from the digital radar processor.

[0014] The 1553B bus board with the Mini PCIe interface is connected to the interface driver module and the digital radar processor to receive 1553B bus signals from the digital radar processor.

[0015] The ARINC429 bus board with a Mini PCIe interface is connected to the digital radar processor to receive ARINC429 bus signals from the digital radar processor.

[0016] The Mini PCIe interface multi-protocol serial bus board connects to the interface driver module and the digital radar processor to receive multi-protocol serial bus signals from the digital radar processor.

[0017] The discrete signal board with the Mini PCIe interface connects to the interface driver module and the digital radar processor to receive discrete signals from the digital radar processor.

[0018] The video acquisition module connects to the interface driver module to enable the parsing and processing of video signals;

[0019] The interface communication module connects to the interface driver module.

[0020] The interface data processing module is connected to the interface channel module to perform analysis and processing of fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0021] The internal bus test module connects to the interface channel module to test fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0022] The integrated display and control simulation module connects with the interface data processing module and the video acquisition module to display video signals and add fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals to the display screen of the video signals.

[0023] According to at least one embodiment of this application, in the radar digital processor test system described above, the integrated display and control simulation module can send instructions to the digital radar processor through the interface data processing module, interface communication module, interface driver module, as well as fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, so that the digital radar processor can generate corresponding responses.

[0024] According to at least one embodiment of this application, the radar digital processor test system described above further includes:

[0025] The bus real-time monitoring module is connected to the interface data processing module to display digital signals such as fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0026] According to at least one embodiment of this application, in the radar digital processor test system described above, the bus real-time monitoring module can send instructions to the digital radar processor through the interface data processing module, interface communication module, interface driver module, and fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, so that the digital radar processor can generate corresponding responses.

[0027] According to at least one embodiment of this application, the radar digital processor test system described above further includes:

[0028] The bus real-time recording module is connected to the interface communication module to record fiber optic signals.

[0029] According to at least one embodiment of this application, in the radar digital processor test system described above, the bus real-time recording module can play back the fiber optic signal to the digital radar processor through the interface communication module, the interface driver module, and the fiber optic bus board, so that the digital radar processor generates a corresponding response.

[0030] According to at least one embodiment of this application, the radar digital processor test system described above further includes:

[0031] The navigation data simulation module, connected to the interface data processing module, can simulate navigation data. Through the interface data processing module, interface communication module, interface driver module, as well as fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, it sends instructions to the digital radar processor, causing the digital radar processor to generate corresponding responses. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the configuration of the radar digital processor test system provided in the embodiments of this application;

[0033] Figure 2 This is a schematic diagram of the architecture of the radar digital processor test system provided in the embodiments of this application.

[0034] To better illustrate this embodiment, some parts in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual size of the product. Furthermore, the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent. Detailed Implementation

[0035] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings. Other related parts can be referred to the general design. In the absence of conflict, the embodiments and technical features in the embodiments of this application can be combined with each other to obtain new embodiments.

[0036] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "upper," "lower," "left," "right," "center," "vertical," "horizontal," "inner," and "outer," etc., used in this application description to indicate relative direction or positional relationship are used only to indicate relative orientation or positional relationship, and do not imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation. When the absolute position of the described object changes, its relative positional relationship may also change accordingly, and therefore should not be construed as a limitation on this application. The terms "first," "second," "third," and similar terms used in this application description are used only for descriptive purposes to distinguish different components, and should not be construed as indicating or implying relative importance. The terms "a," "one," or "the," etc., used in this application description should not be construed as an absolute limitation on quantity, but should be construed as indicating the existence of at least one. The terms "including," "comprising," etc., used in this application description mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0037] Furthermore, it should be noted that, unless otherwise explicitly specified and limited, terms such as “installation,” “connection,” and “linkage” used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; or it can be a connection within two components. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.

[0038] The following is in conjunction with the appendix Figures 1 to 2 This application will be described in further detail.

[0039] A radar digital processor testing system includes a computer and a differential VAG converter, wherein...

[0040] The differential VAG converter is connected to the digital radar processor to perform differential VAG conversion on the video signal emitted from the digital radar processor;

[0041] The computer integrates:

[0042] Interface driver module;

[0043] The video capture board with a Mini PCIe interface is connected to the interface driver module and the differential VAG converter to receive video signals.

[0044] The Mini PCIe interface fiber optic bus board connects to the interface driver module and the digital radar processor to receive fiber optic signals from the digital radar processor.

[0045] The 1553B bus board with the Mini PCIe interface is connected to the interface driver module and the digital radar processor to receive 1553B bus signals from the digital radar processor.

[0046] The ARINC429 bus board with a Mini PCIe interface is connected to the digital radar processor to receive ARINC429 bus signals from the digital radar processor.

[0047] The Mini PCIe interface multi-protocol serial bus board connects to the interface driver module and the digital radar processor to receive multi-protocol serial bus signals from the digital radar processor.

[0048] The discrete signal board with the Mini PCIe interface connects to the interface driver module and the digital radar processor to receive discrete signals from the digital radar processor.

[0049] The video acquisition module connects to the interface driver module to enable the parsing and processing of video signals;

[0050] The interface communication module connects to the interface driver module.

[0051] The interface data processing module is connected to the interface channel module to perform analysis and processing of fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0052] The internal bus test module connects to the interface channel module to test fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0053] The integrated display and control simulation module connects with the interface data processing module and the video acquisition module to display video signals and add fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals to the display screen of the video signals.

[0054] For the radar digital processor test system disclosed in the above embodiments, those skilled in the art will understand that the computer mentioned therein can be a portable ruggedized laptop, which can be configured with multiple Mini PCIe interface slots for the insertion of Mini PCIe interface video acquisition boards, Mini PCIe interface fiber optic bus boards, Mini PCIe interface 1553B bus boards, Mini PCIe interface ARINC429 bus boards, Mini PCIe interface multi-protocol serial bus boards, Mini PCIe interface discrete signal boards, etc., to form corresponding functional modules, making the radar digital processor test system modular, miniaturized, and lightweight, easy to carry and use. In addition, the computer can be configured with multiple PXIe interface slots to facilitate expansion, which can improve the scalability, maintainability, and reusability of the radar digital processor test system.

[0055] In one specific embodiment, the portable ruggedized laptop internally uses an i7 processor, 16GB of memory, and provides interfaces such as Gigabit Ethernet, USB, and DP video. It comes standard with a 1TB SATA SSD and offers eight Mini PCIe functional modules and two PXIe expansion modules. For details, please refer to [link / reference needed]. Figure 1 .

[0056] In some optional embodiments, in the radar digital processor test system described above, the integrated display and control simulation module can send instructions to the digital radar processor through the interface data processing module, interface communication module, interface driver module, as well as fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, so that the digital radar processor can generate corresponding responses. These instructions can be radar operating mode switching, time information transmission, and radar power on / off, etc.

[0057] In some optional embodiments, the radar digital processor test system described above further includes:

[0058] The bus real-time monitoring module is connected to the interface data processing module to display digital signals such as fiber optic signals, 1553B bus signals, ARINC429 bus signals, multi-protocol serial bus signals, and discrete signals.

[0059] In some optional embodiments, in the radar digital processor test system described above, the bus real-time monitoring module can send instructions to the digital radar processor through the interface data processing module, interface communication module, interface driver module, as well as fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, so that the digital radar processor can generate corresponding responses. These instructions may include obtaining radar operating status, obtaining waveform parameters, and obtaining ATE status information.

[0060] In some optional embodiments, the radar digital processor test system described above further includes:

[0061] The bus real-time recording module is connected to the interface communication module to record fiber optic signals.

[0062] In some optional embodiments, in the radar digital processor test system described above, the bus real-time recording module can play back the fiber optic signal to the digital radar processor through the interface communication module, the interface driver module, and the fiber optic bus board, so that the digital radar processor can generate a corresponding response.

[0063] In some optional embodiments, the radar digital processor test system described above further includes:

[0064] The navigation data simulation module, connected to the interface data processing module, can simulate navigation data. Through the interface data processing module, interface communication module, interface driver module, as well as fiber optic bus board, 1553B bus board, ARINC429 bus board, multi-protocol serial bus board, and discrete signal board, it sends commands to the digital radar processor, causing the digital radar processor to generate corresponding responses. These commands can be inertial navigation information transmission and flight parameter control, etc.

[0065] The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0066] Furthermore, those skilled in the art should recognize that the various modules of the radar digital processor test system disclosed in the embodiments of this application can be implemented in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, they are generally described in terms of function in this application. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can choose different methods to implement the described functions for each specific application and its actual constraints, but such implementation should not be considered to be beyond the scope of this application.

[0067] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A radar digital processor test system, characterized by, The system comprises a computer, a differential VAG converter, wherein, The differential VAG converter is connected with the digital radar processor to enable differential VAG conversion of the video signal from the digital radar processor; The computer is integrated with: an interface driving module; a video acquisition board card of Mini PCIe interface, connected with the interface driving module and the differential VAG converter to enable reception of the video signal; a fiber bus board card of Mini PCIe interface, connected with the interface driving module and the digital radar processor to enable reception of the fiber signal from the digital radar processor; a 1553B bus board card of Mini PCIe interface, connected with the interface driving module and the digital radar processor to enable reception of the 1553B bus signal from the digital radar processor; an ARINC429 bus board card of Mini PCIe interface, connected with the digital radar processor to enable reception of the ARINC429 bus signal from the digital radar processor; a multi-protocol serial bus board card of Mini PCIe interface, connected with the interface driving module and the digital radar processor to enable reception of the multi-protocol serial bus signal from the digital radar processor; a discrete signal board card of Mini PCIe interface, connected with the interface driving module and the digital radar processor to enable reception of the discrete signal from the digital radar processor; a video acquisition module, connected with the interface driving module to enable analysis and processing of the video signal; an interface communication module, connected with the interface driving module; an interface data processing module, connected with the interface channel module to enable analysis and processing of the fiber signal, the 1553B bus signal, the ARINC429 bus signal, the multi-protocol serial bus signal and the discrete signal; an internal bus test module, connected with the interface channel module to enable testing of the fiber signal, the 1553B bus signal, the ARINC429 bus signal, the multi-protocol serial bus signal and the discrete signal; a comprehensive display control simulation module, connected with the interface data processing module and the video acquisition module to enable display of the video signal and attachment of the fiber signal, the 1553B bus signal, the ARINC429 bus signal, the multi-protocol serial bus signal and the discrete signal to the display picture of the video signal.

2. The radar digital processor test system according to claim 1, wherein the comprehensive display control simulation module can issue instructions to the digital radar processor through the interface data processing module, the interface communication module, the interface driving module, and the fiber bus board card, the 1553B bus board card, the ARINC429 bus board card, the multi-protocol serial bus board card and the discrete signal board card, so that the digital radar processor generates corresponding responses.

3. The radar digital processor test system according to claim 1, further comprising: a bus real-time monitoring module, connected with the interface data processing module to enable display of the digital signals of the fiber signal, the 1553B bus signal, the ARINC429 bus signal, the multi-protocol serial bus signal and the discrete signal. ​ 4. The radar digital processor test system of claim 3, wherein the bus real-time monitoring module is capable of issuing instructions to the digital radar processor through the interface data processing module, the interface communication module, the interface driving module, and the fiber bus board card, the 1553B bus board card, the ARINC429 bus board card, the multi-protocol serial bus board card, and the discrete signal board card, so that the digital radar processor generates corresponding responses.

5. The radar digital processor test system of claim 1, wherein the bus real-time monitoring module is capable of issuing instructions to the digital radar processor through the interface data processing module, the interface communication module, the interface driving module, and the fiber bus board card, so that the digital radar processor generates corresponding responses.

6. The radar digital processor test system of claim 1, wherein the bus real-time recording module is connected to the interface communication module to record the fiber signal.

7. The radar digital processor test system of claim 1, wherein the bus real-time recording module is capable of playing back the fiber signal to the digital radar processor through the interface communication module, the interface driving module, and the fiber bus board card, so that the digital radar processor generates corresponding responses.

8. The radar digital processor test system of claim 1, further comprising a navigation data simulation module connected to the interface data processing module to simulate navigation data, and issue instructions to the digital radar processor through the interface data processing module, the interface communication module, the interface driving module, and the fiber bus board card, the 1553B bus board card, the ARINC429 bus board card, the multi-protocol serial bus board card, and the discrete signal board card, so that the digital radar processor generates corresponding responses. ​ ​ ​ ​ ​

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