A data restoration detection method and device of an image input interface and a storage medium

Abstract

The application provides a data restoration detection method and device of an image input interface and a storage medium, and the method comprises the following steps: a Training unit is arranged on the data input side of a Video Capture unit; a Clock signal is acquired, a delay value of the Clock signal is adjusted by using a Block delay unit, clock CLKP and / or clock CLKN are generated, and the clock CLKP and / or clock CLKN are input to a Training_ctrl unit; the delay stage of the Block delay unit is controlled by using the Training_ctrl unit, an adjustment strategy is used to adjust the ctrl and data signals to meet the Clock signal sampling input, and the delay setting interval meeting the requirement is recorded; the control information of an RGB interface protocol is used as a basis for judging whether the Clock signal correctly samples data; after the Training_ctrl unit acquires the effective adjustment value, the adjustment value is directly transmitted to a processing module, so that the data restoration of the image input interface is completed. Through the detection and adjustment circuit, the image data can be truly restored, so that the image data timing meets the CEA / VESA standard specification.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically to a data restoration and detection method for an image input interface and a training unit applied to the algorithm, and also to a computer device and storage medium for implementing the above method. Background Technology

[0002] With the increasing popularity of high-resolution LCD screens, there is a greater demand for transmission bandwidth. For example, with RGB interfaces, the total bandwidth per unit time can be increased by increasing the clock speed. In addition, some screens use the DDR data format for their data interfaces, which can double the transmission bandwidth per unit clock speed, thus meeting the transmission requirements of higher resolution images.

[0003] For typical data format interfaces, such as DDR, DRAM, and SDIO interfaces, a training process is required to ensure that both the sender and receiver sample based on the correct clock. During training, the sender transmits specific data to the receiver, which then uses the training process to ensure effective data reconstruction. However, RGB input image interfaces do not have a protocol-defined training step. Therefore, the sender does not transmit the specific data required for training, and the receiver cannot perform training to reconstruct the data.

[0004] Currently, existing RGB input image interface chip circuits, such as those supporting BT.656 / BT.601 / BT.1120 / RGB888, typically use a single or double edge of the clock to sample input data and then reconstruct the image data. If the resolution is high, the clock frequency may be relatively high, resulting in a small timing margin between the clock line and the data or control lines. In addition, the presence of different corners in the chip can easily lead to unstable data sampling regions or even metastable conditions. This can make the timing sequence unstable and not fully compliant with the standard, potentially causing image errors. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a data restoration detection method, device and storage medium for an image input interface. The method can restore image data in a realistic way by detecting and adjusting the circuit, so that the timing of the image data meets the standards and specifications such as CEA / VESA.

[0006] In a first aspect, the present invention provides a data restoration detection method for an image input interface, comprising: setting a Training unit on the data input side of a VideoCapture unit; acquiring a Clock signal, adjusting the delay value of the Clock signal using a Block delay unit, generating a clock CLKP and / or a clock CLKN, and inputting the clock CLKP and / or clock CLKN to a Training_ctrl unit; using the Training_ctrl unit to control the delay level of the Block delay unit, and using an adjustment strategy to adjust it to meet the requirements of the ctrl and data signals for Clock signal sampling input, and recording the delay setting interval that meets the requirements; using the control information of the RGB interface protocol as the basis for judging the correct sampling data of the Clock signal; and after the Training_ctrl unit acquires a valid adjustment value, directly transmitting it to a processing module to complete the data restoration of the image input interface.

[0007] According to the data restoration detection method for an image input interface provided by the present invention, the Training unit includes a Block delay unit, an inverter, and a Training_ctrl unit. The Block delay unit is used to adjust the clock delay of the input clock, the inverter is used to output an inverted clock CLKN, and the Training_ctrl unit is used to control the delay level of the Block delay unit.

[0008] According to the data restoration detection method of the image input interface provided by the present invention, the clock signal after passing through the Block delay unit is directly output by the Block delay unit as clock CLKP, and the clock signal after passing through the Block delay unit is inverted by an inverter to obtain an inverted clock CLKN. If the image input interface is in DDR protocol mode, clocks CLKN and CLKP are used simultaneously as the data sampling clock edge.

[0009] According to the data restoration detection method of the image input interface provided by the present invention, assuming that the designed Blockdelay unit has n levels, the adjustment strategy of the Block delay unit is configured using the Training_ctrl unit, including: increasing the adjustment from level 0 until the correctly sampled data is obtained to obtain the minimum effective delay value, then decreasing the adjustment from level n-1 until the correctly sampled data is obtained to obtain the maximum effective delay value, and then taking the midpoint between the minimum effective delay value and the maximum effective delay value as the final result;

[0010] According to the data restoration detection method of the image input interface provided by the present invention, assuming that the designed Blockdelay unit has n levels, the adjustment strategy of the Block delay unit is configured using the Training_ctrl unit, including: increasing the adjustment from level 0, recording the configuration of all erroneous sampling data, and then selecting the configuration farthest from all erroneous configurations as the optimal configuration.

[0011] According to the data restoration detection method of the image input interface provided by the present invention, assuming that the designed Blockdelay unit has n levels, the adjustment strategy of the Block delay unit is configured using the Training_ctrl unit, including: setting a threshold m, adjusting it incrementally from level 0, and if it is detected that the delay configured for m consecutive times has been correctly sampled, then the median value of the configuration configured for these m consecutive times is selected as the final result.

[0012] According to the data restoration detection method of the image input interface provided by the present invention, for the BT.656 / BT.1120 protocol containing SAV / EAV key codes, the method determines whether the collected continuous data satisfies the SAV / EAV key codes as the criterion for correctness.

[0013] According to the data restoration detection method of the image input interface provided by the present invention, for the BT.601 or RGB interface, since the interface has control signals and meets the timing protocol, one or more conditions are configured to be used as valid judgment criteria, or the continuous satisfaction of a single condition is configured as valid judgment criteria.

[0014] According to the data restoration detection method for an image input interface provided by the present invention, after the Training_ctrl unit obtains a valid adjustment value, it outputs an interrupt status to notify the system that the correction has been completed, as well as the corresponding status.

[0015] Therefore, compared with the existing technology, the present invention can be applied to RGB input image interface chip circuits. It mainly adds a simple internal training method to the RGB input image interface, ensuring that the image data can be restored correctly quickly and conveniently without adding any requirements to the sender.

[0016] Therefore, this invention adds a training logic to the Video Capture unit to ensure that the correct data can be sampled, thereby avoiding unstable regions or metastability issues when sampling multi-bit data buses from different corner ICs.

[0017] In a second aspect, the present invention also provides an electronic device, comprising:

[0018] Memory, which stores computer-executable instructions;

[0019] The processor is configured to run computer-executable instructions.

[0020] The computer-executable instructions, when executed by the processor, implement the steps of the data restoration and detection method for any of the above-mentioned image input interfaces.

[0021] Thirdly, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the steps of the data restoration detection method for any of the above-described image input interfaces.

[0022] Therefore, the present invention provides an electronic device and storage medium for a data restoration detection method for an image input interface, comprising: one or more memories and one or more processors. The memories are used to store program code and intermediate data generated during program execution, storage of model output results, and storage of the model and model parameters; the processors are used for the processor resources occupied by the code execution and multiple processor resources occupied during model training.

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0024] Figure 1 This is a system schematic diagram of an embodiment of a data restoration and detection method for an image input interface according to the present invention.

[0025] Figure 2 This is a schematic diagram of the Training unit in an embodiment of the data restoration and detection method for an image input interface according to the present invention.

[0026] Figure 3 This is a flowchart of an embodiment of a data restoration and detection method for an image input interface according to the present invention.

[0027] Figure 4 This is a schematic diagram illustrating the principle of the FIFO controller controlling the input and output of data in an embodiment of a data restoration and detection method for an image input interface according to the present invention.

[0028] Figure 5 This is a schematic diagram of a data restoration detection method for an image input interface according to the present invention, in which a training unit is added between the data input interface and the FIFO controller.

[0029] Figure 6 This is a schematic diagram of the BT.1120 interface in an embodiment of a data restoration and detection method for an image input interface according to the present invention.

[0030] Figure 7 This is a schematic diagram illustrating the timing aspect of an embodiment of a data restoration and detection method for an image input interface according to the present invention. Detailed Implementation

[0031] See Figures 1 to 3 The present invention provides a data restoration detection method for an image input interface, comprising:

[0032] Step S1: A Training unit is provided on the data input side of the Video Capture unit;

[0033] Step S2: Obtain the Clock signal, adjust the delay value of the Clock signal using the Block delay unit, generate clock CLKP and / or clock CLKN, and input clock CLKP and / or clock CLKN to the Training_ctrl unit;

[0034] Step S3: Use the Training_ctrl unit to control the delay level of the Block delay unit, and use an adjustment strategy to adjust it to meet the ctrl and data signals of the Clock signal sampling input, and record the delay setting interval that meets the requirements.

[0035] Step S4: Use the control information of the RGB interface protocol as the basis for judging the correct sampling data of the Clock signal;

[0036] Step S5: After obtaining the valid adjustment value in the Training_ctrl unit, it is directly transmitted to the processing module to complete the data restoration of the image input interface.

[0037] In this embodiment, the Training unit includes a Block delay unit, an inverter, and a Training_ctrl unit. The Block delay unit is used to adjust the clock delay of the input clock, the inverter is used to output an inverted clock CLKN, and the Training_ctrl unit is used to control the delay level of the Block delay unit.

[0038] In step S1 above, the Video Capture unit mainly includes a FIFO controller, which controls the data input and data output, such as... Figure 4 As shown. The training implementation method added in this embodiment is equivalent to adding a training unit between the input interface and the FIFO interface. It is responsible for transmitting the data to the next-level FIFO unit after the data input interface has been calibrated, such as... Figure 5As shown.

[0039] Specifically, the Training structure block diagram added to the Video Capture unit in this embodiment is as follows: Figure 2 As shown: The input Clock signal first passes through a Block Delay unit to generate clock CLKP and / or clock CLKN (if it's a dual-edge DDR mode), and then passes through a Training ctrl unit. The Block Delay unit adjusts the delay value of the Clock signal; its number of stages can be planned according to design requirements. The Training ctrl unit controls the delay stages of the Block Delay unit, employing a specific detection strategy to adjust the clock signal so that it can correctly sample the input ctrl and data signals, and records the required delay setting range. Additionally, the control information of the RGB interface protocol itself is used as the basis for judging whether the clock data is correctly sampled. Therefore, this design effectively solves the problem of physical timing skew alignment between the clock and multi-bit data, avoiding sampling unstable or metastable data regions, and ensuring correct data reconstruction.

[0040] In step S2 above, the Clock signal after passing through the Block delay unit is directly output by the Block delay unit as clock CLKP. The Clock signal after passing through the Block delay unit is inverted by an inverter to obtain an inverted clock CLKN. If the image input interface is in DDR protocol mode, then clocks CLKN and CLKP are used simultaneously as the data sampling clock edge.

[0041] In this embodiment, assuming the designed Block delay unit has n levels, the adjustment strategy for the Block delay unit is configured using the Training_ctrl unit, including:

[0042] The adjustment is incremented starting from level 0 until the correctly sampled data is obtained, resulting in the minimum effective delay value. Then, the adjustment is decremented starting from level n-1 until the correctly sampled data is obtained, resulting in the maximum effective delay value. Finally, the midpoint between the minimum and maximum effective delay values ​​is taken as the final result.

[0043] In this embodiment, assuming the designed Block delay unit has n levels, the adjustment strategy for the Block delay unit is configured using the Training_ctrl unit, including:

[0044] Starting from level 0, the configuration is adjusted incrementally, and all erroneous sampled data configurations are recorded. Then, the configuration furthest from all erroneous configurations is selected as the optimal configuration.

[0045] In this embodiment, assuming the designed Block delay unit has n levels, the adjustment strategy for the Block delay unit is configured using the Training_ctrl unit, including:

[0046] Set a threshold m, and adjust it incrementally starting from level 0. If the delay configuration is correctly sampled in m consecutive settings, then the median of these m consecutive correctly sampled settings is selected as the final result.

[0047] In this embodiment, for protocols containing SAV / EAV key codes in BT.656 / BT.1120, the correctness of the data is determined by whether the collected continuous data satisfies the SAV / EAV key code codes.

[0048] In this embodiment, for the BT.601 or RGB interface, since the interface has control signals and meets the timing protocol, one or more conditions can be configured to be detected as valid judgment criteria, or the continuous satisfaction of a single condition can be configured as valid judgment criteria.

[0049] In this embodiment, after the Training_ctrl unit obtains a valid adjustment value, it outputs an interrupt status to notify the system that the correction is complete, along with the corresponding status.

[0050] In practical applications, the technical solution of this invention is mainly used in, for example... Figure 1 In the application scenario shown, video data passes through the Video Capture unit, either writing the video data back to memory or capturing the data and outputting the image data to the next-level image processing unit (video post-process) according to the standard timing sequence.

[0051] This invention primarily addresses the data restoration problem of BT.656 / BT.601 / BT.1120 / RGB video input interfaces, including the following methods:

[0052] A. The BT.656 and BT.1120 interfaces do not have control signals, only data signals. However, the data signals contain a header signal with fixed codewords SEV / EAV to indicate timing information, such as... Figure 6 The BT.1120 shown.

[0053] B. The BT.601 and RGB video interfaces have control signals and data signals, and the timing content is as follows: Figure 7As shown.

[0054] The method provided by this invention adds a training logic to the Video Capture unit, which can ensure that the correct data is sampled correctly. This can avoid unstable regions or metastability issues when sampling multi-bit data buses from different corner ICs. The specific implementation scheme is as follows:

[0055] 1. Design a block delay unit that meets the design requirements for the number of stages. Its function is to adjust the clock delay of the input clock. The clock delay value of each stage can be planned in advance according to the application requirements. The adjustable stage range can also be planned according to the design requirements, such as designing 32 stages or 64 stages. Usually, the adjustable clock delay range should ideally cover one cycle or half a cycle of the input frequency.

[0056] 2. The clock after passing through the Block delay unit is inverted by an inverter to obtain the inverted clock CLKN. If the image input interface is in DDR protocol mode, both the inverted clock CLKN and the clock CLKP are used as the data sampling clock edge.

[0057] 3. The functions to be implemented by the Training_ctrl unit include:

[0058] A. Configurable Block delay unit adjustment strategy. Taking the adjustment of a 32-level Block delay unit as an example, multiple adjustment strategies can be configured, such as: (1) Incremental adjustment starting from level 0 until the determination that the data can be sampled correctly is obtained, and the minimum effective delay value is obtained. Then, decreaseal adjustment starting from level 31 until the determination that the data can be sampled correctly is obtained, and the maximum effective delay value is obtained. Then, the middle value between the two is selected as the final result; (2) Incremental adjustment starting from level 0, record the configuration of all incorrect sampled data, and then select the configuration that is farthest from all incorrect configurations as the best configuration; (3) Set a threshold m, increment the adjustment starting from level 0, and if the delay of m consecutive configurations is detected to be correctly sampled, then select the median value of these m consecutive correctly sampled configurations as the final result.

[0059] B. For protocols like BT.656 / BT.1120 that have SAV / EAV key codes, the correctness of a data sample is determined by whether the collected continuous data satisfies the SAV / EAV key code. Alternatively, multiple consecutive checks can be configured as a valid determination.

[0060] C. For BT.601 or RGB interfaces, since the interface has control signals such as DE / VSYNC / HSYNC, and they meet some common timing protocols, such as the effective clock count value of DE for each line must be equal, the effective pulse width of HSYNC must be equal, or the clock count value between HSYNC pulses must be equal, the pulse width of VSYNC must be an integer number of clock count values ​​between HSYNC pulses, or the clock count value between VSYNC pulses must be equal, etc., one or more conditions can be configured to be detected as valid judgment criteria, or the continuous satisfaction of a single condition can be flexibly configured as valid judgment criteria.

[0061] D. Once the final training calibration is completed and a valid adjustment value is obtained, an interrupt status notification will be output to the system to indicate that training is complete, along with the corresponding status.

[0062] E. It can be configured by the system to output only the image data after training is completed.

[0063] Therefore, compared with the existing technology, the present invention can be applied to RGB input image interface chip circuits. It mainly adds a simple internal training method to the RGB input image interface, ensuring that the image data can be restored correctly quickly and conveniently without adding any requirements to the sender.

[0064] Therefore, this invention adds a training logic to the Video Capture unit to ensure that the correct data can be sampled, thereby avoiding unstable regions or metastability issues when sampling multi-bit data buses from different corner ICs.

[0065] In one embodiment, an electronic device is provided, which may be a server. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the electronic device provides computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the electronic device stores data. The network interface of the electronic device is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a data reconstruction detection method for an image input interface.

[0066] Those skilled in the art will understand that the electronic device structure shown in this embodiment is only a partial structure related to the solution of this application and does not constitute a limitation on the electronic device to which the solution of this application is applied. The specific electronic device may include more or fewer components than shown in this embodiment, or combine certain components, or have different component arrangements.

[0067] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0068] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0069] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] Therefore, the present invention provides an electronic device and storage medium for a data restoration detection method for an image input interface, comprising: one or more memories and one or more processors. The memories are used to store program code and intermediate data generated during program execution, storage of model output results, and storage of the model and model parameters; the processors are used for the processor resources occupied by the code execution and multiple processor resources occupied during model training.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A method of data restoration detection for an image input interface, characterized by, The method comprises: A Training unit is arranged on the data input side of the Video Capture unit; A Clock signal is acquired, the delay value of the Clock signal is adjusted by using a Block delay unit, clock CLKP and / or clock CLKN are generated, and the clock CLKP and / or clock CLKN are input to the Training_ctrl unit; The delay stage of the Block delay unit is controlled by using the Training_ctrl unit, an adjustment strategy is used to adjust the ctrl and data signals that meet the Clock signal sampling input, and the delay setting interval that meets the requirement is recorded; Control information of an RGB interface protocol is used as a basis for judging correct sampling of data of the Clock signal; After the valid adjustment value is acquired by the Training_ctrl unit, the valid adjustment value is directly transmitted to a processing module to complete data restoration of the image input interface; The Training unit comprises a Block delay unit, an inverter and a Training_ctrl unit, the Block delay unit is used to adjust the clock delay of the input clock, the inverter is used to output the inverted clock CLKN, and the Training_ctrl unit is used to control the delay stage of the Block delay unit; The Clock signal after the Block delay unit is directly output as clock CLKP by the Block delay unit, the Clock signal after the Block delay unit is inverted by the inverter to obtain the inverted clock CLKN, and if the image input interface is in a DDR protocol mode, the clock CLKN and CLKP are used as data sampling clock edges at the same time; Suppose that the designed Block delay unit is n stages, the adjustment strategy of the Block delay unit is configured by using the Training_ctrl unit, and the adjustment strategy comprises: From 0 stage, the adjustment is increased until the correctly sampled data is acquired, the minimum valid delay value is obtained, then from n-1 stage, the adjustment is decreased until the correctly sampled data is acquired, the maximum valid delay value is obtained, then the middle number of the minimum valid delay value and the maximum valid delay value is taken as the final result.

2. The method of claim 1, wherein: Suppose that the designed Block delay unit is n stages, the adjustment strategy of the Block delay unit is configured by using the Training_ctrl unit, and the adjustment strategy comprises: From 0 stage, the adjustment is increased, all the error sampling data configurations are recorded, and then the configuration farthest from all the error configurations is selected as the best configuration.

3. The method of claim 1, wherein: Suppose that the designed Block delay unit is n stages, the adjustment strategy of the Block delay unit is configured by using the Training_ctrl unit, and the adjustment strategy comprises: Set a threshold m, from the 0 level start to increase the adjustment, if the detection of consecutive m times configured delay are correct sampling, select the median of the consecutive m times correct sampling configuration as the final result.

4. The method of any one of claims 1 to 3, characterized in that: For BT. 656 / BT. 1120 protocol containing SAV / EAV key words, by judging whether the collected continuous data meets the SAV / EAV key words as the basis for correct or not.

5. The method of any one of claims 1 to 3, characterized in that: For BT. 601 or RGB interface, because the interface has control signal and meets the timing protocol, by configuring to detect one or more conditions as the effective basis for judgment, or configuring a single condition to continuously meet the condition as the effective basis for judgment.

6. An electronic device, comprising: Including: A memory storing computer executable instructions; A processor configured to run the computer executable instructions, Wherein the computer executable instructions are run by the processor to implement the steps of the data restoration detection method of the image input interface as claimed in any one of claims 1-5.

7. A storage medium, characterized by The storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the data restoration detection method of the image input interface as claimed in any one of claims 1-5.

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