Signal transmission method, apparatus and electronic device

Abstract

The present disclosure relates to a signal transmission method, a device and an electronic device. The signal transmission method is used for transmitting a display signal to a source driver based on a clock signal, and the method comprises: providing a reset signal to the source driver; after providing the reset signal to the source driver, providing a first start signal to the source driver, the first start signal comprising a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal; and after the end of the first start signal, providing a display signal to the source driver, the at least one additional trigger signal being determined by a controller based on a clock frequency of the clock signal. The method is advantageous in improving the frequency of signal transmission between the controller and the source driver.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a signal transmission method, apparatus and electronic device. BACKGROUND

[0002] In the field of display technology, a pixel array of a display panel such as a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines arranged in cross with the gate lines. A timing controller (T-con) of the display panel needs to provide gate signals and data signals to the multiple rows of gate lines and the multiple columns of data lines respectively through a gate driving circuit and a source driving circuit, so as to form a gray voltage required by each gray level of a display image in each row of pixel units in a row-by-row scanning manner, and then display a frame of image. SUMMARY

[0003] At least one embodiment of the present disclosure provides a signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal, the method comprising: providing a reset signal to the source driver; providing a first start signal to the source driver after providing the reset signal to the source driver, wherein the first start signal comprises a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal; and providing the display signal to the source driver after the first start signal ends, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

[0004] Another embodiment of the present disclosure provides another signal transmission method for a source driver to receive a display signal provided by a controller based on a clock signal, the method comprising: obtaining a reset signal provided by the controller; and in response to receiving a first start signal provided by the controller after obtaining the reset signal; receiving the display signal provided by the controller after the first start signal ends, the first start signal comprising a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of a clock signal adopted by the display signal.

[0005] The at least one embodiment of the present disclosure provides a signal transmission device for a controller to transmit a display signal to a source driver based on a clock signal, the device comprising: a signal providing unit configured to provide a reset signal to the source driver, provide a first start signal to the source driver after providing the reset signal to the source driver, the first start signal comprising a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, and provide the display signal to the source driver after the first start signal ends, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

[0006] The at least one embodiment of the present disclosure provides a signal transmission device for a source driver to receive a display signal provided by a controller based on a clock signal, the device comprising: a signal obtaining unit configured to obtain a reset signal provided by the controller, and in response to receiving a first start signal provided by the controller after obtaining the reset signal, receive the display signal provided by the controller after the first start signal ends, the first start signal comprising a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

[0007] The at least one embodiment of the present disclosure provides an electronic device comprising the signal transmission device provided by the at least one embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not a limitation on the present disclosure.

[0009] Figure 1A A circuit driving system architecture schematic diagram of a display panel is shown;

[0010] Figure 1A A system architecture diagram of a connection between a timing controller TCON and a source driver is shown;

[0011] Figure 1A A timing sequence diagram of signal transmission between a timing controller TCON and a source driver is shown;

[0012] Figure 2 A flowchart of a signal transmission method provided by the at least one embodiment of the present disclosure is shown;

[0013] Figure 3 A timing sequence diagram of signal transmission between a timing controller TCON and a source driver provided by the at least one embodiment of the present disclosure is shown.

[0014] Figure 4 Another signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0015] Figure 5A and 5B A signal format diagram of a display signal provided by a controller to a source driver is shown according to at least one embodiment of the present disclosure;

[0016] Figure 6A A timing diagram of a mode trigger signal (PSI) is shown according to at least one embodiment of the present disclosure;

[0017] Figure 6B A timing diagram of a single mode indication signal is shown according to at least one embodiment of the present disclosure;

[0018] Figure 7 A flow chart of another signal transmission method is shown according to at least one embodiment of the present disclosure;

[0019] Figure 8 A schematic block diagram of a signal transmission apparatus is shown according to at least one embodiment of the present disclosure;

[0020] Figure 9 A schematic block diagram of another signal transmission apparatus is shown according to at least one embodiment of the present disclosure; and

[0021] Figure 10 A schematic block diagram of an electronic device is shown according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort belong to the scope of protection of the present disclosure.

[0023] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms, used in the present disclosure do not necessarily denote any ordinal, quantity or importance, but are used to distinguish a different constituent part. Also, the terms "one", "a" or "the" and similar terms used in the present disclosure do not denote a quantity of singular, but denote the presence of at least one. The terms "include", "comprise" and similar terms used in the present disclosure mean that the elements or objects before the terms encompass the elements or objects listed after the terms and equivalents thereof, and do not exclude other elements or objects. The terms "connected" or "coupled" and similar terms used in the present disclosure do not necessarily denote a physical or mechanical connection or coupling, but can include an electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0024] Various driving circuits for display panels generally include scan driving integrated circuits (also referred to as gate drivers or G-ICs), data driving integrated circuits (also referred to as source drivers or SD-ICs), controllers, and the like. The controller is mainly used to convert image data signals, control signals, clock signals, and the like received from the outside (such as signal sources of storage devices, network modems, and the like) into image data signals, gate signals, control signals, clock signals, and the like suitable for source drivers and gate drivers, for implementing image display driving of display panels. For example, the controller can be a timing controller (TCON). The source driver is mainly used to receive digital signals (display signals or image signals) and control signals, and the like provided by the aforementioned controller, and convert the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and input into each column of pixel units of the pixel array of the display panel. The gate driver is mainly used to implement opening of each row of pixel units of the pixel array, for example, row by row (or interlaced), and under the action of control signals, cooperate with the source driver to input the required image data signals into the corresponding pixel units for the opened row of pixel units, so that the pixel units can display according to the image data signals.

[0025] In the display process of the display panel, a video and an animation are composed of a large number of pictures displayed in time sequence (for example, a frame rate of 60 Hz or 120 Hz, etc.), each picture is a frame, that is, a frame of image refers to a complete picture displayed by the display panel. In the display process of a frame of image, the gate driver sequentially turns on each row of pixel units in the pixel array from the first row to the last row for scanning, and in the scanning process, the source driver inputs the required image data signal of each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required for a frame of picture. For example, due to the process of the pixel units of the display panel and other reasons, in order to obtain a clear and complete display effect with good quality, the display picture needs to be continuously refreshed, and each refresh needs to display a frame of image, and a plurality of frames of continuously displayed images form a static picture or a dynamic picture in visual effect. After the gate driver completes the scanning of a frame of image, it needs to return to the first row to start the scanning of a new frame. The time period from the end of the scanning of the last row by the gate driver to the return to the first row is the vertical blanking period. The display panel does not display an image in the vertical blanking period, which is for preparing for the display of the next frame of image.

[0026] Figure 1A A schematic diagram of a circuit driving system architecture of a display panel is shown. As shown, the circuit driving system architecture includes a timing controller TCON, a gate driver G-IC, a source driver SD-IC, and a display panel. The circuit driving system architecture further includes a power management integrated circuit PMIC, a gamma (Gamma) circuit, a common electrode voltage (Vcom) circuit, etc. Figure 1A

[0027] The input voltage Vin of the power management integrated circuit is, for example, 5V or 12V, and the output voltage includes a digital operating voltage DVDD provided to each IC, an analog voltage AVDD provided to the Gamma circuit and the Vcom circuit, a gate turn-on voltage VGH and a gate turn-off voltage VGL provided to the gate driver G-IC, etc. The common electrode voltage (Vcom) circuit is used to provide a common voltage for the pixel array.

[0028] ​The control signals outputted by the timing controller TCON include control signals provided to the gate driver G-IC and control signals provided to the source driver SD-IC. For example, the control signals provided to the source driver SD-IC include a row start signal (Start Horizontal, STH) representing the start of row data transmission, a row clock pulse signal (Clock Pulse Horizontal, CPH), a data transmission control signal Load, and a data polarity inversion signal POL. For example, the control signals provided to the gate driver G-IC include a frame start signal (Start Vertical, STV) representing the start of a frame picture scan, a scan clock pulse signal (Clock Pulse Vertical, CPV), an enable signal (Enable), and the like.

[0029] For example, the input digital interface type of the timing controller TCON can be, for example, Low-Voltage Differential Signaling (LVDS), Embedded Display Port (eDP) interface, and V-by-One (Vx1) interface, and the like. The output digital interface type of the timing controller TCON can be, for example, mini-LVDS, used for communication with the source driver SD-IC.

[0030] The LVDS interface transmits signals in the form of wire pairs, including a clock wire pair and several signal wire pairs. For example, the LVDS signal wire pairs include three control signals: a field synchronization signal, a row synchronization signal, and an enable signal. The mini-LVDS interface is similar to the LVDS interface, and also transmits signals by differential signal wire pairs. Unlike the LVDS signal wire pairs, the mini-LVDS signal wire pairs of the mini-LVDS interface do not transmit control signals, and these control signals are transmitted by signal wires or signal differential pairs independent of the mini-LVDS signal wire pairs.

[0031] In the present disclosure, the source driver and the controller are taken as an example to illustrate embodiments by the mini-LVDS interface.

[0032] Figure 1A A system architecture diagram showing the connection between the timing controller TCON and the source driver is shown.

[0033] As Figure 1AAs shown, the system architecture includes a timing controller (TCON) and multiple source drivers. These source drivers include, for example, source driver SD#1, source driver SD#2, etc. The number of source drivers is related to the physical resolution of the display panel; for a single display panel, this may require dozens or even hundreds. For example, each source driver is connected via clock signal pairs for transmitting clock signals, mini-LVDS signal pairs for transmitting image data signals, and control signal lines for transmitting multiple control signals. The mini-LVDS signal pairs can be 3 or 6 pairs. The control signal lines can be differential pairs or not. The mini-LVDS signal lines and the multiple control signal lines are independent of each other.

[0034] For example, the timing controller TCON and each source driver (e.g., source driver SD#1, source driver SD#2, etc.) are connected not only through mini-LVDS signal pairs, but also through the LOAD control signal line for transmitting data transmission control signal LOAD, the POL control signal line for transmitting control signal POL, the POL2 control signal line for transmitting control signal POL2, etc.

[0035] Other control signal lines may also be included between each source driver and TCON, such as horizontal dot inversion (H2DOT) control signal lines, bias voltage (PWRC) control signal lines, POLC control signal lines, etc.

[0036] Figure 1A A timing diagram of signal transmission between the timing controller TCON and the source driver is shown.

[0037] like Figure 1A As shown, this timing sequence includes a clock signal CLK and a data signal LV0. The clock signal CLK is, for example,... Figure 1A The clock signal line transmits signals on CLK. Figure 1A The mini-LVDS signal line pair includes, for example, three pairs of signal lines. The data signal LV0 can be the signal transmitted on the low-voltage differential signal line pair LV0 of the three pairs of signal lines. The low-voltage differential signal line pair LV0 can be any one of the three pairs of signal lines mentioned above.

[0038] In this embodiment, the signal lines and the signals transmitted on the signal lines are represented using the same notation. For example, the clock signal and the clock signal line pair are both represented by CLK.

[0039] like Figure 1A As shown, before a frame of image is displayed, the controller first provides a reset signal re to each source driver, causing the source drivers to reset.

[0040] exist Figure 1AIn the example, the reset signal is, for example, the digital signal "1". In embodiments of this disclosure, for example, a high-level signal represents the digital signal "1" and a low-level signal represents the digital signal "0".

[0041] For example, the controller provides a reset signal *re* to the source driver during multiple consecutive clock cycles of the clock signal. After providing the reset signal *re*, the controller provides a start signal *st* to the source driver based on the valid reset edge *P* of the clock signal. The valid reset edge *P* is the first valid edge after the last valid edge *Q* of the clock signal in the aforementioned multiple consecutive clock cycles. The start signal *st* is, for example, a digital signal "0" to indicate that the source driver is ready to receive subsequent display signals. The display signals are used to display a frame of image and may include, for example, control signals and image data signals.

[0042] For example, the source driver responds to acquiring a high-level signal on multiple valid edges of the clock signal and a low-level signal on the valid reset edge, and begins to perform operations such as reset and configuration.

[0043] The timing relationships between the reset signal re and the start signal st and the clock signal CLK satisfy the setup time and hold time, respectively.

[0044] like Figure 1A As shown, after the controller provides the start signal st to the source driver, the controller begins to provide the display signal to the source driver, and ensures that the clock signal CLK and the data signal LV0 satisfy the setup and hold times. For example, the source driver acquires the signal transmitted on the low-voltage differential signal line LV0 at the effective edge M of the clock signal and subsequent effective edges to obtain the display signal. The effective edge M of the display signal is the first effective edge of the clock signal after the effective reset edge P.

[0045] In this example, the source driver performs reset and configuration operations during the time period tStart between the reset valid edge P and the display signal valid edge M in preparation for receiving the display signal later.

[0046] If the clock signal frequency is too high, the source driver may have difficulty fully performing reset and configuration operations within the time period tStart between the valid reset edge P and the valid display signal edge M, making it difficult to adequately prepare for subsequent display signal reception and affecting the transmission of subsequent display signals. If the clock signal frequency is too low, the signal transmission efficiency between the source driver and the controller will be low, resulting in poor image display quality on the display panel.

[0047] In the above embodiments, the active edge of the clock signal is, for example, a rising edge of the clock signal. For example, the reset active edge P and the display signal active edge M are both rising edges of the clock signal. In other embodiments of the present disclosure, the active edge of the clock signal is, for example, a falling edge of the clock signal. In the following description, only the case where the active edge of the clock signal is a rising edge of the clock signal is taken as an example to illustrate the embodiments provided by the present disclosure.

[0048] It should be noted that the reset signal can also be other types of signals, and the start signal is a signal different from the reset signal. The present disclosure does not limit the reset signal to be a high-level signal and the start signal to be a low-level signal. For example, the reset signal is a low-level signal and the start signal is a high-level signal. In the following description, only the case where the reset signal is a high-level signal and the start signal is a low-level signal is taken as an example to illustrate the embodiments provided by the present disclosure.

[0049] To this end, embodiments of the present disclosure provide a signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal. The method comprises: providing a reset signal to the source driver; after providing the reset signal to the source driver, providing a first start signal to the source driver, the first start signal comprising a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal; and after the end of the first start signal, providing a display signal to the source driver, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal. This method is advantageous to improve the frequency of signal transmission between the controller and the source driver, and the source driver has sufficient time to perform reset and configuration operations to fully prepare for the transmission of the display signal.

[0050] Figure 2 A flowchart of a signal transmission method provided by at least one embodiment of the present disclosure is shown. For example, the signal transmission method provided by embodiments of the present disclosure is applicable to both LVDS interface and mini-LVDS interface.

[0051] As Figure 2 shown, the signal transmission method comprises steps S10-S30. This embodiment is used for a controller to transmit a display signal to a source driver based on a clock signal. Figure 2 The signal transmission method described above is, for example, executed by a timing controller TCON in Figure 1A . For example, the signal transmission method is used for the timing controller TCON to transmit a display signal to a source driver SD#1, a source driver SD#2, etc. based on a clock signal.

[0052] Step S10: providing a reset signal to the source driver.

[0053] Step S20: After providing the reset signal to the source driver, a first start signal is provided to the source driver, the first start signal including a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal.

[0054] Step S30: After the first start signal ends, a display signal is provided to the source driver.

[0055] In embodiments of the present disclosure, the at least one additional trigger signal is determined by the controller based on a clock frequency of the clock signal.

[0056] In this embodiment, the time length of the start signal (i.e., the first start signal) is increased by the at least one additional trigger signal, so that the source driver can sufficiently perform the reset and configuration and the like even if the frequency of the clock signal is increased, thereby being able to increase the frequency of signal transmission between the controller and the source driver.

[0057] In some embodiments of the present disclosure, the display signal provided by the controller to the source driver may, for example, only include an image data signal, i.e., the mini-LVDS signal line pair only transmits the image data signal.

[0058] In the example in which the display signal only includes the image data signal, the control signal is transmitted through Figure 1A the various control signal lines described above. As Figure 1A shown, the mini-LVDS signal line pair is only used to transmit the image data signal, and is not used to transmit control signals such as polarity inversion configuration information, data transmission control information, and the like. Therefore, there are multiple signal lines and multiple signal line interfaces between the timing controller and the source driver, which results in occupying a large signal routing space in the display panel, and this problem is more significant when the number of source drivers is large. If the available signal routing space in the display panel is not enough to accommodate the multiple data lines, some commonly used control functions cannot be flexibly embedded into the source driver.

[0059] In other embodiments of the present disclosure, the display signal includes both the image data signal and the configuration data signal. That is, the mini-LVDS signal line pair transmits both the image data signal and the configuration data signal.

[0060] In this example, the connection between the timing controller TCON and the source driver can only be through the mini-LVDS signal line pair, the clock signal line pair, the LOAD control signal line and the POL control signal line. In this embodiment, the mini-LVDS transmits, in addition to the image data signal, configuration data signals for controlling the source driver, such as the above-mentioned control signal POL2, the horizontal dot inversion control signal, the bias voltage control signal, etc. This can multiplex the low-voltage differential signal interface, so that it is used not only to provide image data to the source driver but also to provide configuration data, thereby reducing the number of interfaces for signal transmission, saving costs, and ensuring that various control functions can be flexibly embedded into the source driver. The image data signal is a signal for image display, such as including RGB (red, green, blue) data. The configuration data is used to configure the source driver.

[0061] For example, in addition to the transmission of the data transmission control signal LOAD through the LOAD control signal line and the transmission of the control signal POL through the POL control signal line, other control signals are also transmitted through the mini-LVDS signal line pair. That is, the configuration data signal includes other control signals in addition to the data transmission control signal LOAD and the control signal POL, such as the horizontal dot inversion control signal, the bias voltage control signal, the POLC control signal, etc.

[0062] The described signal transmission method will be described below in conjunction with Figure 3 . Figure 2 .

[0063] Figure 3 A timing diagram of signal transmission between the timing controller TCON and the source driver provided by at least one embodiment of the present disclosure is shown.

[0064] As Figure 3 shown, the timing includes the clock signal CLK' and the data signal LV0'. The clock signal CLK' is, for example, the signal transmitted on the clock signal line pair CLK in Figure 1A . Figure 1A The mini-LVDS signal line pair in , for example, includes 3 pairs of signal lines, and the data signal LV0' can be the signal transmitted on the low-voltage differential signal line pair LV0 in the 3 pairs of signal lines, which is any one of the above-mentioned 3 pairs of signal lines.

[0065] Figure 1A The frequency of the clock signal CLK' is, for example, greater than the frequency of the clock signal CLK in

[0066] . Figure 3 As shown, for example, for step S10, before one frame of image display, the controller first provides a reset signal re' to each source driver, so that the source driver is reset.

[0067] In Figure 3 the example, the reset signal re' is the same as the reset signal re in Figure 1A , for example, a digital signal "1". Alternatively, the reset signal re' can also be different from the reset signal re in Figure 1A .

[0068] For example, the controller provides the reset signal re' to the source driver in a plurality of consecutive clock periods of the clock signal. For step S20, the controller provides the start signal st' to the source driver, for example, after providing the reset signal re'. The start signal st' is an example of a first start signal. The start signal st' comprises a base trigger signal BT and at least one additional trigger signal AT consecutive to the base trigger signal.

[0069] In some embodiments of the present disclosure, the base trigger signal BT and each additional trigger signal AT are, for example, a digital signal "0".

[0070] The base trigger signal BT and each additional trigger signal AT are determined by the controller based on a clock frequency of the clock signal.

[0071] For example, the setup time and the hold time of the clock signal CLK' and the data signal LV0' in each clock period determine the base trigger signal BT and each additional trigger signal AT, so that the source controller can accurately and stably capture the base trigger signal BT and each additional trigger signal AT at the active edge of the clock signal.

[0072] In some embodiments of the present disclosure, at least two consecutive rising edges of the clock signal CLK' correspond to the base trigger signal and the at least one additional trigger signal, respectively.

[0073] The source driver captures the base trigger signal BT provided by the controller at the first active edge P1 (i.e., the reset active edge) after the last active edge Q' of the clock signal in the plurality of consecutive clock periods (the clock periods in which the reset signal is provided), and captures the at least one additional trigger signal provided by the controller at the at least one active edge (e.g., the active edge P2) consecutive to the first active edge P1. Each additional trigger signal is captured at the active edge of the clock signal after the first active edge P1, respectively.

[0074] As Figure 3As shown, after the controller provides the start signal st' to the source driver, the controller starts to provide the display signal to the source driver, so that the clock signal CLK' and the data signal LV0' meet the setup time and the hold time. For example, the source driver acquires the signal transmitted on the low-voltage differential signal line pair LV0 at the display signal active edge M' of the clock signal and the subsequent active edge, where the display signal active edge M' is the first active edge after the last active edge of the clock signal corresponding to the start signal, i.e., the first active edge after the last additional trigger signal active edge. In Figure 3 For example, the last additional trigger signal active edge is active edge P2.

[0075] In this embodiment, the source driver performs the reset and configuration and the like within the time period tStart' between the first active edge P1 after the clock signal active edge Q' and the display signal active edge M' to prepare for the subsequent reception of the display signal.

[0076] In Figure 3 For example, only one additional trigger signal is shown, but in actual applications, the number of additional trigger signals can be set according to actual needs.

[0077] In some embodiments of the present disclosure, the number of at least one additional trigger signal can be determined according to the frequency of the clock signal and the length of time required for the source driver to perform the reset and configuration.

[0078] For example, the longer the length of time required for the source driver to perform the reset and configuration, the more the number of additional trigger signals.

[0079] In Figure 3 For example, since the frequency of the clock signal CLK' is greater than the frequency of the clock signal CLK, if the start signal and the display signal are still provided to the source driver in the timing shown in Figure 1A , the time for the source driver to perform the reset and configuration and the like is not enough. In the embodiment shown in Figure 3 , the length of time between the reset active edge and the display signal active edge is extended by the additional trigger signal, and the additional trigger signal and the basic trigger signal can be the same, so that the controller and the source driver do not need to perform additional operations, which is simple and easy to implement.

[0080] In some embodiments of the present disclosure, the signal transmission method further includes obtaining a reset format, the reset format including a first format and a second format. Step S20 includes, in response to the reset format being the first format, providing a first start signal to the source driver after providing the reset signal to the source driver.

[0081] For example, the reset format can be set by those skilled in the art according to actual needs. The first format corresponds to providing the first start signal to the source driver, and the second format corresponds to providing the second start signal to the source driver, the second start signal being different from the first start signal.

[0082] For example, if the reset format is the first format, the first start signal is provided to the source driver after the reset signal is provided to the source driver; if the reset format is the second format, the second start signal is provided to the source driver after the reset signal is provided to the source driver.

[0083] For example, the first start signal is the start signal st' shown in Figure 3 , and the second start signal is the start signal st shown in Figure 1A . That is, the first start signal includes the basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, and the second start signal only includes the basic trigger signal.

[0084] It should be noted that although Figure 1A and Figure 3 both take the display signal as an example of the digital signal "0", this does not limit the present disclosure, and the display signal can be any signal.

[0085] Figure 4 Another signal transmission method provided by at least one embodiment of the present disclosure is shown.

[0086] As shown in Figure 4 , the signal transmission method includes steps S401-S405.

[0087] Step S401: Obtain a reset format. The reset format includes a first format and a second format.

[0088] Step S402: In response to the reset format being the first format, provide the first start signal to the source driver after providing the reset signal to the source driver.

[0089] Step S403: Provide the display signal to the source driver after the first start signal ends.

[0090] Step S404: In response to the reset format being the second format, provide the second start signal to the source driver after providing the reset signal to the source driver, the second start signal only including the basic trigger signal.

[0091] Step S405: Provide the display signal to the source driver after the second start signal ends.

[0092] The method can provide the source driver with a first start signal or a second start signal based on a preset reset format (a first format or a second format) according to different clock frequencies, and the first start signal or the second start signal corresponds to different clock frequencies respectively, thereby being applicable to signal transmission at different clock frequencies.

[0093] For step S401, in some embodiments of the present disclosure, for example, a clock frequency is acquired, and a reset format is acquired according to the clock frequency.

[0094] For example, in response to the clock frequency being greater than a preset frequency, it is determined that the reset format is the first format, or in response to the clock frequency being less than or equal to the preset frequency, it is determined that the reset format is the second format.

[0095] For example, the preset frequency is 330 Mhz, if the clock frequency is greater than 330 Mhz, the reset format is the first format, and if the clock frequency is less than or equal to 330 Mhz, the reset format is the second format.

[0096] The preset frequency can be set by a person skilled in the art according to actual needs, and the present disclosure does not limit the preset frequency. For example, the preset frequency can also be 48 Mhz, etc.

[0097] In some other embodiments of the present disclosure, the reset format can be preset or renewed by a person skilled in the art.

[0098] For the reset format, refer to the description above.

[0099] For steps S402 and S403, for example, if the reset format is the first format, after providing the source driver with the reset signal, the source driver is provided with Figure 3 a start signal st' as shown. After the end of the start signal st', the source driver is provided with a display signal. The timing relationship between the timing signal and the data signal in the embodiment of steps S402 and S403 is, for example, as shown in the example. Figure 3

[0100] As Figure 4 shown, the signal transmission method further includes steps S404 and S405 in addition to steps S401-S403.

[0101] For step S404, for example, the second start signal can be Figure 1A a start signal st as shown. The start signal st only includes a basic trigger signal. That is, there is only one reset active edge P between the display signal active edge M and the last clock signal active edge Q in a plurality of consecutive clock periods.

[0102] For step S405, as Figure 1A ​As shown, the display signal is provided to the source driver after the end of the start signal st.

[0103] The timing relationship between the timing signal and the data signal in steps S404 and S405 in the embodiment is, for example, Figure 1A As shown in the example.

[0104] In the above embodiment, a suitable reset format can be selected according to different clock frequencies, so that the signal transmission method can use different reset formats for different clock frequencies, has stronger applicability, and is beneficial to improving the frequency of signal transmission between the controller and the source driver.

[0105] In some embodiments of the present disclosure, the controller provides the reset signal, the first start signal and the display signal to the source driver in sequence through a low-voltage differential signal interface.

[0106] In at least one embodiment of the present disclosure, the low-voltage differential signal interface includes a plurality of pairs of transmission lines, each pair of transmission lines including two complementary differential signals, and the image data and the configuration data are transmitted through the two complementary differential signals. For example, the low-voltage differential signal interface can be a mini-LVDS interface or an LVDS interface, etc.

[0107] As described above, in some embodiments, the display signal only includes the image data signal, and the control signal for display is transmitted through the control signal line.

[0108] In some other embodiments of the present disclosure, the display signal further includes the configuration data signal in addition to the image data signal.

[0109] For example, the controller provides the display signal to the source driver in at least two modes, and the display signal includes the image data signal and the configuration data signal.

[0110] For example, the configuration data signal can be generated by a timing control module in the timing controller. The configuration data signal is used to configure the source driver, so that the source driver processes the image data signal according to the configuration data signal. For example, the source driver outputs the image data signal to the pixel array according to the timing provided by the configuration data signal.

[0111] In some embodiments of the present disclosure, the configuration data signal comprises control signals required in the process of displaying RGB data by the pixel array. For example, the display panel is a liquid crystal display panel, and the polarity of liquid crystal molecules needs to be controlled in the process of displaying RGB data by the liquid crystal display panel, and the control signals can comprise data polarity inversion control signals (for example, POL control signals, POL2 control signals and POLC control signals). For another example, the start signal of row data is required in the process of displaying RGB data by the pixel array, and the control signals can comprise the start signal STH of row data. For another example, in embodiments of the present disclosure, the display panel can also be an OLED display panel, and the like, and embodiments of the present disclosure do not limit this.

[0112] For example, the configuration data signal can be set by those skilled in the art according to actual needs, and the present disclosure does not limit the configuration data. The above-mentioned data polarity inversion control signal, frame scanning start signal and start signal of row data are only examples.

[0113] For example, one frame display period comprises an image display period (Active Frame) and a vertical blanking period (Vertical Blanking Period, VBP). In the image display period, for example, the pixels in the pixel array display image data row by row, and in the vertical blanking period, the display of the next frame image data is prepared.

[0114] For example, the display signal comprises a plurality of display sub-signals, and at least two modes each provide at least one display sub-signal. The at least two modes comprise a frame configuration mode, and the display sub-signal provided in the frame configuration mode comprises frame configuration data for displaying one frame of image, and the frame configuration data comprises a power consumption flag signal.

[0115] In some embodiments of the present disclosure, in addition to the frame configuration mode, the at least two modes further comprise a row configuration mode, and the configuration data comprises row configuration data, and the display sub-signal provided in the row configuration mode comprises the row configuration data and row image data.

[0116] The display sub-signal provided in the row configuration mode is used for image data display of one row of pixels. The row image data is, for example, the RGB data corresponding to the row in the pixel array. The row configuration data is used for configuring the source driver, so that the source driver outputs the row image data and timing control signals and the like to the row of pixels in response to the row configuration data.

[0117] In some embodiments of the present disclosure, the at least two modes further comprise a correction configuration mode, and the display sub-signal provided in the correction configuration mode comprises a correction for the timing relationship between the clock signal and the data signal.

[0118] Figure 5A and 5BA signal format diagram of a display signal provided by a controller to a source driver according to an embodiment of the present disclosure is shown.

[0119] As shown in Figure 5A , in a frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 501 provided in a line configuration mode, a display sub-signal 502 provided in a frame configuration mode, and a display sub-signal 503 provided in a correction configuration mode.

[0120] For example, the plurality of display sub-signals 501 are provided in the line configuration mode during the image display period, the display sub-signal 502 is provided in the frame configuration mode during the vertical blanking period, and the display sub-signal 503 is provided in the correction configuration mode.

[0121] As shown in Figure 5A , the display signal is provided to the source driver in at least two modes via the LVDS interface in a frame display period includes that the display signal is provided to the source driver in at least two modes via the LVDS interface in a frame display period in sequence, and for each mode, one or more display sub-signals are provided to the source driver in sequence via the LVDS interface.

[0122] For example, in the example of Figure 5A , the plurality of display sub-signals 501 are provided to the source driver in the line configuration mode via the LVDS interface first, then the display sub-signal 502 is provided to the source driver in the frame configuration mode, and then the display sub-signal 503 is provided to the source driver in the correction configuration mode. For example, for the line configuration mode including the plurality of display sub-signals 501, the plurality of display sub-signals 501 are provided to the source driver in sequence via the LVDS interface. That is, in the example of Figure 5A , the plurality of display sub-signals 501 are provided to the source driver via the LVDS interface first, then the display sub-signal 502 is provided to the source driver via the LVDS interface, and then the display sub-signal 503 is provided to the source driver via the LVDS interface.

[0123] As shown in Figure 5A , each display sub-signal 501 provided in the line configuration mode includes line data LPC and image data (e.g., RGB data). As shown in Figure 5B , the line data LPC includes a mode identification signal A and line configuration data. For example, the mode identification signal A includes a reset signal RE and a line mode start signal LPC Start. For example, the line mode start signal can be a logic invalid level, e.g., "000 000", so that the display signal shown in Figure 1A and Figure 3 is the line mode start signal.

[0124] In some embodiments of this disclosure, the row configuration data may be, for example, a row data packet including 16 bits, such as the row data packet including the 0th bit data LPC[0], the 1st bit data LPC[1], and the 15th bit data LPC

[15] .

[0125] Table 1 below illustrates the definition of an exemplary row data packet provided in at least one embodiment of this disclosure.

[0126] Table 1

[0127]

[0128] As shown in Table 1, in one type of row configuration data provided in this disclosure, the row configuration data includes a frame start indication signal. For example, the 0th bit LPC[0] of the row data packet is the frame start indication signal. In the row configuration data of the first display row of each frame, LPC[0] is, for example, high.

[0129] As shown in Table 1, in a row configuration data provided in this disclosure, the row configuration data includes a data polarity inversion control signal. For example, the first bit of the row data packet LPC[1] is the data polarity inversion control signal POL; the second bit of the row data packet LPC[2] is the data polarity inversion control signal POLC; and the third bit of the row data packet LPC[3] is the data polarity inversion control signal POL2.

[0130] As shown in Table 1, in a row configuration data provided in this disclosure, the row configuration data includes charge sharing function control signals. For example, bits 4 to 7 of the row data packet, i.e., LPC[4:7], are charge sharing control bits used to control charge sharing.

[0131] As shown in Table 1, the row configuration data provided in this disclosure also includes reserved bits, which are used to flexibly add some row configurations and improve configuration flexibility. For example, bits 8 to 15, namely LPC[8:15], are reserved bits.

[0132] It should be noted that Table 1 is merely an example of a row data packet definition and is not intended to limit the embodiments of this disclosure. Those skilled in the art can design other row data packet definitions. For example, row data packets can also be 8-bit, 32-bit, 64-bit, etc.

[0133] like Figure 5AAs shown, each display sub-signal 502 provided in the frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The invalid data IDLE0 and the invalid data IDLE1 can be the same signal, for example, a low level signal, and the distinction is made here because the data length of IDLE0 and IDLE1 is different. In embodiments of the present disclosure, the invalid data can be a low level signal, or can be other forms of signals.

[0134] During the low power consumption working state of the source driver, the controller provides a logic invalid level to the source driver to reduce the power consumption during the vertical blanking. As shown in FIG. 4, the controller provides a logic invalid level to the source driver during the vertical blanking. Figure 5B As shown, the frame data FPC includes a mode identification signal B and frame configuration data. For example, the mode identification signal B of the frame data FPC is a reset signal RE and a frame mode start signal FPC Start. For example, the frame mode start signal is different from the line mode start signal to distinguish the frame configuration mode and the line configuration mode, and the frame mode start signal can be a logic valid level, for example, “111 111”.

[0135] Table II below shows a definition of an exemplary frame data packet provided by at least one embodiment of the present disclosure.

[0136] Table II

[0137]

[0138] As shown in Table II, the frame data packet includes 28 bits. The 0thbit data FPC[0] of the frame configuration data is a vertical blanking state bit. For example, if the 0thbit data FPC[0] of the frame configuration data is 1 (i.e., a high level), the source driver enables the low power consumption working state.

[0139] FPC[1:25] of the frame configuration data are bits defined by those skilled in the art, and those skilled in the art can define FPC[1:25] according to the setting requirements. FPC[26:27] of the frame configuration data is low power consumption configuration information, which defines the circuit modules that are turned off during the vertical blanking. For example, if FPC[26:27]=00, the receiver is powered off, i.e., the power supply of the receiver in the source driver is turned off. If FPC[26:27]=01, the receiver and the outputter are powered off, i.e., the power supplies of the receiver and the outputter in the source driver are turned off at the same time.

[0140] In some embodiments of the present disclosure, during the transmission operation performed in the frame configuration mode, a mode trigger signal is provided to the source driver, so that the source driver starts to enter the low power consumption working state in response to the mode trigger signal.

[0141] In some embodiments of this disclosure, the display sub-signal provided in frame configuration mode includes the data signal 512 provided in power control sub-mode.

[0142] The data signals provided in the power control sub-mode may include, for example, invalid data IDLE0 and invalid data IDLE1.

[0143] like Figure 5A As shown, before providing invalid data IDLE0 to the source driver in power configuration sub-mode, the controller provides the mode trigger signal PSI to the source driver again to indicate that the source driver enters a low-power operating state.

[0144] During the period when the controller provides invalid data IDLE0 and invalid data IDLE1 to the source driver in power configuration sub-mode, at least some circuit modules in the source driver are in a power-down state to save power.

[0145] like Figure 5A As shown, each display sub-signal 503 provided in the calibration configuration mode includes calibration data ASC. (As...) Figure 5B As shown, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C can, for example, be a logic invalid level. The correction signal is used, for example, to correct the timing of the data signals transmitted between the clock signal and the low-voltage differential signal line pair. The pattern recognition signal C does not include a reset signal; therefore, the timing of the display sub-signals provided in the correction configuration mode can differ from... Figure 3 The temporal relationship is shown.

[0146] like Figure 5A As shown, after transmitting the display signal for one display cycle to the source driver, the display signal for the next display cycle continues to be transmitted to the source driver.

[0147] like Figure 5A As shown, before providing each display sub-signal to the source driver, a mode trigger signal PSI is provided to the source driver. The mode trigger signal PSI is used to notify the source driver whether to perform a transmission operation for at least two modes or a single-mode transmission operation. A single-mode transmission operation is, for example, the embodiment described above that uses a low-voltage differential signal interface such as mini-LVDS to transmit display signals that include only image data signals, while control signals are transmitted through control signal lines.

[0148] In this embodiment, the source driver is notified of the transmission operation of at least two modes by the mode trigger signal PSI, which facilitates the compatibility of the source driver and the controller with other transmission operations other than the transmission operation of at least two modes, and provides compatibility. For example, the controller and the source driver can compatibly perform a single-mode transmission operation in addition to the transmission operation of at least two modes. For example, the display signal that can be transmitted in at least two modes conforms to a first signal transmission protocol, and the display signal that can be transmitted to the source driver in a single mode conforms to a second signal transmission protocol. If the controller and the source driver perform the transmission operation of at least two modes, the controller provides the mode trigger signal PSI to the source driver as an indication signal of the transmission operation of at least two modes; if the controller and the source driver perform the transmission operation of a single mode, the controller provides a single-mode indication signal different from the mode trigger signal PSI to the source driver. The second signal transmission protocol can be some protocol different from the first signal transmission protocol, such as some transmission protocol in the related art. By setting the mode trigger signal, signal line multiplexing can be achieved, the chip has multiple functions, and thus the difficulty of popularizing the first signal transmission protocol is also reduced.

[0149] In some embodiments of the present disclosure, providing the mode trigger signal to the source driver includes providing a data transmission control signal and a data polarity inversion control signal to the source driver, and obtaining the mode trigger signal based on the relative timing relationship between the data transmission control signal and the data polarity inversion control signal. The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity inversion control signal after the first transition edge at least partially coincides with the second transition state of the data transmission control signal after the second transition edge.

[0150] For example, the data polarity inversion control signal controls the polarity inversion of the output data signal of the source driver by switching between high and low levels to achieve alternating current driving of liquid crystals. The data transmission control signal is used to latch the data and the data polarity inversion signal input to the source driver at the rising edge, and to control the release of data to the panel at the falling edge.

[0151] In this example, the controller and the source driver can be connected through the mini-LVDS signal line, the POL signal line, and the LOAD signal line, so other signal lines such as the POL2 control signal line and the POLC control signal line, the horizontal dot inversion (H2DOT) control signal line, the bias voltage (PWRC) control signal line, etc. can be all or partially omitted. Therefore, this example not only reduces the number of signal lines between the controller and the source driver, but also informs the source driver of which transmission operation to perform to be compatible with the single-mode transmission operation.

[0152] Figure 6AA timing diagram of a mode trigger signal PSI is shown.

[0153] As shown in Figure 6A , the mode trigger signal PSI includes a data transfer control signal LOAD and a data polarity inversion control signal POL, and a first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than a second transition edge (e.g., rising edge) of the data transfer control signal LOAD, and a first transition state (e.g., high state) of the data polarity inversion control signal POL after the first transition edge at least partially overlaps with a second transition state (e.g., high state) of the data transfer control signal LOAD after the second transition edge.

[0154] In some embodiments of the present disclosure, for example, a driver in a controller can be adjusted such that the data polarity inversion control signal POL is later than the data transfer control signal LOAD by a time length tS2 within a same cycle of the data transfer control signal LOAD and the data polarity inversion control signal POL, so that a rising edge of the data polarity inversion control signal POL is later than a rising edge of the data transfer control signal LOAD. The data polarity inversion control signal POL and the data transfer control signal LOAD are in a high state simultaneously within a time length tH2 after the rising edges.

[0155] Figure 6B A timing diagram of a single mode indication signal is shown.

[0156] As shown in Figure 6B , the single mode indication signal includes a data transfer control signal LOAD' and a data polarity inversion control signal POL', and a first transition edge (e.g., rising edge) of the data polarity inversion control signal POL' is earlier than a second transition edge (e.g., rising edge) of the data transfer control signal LOAD', and a first transition state (e.g., high state) of the data polarity inversion control signal POL' after the first transition edge at least partially overlaps with a second transition state (e.g., high state) of the data transfer control signal LOAD' after the second transition edge.

[0157] In some embodiments of the present disclosure, for example, a driver in a controller can be adjusted such that the data polarity inversion control signal POL' is earlier than the data transfer control signal LOAD' by a time length tS1 within a same cycle of the data transfer control signal LOAD' and the data polarity inversion control signal POL', so that a rising edge of the data polarity inversion control signal POL' is earlier than a rising edge of the data transfer control signal LOAD'.

[0158] Figure 6A and Figure 6BThe embodiments of the present application can distinguish between the single mode transmission operation and the transmission operation of at least two modes by means of the data transmission control signal and the data polarity inversion control signal, without the need to improve the hardware circuit of the interface, and are easy to implement. In this way, the same set of controllers and source drivers can be used to select the first signal transmission protocol or the second signal transmission protocol as needed, without the need to provide a set of controllers and source drivers for the first signal transmission protocol and the second signal transmission protocol respectively, thereby reducing the cost of design, research and development, manufacturing and management for the supplier.

[0159] Figure 7 A flowchart of another signal transmission method provided by at least one embodiment of the present application is shown.

[0160] As shown in Figure 7 , the signal transmission method comprises steps S710-S730. Figure 7 The signal transmission method shown in is performed by the source driver, for example. The signal transmission method is used for the source driver to receive the display signal provided by the controller based on the clock signal, for example.

[0161] Step S710: Obtain the reset signal provided by the controller.

[0162] Step S720: After obtaining the reset signal, receive the first start signal provided by the controller. The first start signal comprises a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, and the at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal adopted by the display signal.

[0163] Step S730: After the end of the first start signal, receive the display signal provided by the controller.

[0164] The signal transmission method is advantageous in improving the frequency of signal transmission between the controller and the source driver.

[0165] For step S710, in the example of Figure 1A , the timing controller TCON sends the display signal in a frame display period to the source driver SD#1, the source driver SD#2, etc. through its own low-voltage differential signal interface. The source driver SD#1, the source driver SD#2, etc. receive the display signal from the timing controller TCON through its own low-voltage differential signal interface.

[0166] Before the timing controller TCON and the source driver SD#1, the source driver SD#2, etc. perform the transmission of the display signal, the timing controller TCON provides the reset signal to the source driver SD#1, the source driver SD#2, etc. Each source driver receives the reset signal provided by the controller. For the reset signal, please refer to the description above.

[0167] For step S720, the first start signal is, for example, a start signal st' as shown in FIG. 7B, the start signal st' including a basic trigger signal BT and at least one additional trigger signal AT continuous after the basic trigger signal. Figure 3

[0168] For example, as shown in FIG. 7B, the basic trigger signal is a low signal captured after a first active edge of a clock signal in a plurality of continuous clock periods after a last active edge Q' of the clock signal for providing a reset signal, and the additional trigger signal is a low signal captured after a second active edge of the clock signal and after a subsequent active edge of the clock signal in the plurality of continuous clock periods after the last active edge Q' of the clock signal. Figure 3

[0169] For the basic trigger signal and the additional trigger signal AT, refer to the foregoing description.

[0170] For example, the source driver and the controller communicate through a low-voltage differential signal interface to transmit a reset signal, a first start signal and a display signal. Step S720 includes: after obtaining the reset signal, sampling a differential signal output by the low-voltage differential signal interface at a plurality of rising edges of a clock signal, and the plurality of samplings obtaining the first start signal, the first start signal including a basic trigger signal and at least one additional trigger signal.

[0171] In this example, the plurality of rising edges of the clock signal are active edges of the clock signal. The signal transmitted on the low-voltage differential signal line pair is sampled at the rising edge of the clock signal. For example, the number of additional trigger signals is N, after the reset signal is captured, if a low signal is captured at the rising edge of the clock signal, the low signal is the basic trigger signal, and the low signals captured at the N rising edges after the rising edge are the N additional trigger signals.

[0172] For step S730, for example, the signals captured from the first active edge of the clock signal after the end of the additional trigger signal are all display signals of a frame of image, until the reset signal for the next frame of image is received again.

[0173] As shown in FIG. 7C, the signal transmission method can further include steps S740-S750 in addition to steps S710-S730. Figure 7 Step S740: receiving a second start signal provided by the controller after obtaining the reset signal. The second start signal only includes the basic trigger signal.

[0174] Step S750: receiving a display signal provided by the controller after the second start signal.

[0175]

[0176] ​​​For step S740, the source driver receives a second start signal provided by the controller after obtaining the reset signal. The second start signal is, for example, the start signal st shown in Figure 1A The base trigger signal is, for example, a low-level signal captured at the first active edge after obtaining the reset signal. If the low-level signal is captured only at the first active edge after the reset signal, the start signal includes only the base trigger signal, and the start signal is the second start signal.

[0177] For step S750, the signal captured at the second active edge after the reset signal is the display signal.

[0178] In the above embodiments, a suitable reset format can be selected according to different requirements, so that the signal transmission method can use different reset formats for different clock frequencies, has stronger applicability, and is beneficial to improving the frequency of signal transmission between the controller and the source driver.

[0179] The signal transmission method performed by the source driver corresponds to the signal transmission method performed by the controller described above, and will not be described again.

[0180] Figure 8 A schematic block diagram of a signal transmission apparatus 800 provided by at least one embodiment of the present disclosure is shown. The signal transmission apparatus 800 can be used to transmit a display signal to a source driver in a display apparatus.

[0181] For example, as shown in Figure 8 The signal transmission apparatus 800 includes a signal acquisition unit 810 and a signal providing unit 820.

[0182] The signal acquisition unit 810 is configured to acquire a reset signal, a first start signal, and a display signal. For example, the signal acquisition unit 810 can be an input interface, for example, for receiving the reset signal, the first start signal, and the display signal from an external device.

[0183] The signal providing unit 820 is configured to provide the reset signal to the source driver, and provide the first start signal to the source driver after providing the reset signal to the source driver.

[0184] The first start signal includes a base trigger signal and at least one additional trigger signal continuous after the base trigger signal, and the display signal is provided to the source driver after the first start signal ends. The at least one additional trigger signal is determined by the controller based on a clock frequency of a clock signal.

[0185] The signal providing unit 820 is, for example, a low-voltage differential signal interface.

[0186] The signal providing unit 820 can perform, for example, steps S10-S30 described above. Figure 2 The signal providing unit 820 can perform, for example, steps S10-S30 described above.

[0187] The signal transmission apparatus 800 is advantageous to improve the frequency of signal transmission between the controller and the source driver, and the source driver has sufficient time to perform reset and configuration and the like to fully prepare for the transmission of display signals.

[0188] Figure 9 A schematic block diagram of a signal transmission apparatus 900 is shown, which is provided by at least one embodiment of the present disclosure. The signal transmission apparatus 900 is configured to obtain display signals from a controller.

[0189] For example, as shown in Figure 9 The signal transmission apparatus 900 includes a signal obtaining unit 910.

[0190] The signal obtaining unit 910 is configured to obtain a reset signal provided by the controller, and in response to receiving a first start signal provided by the controller after obtaining the reset signal, receive a display signal provided by the controller after the end of the first start signal.

[0191] The first start signal includes a basic trigger signal and at least one additional trigger signal continuous after the basic trigger signal, and the at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal.

[0192] The signal providing unit 910 is, for example, a low-voltage differential signal interface.

[0193] The signal obtaining unit 910 may, for example, perform Figure 7 The steps S710-S730 described above.

[0194] The signal transmission apparatus 900 is advantageous to improve the frequency of signal transmission between the controller and the source driver, and the source driver has sufficient time to perform reset and configuration and the like to fully prepare for the transmission of display signals.

[0195] For example, the signal obtaining unit 810, the signal providing unit 820 and the signal obtaining unit 910 can be hardware, software, firmware or any feasible combination thereof. For example, the signal obtaining unit 810, the signal providing unit 820 and the signal obtaining unit 910 can be special-purpose or general-purpose circuits, chips or apparatuses, etc., or a combination of a processor and a memory. The specific implementation form of each unit described above is not limited by embodiments of the present disclosure.

[0196] It should be noted that in embodiments of the present disclosure, each unit of the signal transmission apparatus 800 and the signal transmission apparatus 900 corresponds to each step of the signal transmission method described above, and the specific functions of the signal transmission apparatus 800 and the signal transmission apparatus 900 can be referred to the related description of the signal transmission method, which will not be described here. Figure 8The signal transmission device 800 shown and Figure 9 The components and structures of the signal transmission device 900 shown are merely exemplary and not limiting. The signal transmission device 800 and signal transmission device 900 may also include other components and structures as needed.

[0197] At least one embodiment of this disclosure provides an electronic device 1000. The electronic device 1000 includes a signal transmission device provided in any embodiment of this disclosure. For example, the signal transmission device may be... Figure 8 The signal transmission device 800 or signal transmission device 900 shown.

[0198] For example, an electronic device includes signal transmission device 800 and signal transmission device 900. For a description of the electronic device, please refer to the section above on signal transmission device 800 and signal transmission device 900.

[0199] Figure 10 A schematic block diagram of an electronic device 1000 provided in at least one embodiment of this disclosure is shown. For example... Figure 10 As shown, the electronic device 1000 includes a controller 1010, a source driver 1020, and a display panel 1030.

[0200] The controller 1010 includes, for example, a signal transmission device 800 to perform the above. Figure 2 The described signal transmission method. The source driver 1020 includes, for example, a signal transmission device 900 to perform the above... Figure 7 The described signal transmission method. The display panel 1030 is, for example, a liquid crystal display panel, used to receive drive signals (i.e., grayscale voltage signals) provided by the source driver 1020 and display images.

[0201] The electronic device 1000 can be any electronic device with image display capabilities, including but not limited to smartphones, tablets, laptops, monitors, televisions, etc.

[0202] This electronic device facilitates increasing the frequency of signal transmission between the controller and the source driver, and the source driver has sufficient time to perform operations such as reset and configuration to fully prepare for the transmission of display signals.

[0203] Although the above points have been made, the following points still need to be clarified:

[0204] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0205] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0206] The above merely describes a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal, the method comprising: The controller provides a reset signal to the source driver during multiple consecutive clock cycles of the clock signal, wherein the reset signal is used to reset the source driver; After providing the reset signal to the source driver, a first start signal is provided to the source driver, wherein the first start signal includes a base trigger signal and at least one additional trigger signal following the base trigger signal; and After the first start signal ends, the display signal is provided to the source driver. Wherein, the at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal. The source driver acquires the base trigger signal provided by the controller at the first valid edge following the last valid edge of the plurality of consecutive clock cycles, and acquires at least one additional trigger signal provided by the controller at the valid edge of at least one consecutive clock signal following the first valid edge, to perform the reset during the time period between the first valid edge and the valid edge of the display signal.

2. The method according to claim 1, further comprising: Obtain the reset format, wherein the reset format includes a first format and a second format; After providing the reset signal to the source driver, providing the first start signal to the source driver includes: In response to the reset format being the first format, the first start signal is provided to the source driver after the reset signal is provided to the source driver.

3. The method according to claim 2, further comprising: In response to the reset format being the second format, after providing the reset signal to the source driver, a second start signal is provided to the source driver; as well as After the second start signal ends, the display signal is provided to the source driver. The second start signal includes only the basic trigger signal.

4. The method according to claim 2 or 3, wherein, Obtaining the reset format includes: Obtain the clock frequency; and In response to the clock frequency being greater than a preset frequency, the reset format is determined to be the first format; or in response to the clock frequency being less than or equal to the preset frequency, the reset format is determined to be the second format.

5. The method according to claim 1, wherein, At least two consecutive rising edges of the clock signal correspond to the basic trigger signal and the at least one additional trigger signal, respectively.

6. The method according to claim 1, wherein, The controller sequentially provides the reset signal, the first start signal, and the display signal to the source driver via a low-voltage differential signal interface.

7. A signal transmission method for a source driver to receive a display signal provided by a controller based on a clock signal, the method comprising: The source driver acquires a reset signal provided by the controller during multiple consecutive clock cycles of the clock signal, wherein the reset signal is used to reset the source driver; and In response to receiving the reset signal, the controller provides a first start signal. After the first start signal ends, the display signal provided by the controller is received. The first start signal includes a base trigger signal and at least one additional trigger signal following the base trigger signal. The at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal used by the display signal. The source driver acquires the base trigger signal provided by the controller at the first valid edge following the last valid edge of the plurality of consecutive clock cycles, and acquires at least one additional trigger signal provided by the controller at the valid edge of at least one consecutive clock signal following the first valid edge, to perform the reset during the time period between the first valid edge and the valid edge of the display signal.

8. The method according to claim 7, wherein, Also includes: In response to receiving the reset signal, a second start signal provided by the controller is received. Following the second start signal, the display signal provided by the controller is received. The second start signal includes only the basic trigger signal.

9. The method according to claim 1 or 7, wherein, The source driver and the controller communicate via a low-voltage differential signal interface to transmit the reset signal, the first start signal, and the display signal.

10. The method according to claim 9, wherein, After receiving the reset signal, the system receives the first start signal provided by the controller, including: After receiving the reset signal, the differential signal output from the low-voltage differential signal interface is sampled multiple times on multiple rising edges of the clock signal; The first starting signal is obtained by multiple samplings, wherein the first starting signal includes a basic trigger signal and the at least one additional trigger signal.

11. A signal transmission device for a controller to transmit a display signal to a source driver based on a clock signal, the device comprising: A signal providing unit is configured to provide a reset signal to the source driver during a plurality of consecutive clock cycles of the clock signal, wherein the reset signal is used to reset the source driver; After providing the reset signal to the source driver, a first start signal is provided to the source driver, wherein the first start signal includes a base trigger signal and at least one additional trigger signal following the base trigger signal, and after the first start signal ends, the display signal is provided to the source driver. Wherein, the at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal. The source driver is configured to acquire a base trigger signal provided by the controller at the first valid edge following the last valid edge of the plurality of consecutive clock cycles, and to acquire at least one additional trigger signal provided by the controller at the valid edge of at least one consecutive clock signal following the first valid edge, so as to perform the reset during the time period between the first valid edge and the valid edge of the display signal.

12. A signal transmission device for a source driver to receive a display signal provided by a controller based on a clock signal, the device comprising: A signal acquisition unit is configured to acquire a reset signal provided by the controller during multiple consecutive clock cycles of the clock signal, wherein the reset signal is used to reset the source driver; and In response to receiving the reset signal, the system receives a first start signal provided by the controller; after the first start signal ends, the system receives the display signal provided by the controller. The first start signal includes a base trigger signal and at least one additional trigger signal following the base trigger signal, wherein the at least one additional trigger signal is determined by the controller based on the clock frequency of the clock signal. The source driver is configured to acquire a base trigger signal provided by the controller at the first valid edge following the last valid edge of the plurality of consecutive clock cycles, and to acquire at least one additional trigger signal provided by the controller at the valid edge of at least one consecutive clock signal following the first valid edge, so as to perform the reset during the time period between the first valid edge and the valid edge of the display signal.

13. An electronic device, comprising: The signal transmission device according to claim 11 or 12.

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