Gate driving circuit, display substrate and display device

Abstract

The present disclosure provides a gate driving circuit, a display substrate and a display device. The display substrate comprises a gate driving circuit arranged in a semiconductor substrate, and a plurality of pixel circuits arranged in the semiconductor substrate, the gate driving circuit comprises a single-stage gate driving circuit in cascade, the single-stage gate driving circuit comprises a first circuit and a second circuit, the semiconductor substrate comprises a first well region and a plurality of second well regions, a depth of the first well region is greater than a depth of the second well region, the second circuit and the pixel circuit are arranged in the first well region, and the first circuit is arranged in the plurality of second well regions.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a gate driving circuit, a display substrate and a display device. BACKGROUND

[0002] This section is intended to provide background or context to the embodiments recited in the claims. The description herein does not constitute admission that the prior art is prior art nor does it constitute an admission of any description in this section as prior art to a presently claimed embodiment.

[0003] Micro-OLED is a new type of OLED display device with a silicon substrate as a substrate. The silicon-based OLED display substrate has the characteristics of small volume and high resolution, is made of mature integrated circuit CMOS process, and realizes active addressing of pixels. The silicon-based OLED display substrate can integrate gate driving circuit, source driving circuit, crystal oscillator, Gamma register, pixel circuit, etc. The silicon-based OLED display substrate is widely used in near-eye display and virtual reality, augmented reality fields, especially in AR / VR head-mounted display devices. SUMMARY

[0004] The present disclosure provides a gate driving circuit, a display substrate and a display device.

[0005] The present disclosure adopts the following technical solution: a display substrate, characterized by comprising a gate driving circuit arranged in a semiconductor substrate, and a plurality of pixel circuits arranged in the semiconductor substrate, the gate driving circuit comprising a single-stage gate driving circuit in cascade, the single-stage gate driving circuit comprising: a first circuit and a second circuit, the semiconductor substrate comprising a first well region and a plurality of second well regions, the depth of the first well region being greater than the depth of the second well regions, the second circuit and the pixel circuits being arranged in the first well region, and the first circuit being arranged in the plurality of second well regions.

[0006] In some embodiments, the first circuit comprises a single-stage shift register circuit and a logic operation circuit, and the second circuit comprises a level conversion circuit and a driving output circuit.

[0007] In some embodiments, the single-stage shift register circuit, the logic circuit, the level conversion circuit and the driving output circuit are arranged in a row along a first direction, the first direction being a connection direction of the gate driving circuit and a display area, and the plurality of pixel circuits are located in the display area.

[0008] In some embodiments, the single-stage gate drive circuit includes a one-to-one correspondence of multiple level conversion circuits and multiple drive output circuits, and the level conversion circuit and the corresponding drive output circuit have the same second working voltage, the second working voltage of the multiple level conversion circuits has multiple types, the level conversion circuit and the drive output circuit with the same second working voltage are located in the same continuous area, and the level conversion circuit and the drive output circuit with different second working voltages are located in different continuous areas.

[0009] In some embodiments, the first circuit includes a single-stage shift register circuit, and the second circuit includes a logic operation circuit and a drive output circuit.

[0010] In some embodiments, the single-stage shift register circuit, the logic circuit, and the drive output circuit are arranged in a row along a first direction, the first direction is a connection direction of the gate drive circuit and a display area, and the multiple pixel circuits are located in the display area.

[0011] In some embodiments, the single-stage gate drive circuit is a CMOS circuit, the NMOS tubes in the single-stage gate drive circuit are arranged in a row along the first direction, the PMOS tubes in the single-stage gate drive circuit are arranged in a row along the first direction, the substrate electrodes of a row of NMOS tubes in the single-stage gate drive circuit are located on the side of the active areas of the row of NMOS tubes away from the active areas of a row of PMOS tubes in the single-stage gate drive circuit, the substrate electrodes of a row of PMOS tubes in the single-stage gate drive circuit are located on the side of the active areas of the row of PMOS tubes away from the active areas of a row of NMOS tubes in the single-stage gate drive circuit, and the polarities of the two rows of MOS tubes close to each other in the adjacent two single-stage gate drive circuits are the same and share the substrate electrodes.

[0012] In some embodiments, the boundary of the substrate electrode towards the side of the corresponding active area is flush with the corresponding active area.

[0013] In some embodiments, the gate drive circuit includes a first metal layer, a second metal layer, and a second metal layer arranged in sequence in a direction away from the semiconductor substrate, most of the wires in the first metal layer are used for interconnection between the internal MOS tubes of the single-stage shift register circuit, the logic circuit, the level conversion circuit, and the drive output circuit, most of the wires in the second metal layer are used for interconnection between the single-stage shift register circuit, the logic circuit, the level conversion circuit, and the drive output circuit, and most of the wires in the third metal layer are used for interconnection between adjacent single-stage shift register circuits.

[0014] In some embodiments, the gate drive circuit comprises: a first metal layer, a second metal layer and a third metal layer arranged in sequence in a direction away from the semiconductor substrate; a majority of the traces in the first metal layer are used for interconnection between internal MOS tubes of the single-stage shift register circuit, the logic circuit and the drive output circuit; a majority of the traces in the second metal layer are used for interconnection between the single-stage shift register circuit, the logic circuit and the drive output circuit; and a majority of the traces in the third metal layer are used for interconnection between adjacent single-stage shift register circuits.

[0015] In some embodiments, a majority of the traces in the second metal layer extend in the first direction, and a majority of the traces in the third metal layer extend in a second direction, which is the arrangement direction of the cascaded single-stage gate drive circuits.

[0016] In some embodiments, the display substrate further comprises: an organic light-emitting diode driven by the pixel circuit.

[0017] The present disclosure adopts the following technical solution: a gate drive circuit comprising cascaded single-stage gate drive circuits, the single-stage gate drive circuit comprising: a single-stage shift register circuit, a logic operation circuit and a drive output circuit;

[0018] The single-stage shift register circuit is configured to pass an encoding sequence to a single-stage shift register circuit in a next-stage single-stage gate drive circuit.

[0019] The logic operation circuit is configured to map the encoding sequence into a plurality of drive signal waveforms.

[0020] The drive output circuit is configured to drive a plurality of gate lines one-to-one according to the plurality of drive signal waveforms.

[0021] In some embodiments, the single-stage shift register circuit comprises: a plurality of D flip-flops numbered in sequence, and two transmission gates connected to each D flip-flop.

[0022] The input end of the D flip-flop is connected to the output end of a D flip-flop of a corresponding number in a next-stage single-stage shift register circuit through one transmission gate, and the output end of the D flip-flop is connected to the input end of a D flip-flop of a corresponding number in the next-stage single-stage shift register circuit through the other transmission gate.

[0023] In some embodiments, the D flip-flop comprises: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first NAND gate, a second NAND gate, a first transmission gate, a second transmission gate and a third transmission gate.

[0024] The clock signal end of the D flip-flop is connected to the input end of the first NOT gate, and the output end of the first NOT gate is connected to a first node.

[0025] The input end of the second NOT gate is connected to the first node, and the output end of the second NOT gate is connected to the second node.

[0026] The first end of the first transmission gate is connected to the input end of the D flip-flop, the second end of the first transmission gate is connected to the first input end of the first NAND gate and the output end of the third NOT gate, the high-level active enable end of the first transmission gate is connected to the first node, and the low-level active enable end of the first transmission gate is connected to the second node.

[0027] The second input end of the first NAND gate is connected to the enable end of the D flip-flop, and the output end of the first NAND gate is connected to the input end of the third NOT gate and the first end of the second transmission gate.

[0028] The high-level active enable end of the third NOT gate is connected to the second node, and the low-level active enable end of the third NOT gate is connected to the first node.

[0029] The second end of the second transmission gate is connected to the first end of the third transmission gate and the input end of the fourth NOT gate, the high-level active enable end of the second transmission gate is connected to the second node, and the low-level active enable end of the second transmission gate is connected to the first node.

[0030] The second end of the third transmission gate is connected to the inverted output end of the D flip-flop and the output end of the second NAND gate, the high-level active enable end of the third transmission gate is connected to the first node, and the low-level active enable end of the third transmission gate is connected to the second node.

[0031] The output end of the fourth NOT gate is connected to the output end of the D flip-flop and the first input end of the second NAND gate.

[0032] The second input end of the second NAND gate is connected to the enable end of the D flip-flop.

[0033] In some embodiments, the logic operation circuit includes a NOT gate, a NAND gate, a NOR gate, a multiplexer, and a D latch.

[0034] In some embodiments, the logic operation circuit includes three output ends to output three different drive waveforms.

[0035] In some embodiments, the level conversion circuit includes a fifteenth NOT gate, a first N-type transistor, a second N-type transistor, a third P-type transistor, and a fourth P-type transistor.

[0036] The input end of the level conversion circuit is connected to the input end of the fifteenth NOT gate and the gate of the third transistor.

[0037] an output terminal of the fifteenth NOT gate is connected to a gate of the fourth transistor;

[0038] a source of the third transistor and a source of the third transistor are both connected to a first power supply terminal;

[0039] a drain of the third transistor is connected to an inverted output terminal of the level conversion circuit, a drain of the first transistor, and a gate of the second transistor;

[0040] a drain of the fourth transistor is connected to an output terminal of the level conversion circuit, a gate of the first transistor, and a drain of the second transistor;

[0041] sources of the first transistor and the second transistor are connected to a second power supply terminal.

[0042] In some embodiments, the level conversion circuit further comprises: a fifth transistor and a sixth transistor, a gate, a source, and a drain of the fifth transistor are all connected to the second power supply terminal, a gate, a source, and a drain of the sixth transistor are all connected to the second power supply terminal, the fifth transistor and the first transistor are adjacent to each other in a layout, and the sixth transistor and the second transistor are adjacent to each other in the layout.

[0043] In some embodiments, the driving output circuit comprises: at least one class A driving output circuit; the class A driving output circuit comprises: a sixth NAND gate, a seventh NAND gate, a sixteenth NOT gate, a seventh transistor of P type, and an eighth transistor of N type.

[0044] an input terminal and an enable terminal of the class A driving output circuit are connected to an input terminal of the sixth NAND gate, an output terminal of the sixth NAND gate is connected to a gate of the seventh transistor, and a source of the seventh transistor is connected to the first power supply terminal.

[0045] an inverted input terminal and an enable terminal of the class A driving output circuit are connected to an input terminal of the seventh NAND gate, an output terminal of the seventh NAND gate is connected to an input terminal of the sixteenth NOT gate, an output terminal of the sixteenth NOT gate is connected to a gate of the eighth transistor, and a source of the eighth transistor is connected to the second power supply terminal.

[0046] a drain of the seventh transistor and a drain of the eighth transistor are connected to an output terminal of the class A driving output circuit.

[0047] In some embodiments, the class A driving output circuit further comprises: a third transmission gate of always-on setting, and an output terminal of the sixth NAND gate is connected to the gate of the seventh transistor through the third transmission gate.

[0048] In some embodiments, the driving output circuit comprises: at least one class-B driving output circuit; the class-B driving output circuit comprises:

[0049] at least one N-type transistor, a source of the at least one N-type transistor receiving a second power supply voltage, a drain of the at least one N-type transistor being connected to an output end of the class-B driving output circuit, and a gate of the at least one N-type transistor receiving a signal obtained by performing an AND operation on an inverted input end and an enable end of the class-B driving output circuit;

[0050] at least two P-type transistors, a source of the at least two P-type transistors being connected to a first power supply end, a drain of the at least two P-type transistors being connected to the output end of the class-B driving output circuit, and a gate of the at least two P-type transistors respectively receiving a plurality of control signals obtained by performing an NAND operation on an input end and a plurality of rising edge adjusting ends of the class-B driving output circuit.

[0051] In some embodiments, the plurality of control signals are respectively transmitted to the gates of the corresponding P-type transistors through a constantly-on transmission gate.

[0052] The present disclosure adopts the following technical solution: a display substrate, comprising: the aforementioned gate driving circuit.

[0053] The present disclosure adopts the following technical solution: a display device, comprising the aforementioned display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a layout diagram of a display substrate of an embodiment of the present disclosure.

[0055] Figure 2 is a planar layout diagram of a single-stage gate driving circuit in a display substrate of an embodiment of the present disclosure.

[0056] Figure 3 is a circuit diagram of a single-stage shift register circuit in two adjacent single-stage shift register circuits of an embodiment of the present disclosure.

[0057] Figure 4 is a circuit diagram of part of a logic operation circuit of an embodiment of the present disclosure.

[0058] Figure 5 is an exemplary circuit diagram of a pixel circuit of an embodiment of the present disclosure.

[0059] Figure 6 is Figure 5 a timing diagram of the pixel circuit shown in FIG. 8.

[0060] Figure 7 is Figure 1 an exemplary schematic diagram of a cross-sectional view of the display substrate shown in FIG. 9.

[0061] Figure 8 is a layout of the single-stage gate drive circuit shown in FIG. 1. Figure 2

[0062] Figure 9 is a metal layer layout of the single-stage gate drive circuit shown in FIG. 1. Figure 2

[0063] Figure 10 is a partial layout of a display substrate of an embodiment of the present disclosure.

[0064] Figure 11

[0065] Figure 12

[0066] Figure 13

[0067] Figure 14

[0068] Figure 15

[0069] Figure 16

[0070] Figure 17

[0071] Figure 18

[0072] ​​​​​​​​​​Wherein the labels are as follows: 1, display substrate; AA, display area; GIP, single-stage gate drive circuit; Cell1, single-stage shift register circuit; Cell2, logic operation circuit; Level Shift1, first level shift circuit; Level Shift2, second level shift circuit; Level Shift3, third level shift circuit; Driver1, first drive output circuit; Driver2, second drive output circuit; Driver3, third drive output circuit; D1, D2, D3, D4, D flip-flop; CLK, clock signal; D, input terminal of D flip-flop; Q, output terminal of D flip-flop; QN, inverse output terminal of D flip-flop; CP, clock input terminal of D flip-flop; Driver1_Out, voltage output terminal of first drive output circuit; Driver2_Out, voltage output terminal of second drive output circuit; Driver3_Out, voltage output terminal of third drive output circuit; DATA, data line; ELVDD, power supply terminal; GND, ground terminal; VCOM, common electrode; LED, light emitting diode; T1, T2, T3, T4, transistor; C1, C2, capacitor; PSUB, P-type substrate; NWELL, N well; DNELL, deep N well; PWELL, P well; N+, N-type heavily doped region; P+, P-type heavily doped region; GI, gate insulating layer; G, gate; M1, first metal layer; M2, second metal layer; M3, third metal layer; GIP1 to GIPn, single-stage gate drive circuit; A1 to An, single-row pixel circuit; CKV1, CKV2, CKV3, CKV4, clock signal terminal; GSD_BW, control signal; GSD_FW, control signal; TG1 to TG8, transmission gate; A_Dn, B_Dn, C_Dn, D_Dn, input terminal of nth single-stage shift register circuit; A_Dn+1, B_Dn+1, C_Dn+1, D_Dn+1, input terminal of (n+1)th single-stage shift register circuit; A_Qn, B_Qn, C_Qn, D_Qn, output terminal of nth single-stage shift register circuit; A_Qn+1, B_Qn+1, C_Qn+1, D_Qn+1, output terminal of (n+1)th single-stage shift register circuit; A_Qn-, B_Qn-, C_Qn-, D_Qn-, inverse output terminal of nth single-stage shift register circuit; Rn, reset signal terminal; NOT1, first NOT gate; NOT2, second NOT gate; NOT3, third NOT gate; NOT4, fourth NOT gate; TG9, first transmission gate; TG10, second transmission gate; TG11, third transmission gate; NAND1, first NAND gate; NAND2, second NAND gate; CP-, first node; CP', second node; NAND3, third NAND gate; NOT5, fifth NOT gate; NOR1, first NOR gate; NOT6, sixth NOT gate; NOR2, second NOR gate; NOT7, seventh NOT gate;MUX2, Multiplexer; NOR3, Third NOR gate; NOT8, Eighth NOT gate; NOR4, Fourth NOR gate; NAND4, Fourth NAND gate; NOT9 to NOT14, Ninth to Fourteenth NOT gates; D_latch, D latch; NOR5, Fifth NOR gate; NAND5, Fifth NAND gate; WSn', WSn", WSn, Third gate drive signal; AZn', AZn", AZn, First gate drive signal; DSn', DSn", DSn, Second gate drive signal; WSn_b", Third inverted gate drive signal; AZn_b", First inverted gate drive signal; DSn_b", Third... Two inverting gate drive signals; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; NOT15, fifteenth NOT gate; VDD positive power supply terminal; VSS2 negative power supply terminal; NAND6, sixth NAND gate; NAND7, seventh NAND gate; NOT16, sixteenth NOT gate; TG11, third transmission gate; M7, seventh transistor; M8, eighth transistor; NAND8 to NAND12, NAND gates; NOT17, NOT gate; TG12 to TG15, transmission gates; M9 to M12, P-type transistors; M13 to M16, N-type transistors. Detailed Implementation

[0073] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0074] Figure 1 This is a layout diagram of the display substrate according to an embodiment of the present disclosure.

[0075] The display substrate is, for example, a silicon-based OLED display substrate. The substrate of the display substrate is not limited to silicon. In other embodiments, the substrate of the display substrate is a semiconductor substrate such as a silicon-containing substrate, an epitaxial silicon substrate, a silicon-coated insulating substrate, a silicon-germanium substrate, or a gallium arsenide substrate.

[0076] The display substrate contains an array of pixel circuits arranged in the display area. Figure 1 (Not shown in the image) and light-emitting elements that are connected one-to-one with the pixel circuitry. Examples of light-emitting elements include organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes. The pixel circuitry is fabricated on a semiconductor substrate. Due to the relatively high cost of semiconductor substrates, the size of the light-emitting elements should be as small as possible to increase the pixel density (PPI).

[0077] A gate driving circuit is disposed outside the display area AA of the display substrate. The gate driving circuit includes multiple cascaded single-stage gate driving circuits (GIPs). Each single-stage gate driving circuit (GIP) can, for example, provide gate control signals for a row of pixel circuits.

[0078] Figure 2FIG. 1 is a plan layout of a single-stage gate driving circuit (GIP) in a display substrate according to an embodiment of the present disclosure. Figure 3 FIG. 2 is a circuit diagram of a single-stage shift register circuit Cell1 of two adjacent single-stage shift register circuits GIP according to an embodiment of the present disclosure.

[0079] Figure 3 In the embodiment shown, the single-stage shift register circuit Cell1 includes four D flip-flops D1, D2, D3 and D4. The cascaded single-stage shift register circuits Cell1 receive the same clock signal. In two adjacent single-stage shift register circuits Cell1, the output terminal Q of the D flip-flop D1 of the former single-stage shift register circuit Cell1 is connected to the input terminal D of the D flip-flop D1 of the latter single-stage shift register circuit Cell1, the output terminal Q of the D flip-flop D2 of the former single-stage shift register circuit Cell1 is connected to the input terminal D of the D flip-flop D2 of the latter single-stage shift register circuit Cell1, the output terminal Q of the D flip-flop D3 of the former single-stage shift register circuit Cell1 is connected to the input terminal D of the D flip-flop D3 of the latter single-stage shift register circuit Cell1, and the output terminal Q of the D flip-flop D4 of the former single-stage shift register circuit Cell1 is connected to the input terminal D of the D flip-flop D4 of the latter single-stage shift register circuit Cell1.

[0080] The waveforms of the signals output by the respective D flip-flops D1, D2, D3 and D4 in the first single-stage shift register circuit Cell1 of the cascaded single-stage shift register circuits Cell1 are different, so that the cascaded single-stage shift register circuits Cell1 can simultaneously transmit four signal waveforms.

[0081] For example, the D flip-flops D1, D2, D3 and D4 each transmit a high-level pulse, and the phases are sequentially delayed by one clock cycle. Then, the single-stage shift register circuit Cell1 is equivalent to sequentially transmitting the codes (1, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0) and (0, 0, 0, 1) to the latter single-stage shift register circuit. The above example only indicates that the state output of at least one D flip-flop is different from the state outputs of the other D flip-flops in the same clock cycle.

[0082] The logic operation circuit Cell2 is configured to perform logic operation on the output terminals and / or the inverted output terminals of the respective D flip-flops of the single-stage shift register circuit Cell1, so as to obtain a plurality of output signals with different waveforms. That is, the logic operation circuit Cell2 maps the aforementioned code sequence into driving signals with different waveforms.

[0083] In some embodiments, the logic operation circuit Cell2 includes: inverters, NAND gates, transmission gates, NOR gates, latches, transmission gates, etc. In some embodiments, the logic operation circuit Cell2 also receives a global control signal as an input signal of some of the gates or devices.

[0084] Figure 4 is a circuit diagram of a part of the logic operation circuit Cell2 of the embodiments of the present disclosure.

[0085] The state output of the D flip-flop D3 is denoted as D3_Q, the state output of the D flip-flop D2 is denoted as D2_Q, the state output of the D flip-flop D4 is denoted as D4_Q, and the global reset signal is denoted as RESET.

[0086] Figure 4 The function of the circuit shown is to provide a pulse signal for the first level conversion circuit Level Shift1. The logic operation circuit Cell2 also provides pulse signals to the second level conversion circuit Level Shift2 and the third level conversion circuit Level Shift3. The waveforms of the three pulse signals are different.

[0087] The first, second and third level conversion circuits Level Shift1, Level Shift2 and Level Shift3 can convert the high voltage or low voltage of the pulse signal. For example, the low voltage can be converted from 0V to -3V or -5V. Thus, a low enough off voltage is provided for the NMOS transistor in the display area, or a low enough on voltage is provided for the PMOS transistor in the display area.

[0088] The first, second and third drive output circuits Driver1, Driver2 and Driver3 respectively buffer the pulse signals output by the first, second and third level conversion circuits Level Shift1, Level Shift2 and Level Shift3, and provide three different pulse signals to three gate lines. The three gate lines are connected to three signal terminals in the pixel circuit.

[0089] Figure 5 is a circuit diagram of a part of the logic operation circuit Cell2 of the embodiments of the present disclosure. Figure 6 is Figure 5 is a timing diagram of the pixel circuit shown.

[0090] Figure 5The pixel circuit shown comprises four transistors T1, T2, T3 and T4, two capacitors C1 and C2. A power supply terminal ELVDD provides a high-level power supply voltage for the pixel circuit, a ground terminal GND provides a ground signal, and a common electrode VCOM provides a common voltage. A voltage output terminal Driver1_Out of a first drive output circuit Driver1 is connected to the control electrode of the transistor T3; a voltage output terminal Driver2_Out of a second drive output circuit Driver2 is connected to the control electrode of the transistor T4; and a voltage output terminal Driver3_Out of a third drive output circuit Driver3 is connected to the control electrode of the transistor T1.

[0091] From Figure 6 It can be seen that the logic operation circuit Cell2 maps the state sequence of the single-stage shift register circuit Cell1 into three different waveforms.

[0092] The present disclosure does not limit the specific logic definition of the logic operation circuit, the definition of the state sequence of the single-stage shift register circuit Cell1, and the circuit structure of the pixel circuit. The above is only a division of the functional modules of the single-stage shift register circuit.

[0093] In some other embodiments, the logic operation circuit Cell2 receives a negative power supply voltage, so that the level conversion circuit can be omitted.

[0094] In these embodiments, the output terminal of the logic operation circuit is connected to the input terminal of the drive output circuit through an inverter.

[0095] In some embodiments, the single-stage shift register circuit, the logic circuit and the drive output circuit are arranged in a row along a first direction, the first direction being the connection direction of the gate drive circuit and the display area, and the plurality of pixel circuits are located in the display area.

[0096] Figure 7 is Figure 1 An exemplary schematic diagram of a cross-sectional view of the display substrate shown.

[0097] A deep N-well DNWELL is formed in the P-substrate PSUB, and then a P-well PWELL (for forming NMOS transistors therein) is formed in the deep N-well DNWELL, and an N-well (for forming PMOS transistors therein) is formed in the deep N-well DNWELL. The first, second and third level shift circuits Level Shift 1, Level Shift 2, Level Shift 3, the first, second and third driver output circuits Driver 1, Driver 2, Driver 3, and the pixel circuits in the display area AA all have negative working voltages, and in order to improve the process consistency, these circuits are fabricated in the same deep N-well DNWELL. Further, the deep N-well DNWELL area where the first, second and third level shift circuits Level Shift 1, Level Shift 2, Level Shift 3, the first, second and third driver output circuits Driver 1, Driver 2, Driver 3 are located can be regarded as a dummy area of the display area AA, which also greatly improves the process consistency of the pixel circuits and the like in the display area AA.

[0098] The single-stage shift register circuit Cell 1, the logic operation circuit Cell 2 do not need to be set in the deep N-well because they do not need negative working voltages.

[0099] Figure 9 Fig. 4 schematically shows a planar NMOS transistor and a planar PMOS transistor located outside the deep N-well DNWELL, and a planar NMOS transistor and a planar PMOS transistor located in the deep N-well DNWELL.

[0100] The NMOS transistor is set in the P-well PWELL, the source region and the drain region are N-type heavily doped regions N+, the gate insulating layer GI covers the source region, the drain region and the channel region therebetween, and the gate electrode G is set on the gate insulating layer GI. A P-type heavily doped region P+ is set in the top surface of the P-well PWELL for connecting a substrate electrode (not shown).

[0101] The PMOS transistor is set in the N-well NWELL, the source region and the drain region are P-type heavily doped regions P+, the gate insulating layer GI covers the source region, the drain region and the channel region therebetween, and the gate electrode G is set on the gate insulating layer GI. An N-type heavily doped region N+ is set in the top surface of the N-well NWELL for connecting a substrate electrode (not shown).

[0102] Referring again to Figure 2The low voltage of the working voltage of the first level shift circuit Level Shift1 and the first driving output circuit Driver1 is the same, for example, both are -3V. The two circuits are arranged together in the layout design. The low voltage of the working voltage of the second and third level shift circuits Level Shift2, Level Shift3, the second and third driving output circuits Driver2, Driver3 is the same, for example, both are -5V. The two circuits are arranged together in the layout design.

[0103] The first driving output circuit Driver1 is closer to the display area AA than the first level shift circuit Level Shift1. The second and third driving output circuits Driver2, Driver3 are closer to the display area AA than the second and third level shift circuits Level Shift2, Level Shift3.

[0104] The driving output circuit is closer to the display area AA, which can shorten the length of the wire from the driving output circuit to the display area AA and improve the driving capability of the driving output circuit.

[0105] Figure 8 is Figure 2 the layout of the single-stage gate drive circuit shown in

[0106] The first direction is the direction of the connection of the single-stage gate drive circuit and the display area AA, and the second direction is the arrangement direction of the single-stage gate drive circuit. In this example, the first direction is perpendicular to the second direction.

[0107] Figure 8 Two adjacent single-stage gate drive circuits GIP are shown in

[0108] The substrate electrodes of all the PMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along the first direction and are connected together. The substrate electrodes of all the NMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along the first direction and are connected together.

[0109] The polarities of the two rows of transistors opposite to each other in the two adjacent single-stage gate drive circuits are the same, and share a substrate electrode.

[0110] Such a design can shorten the size of the single-stage gate drive circuit GIP along the second direction and reduce the area of the single-stage gate drive circuit GIP.

[0111] In the embodiments of the present disclosure, continuing to refer to Figure 8The size of the substrate electrode close to the boundary of the active region (source region, drain region and channel region between the two) in the first direction is equal to the size of the active region in the first direction. In this way, the process uniformity can be improved.

[0112] Figure 9 is a partial layout of the single-stage gate drive circuit. Figure 2 is a layout of the metal layer of the single-stage gate drive circuit.

[0113] The single-stage gate drive circuit GIP circuit includes 3 layers of metal wiring: the first metal layer M1, the second metal layer M2 and the third metal layer M3 in the direction away from the substrate. Most of the wires in the first metal layer M1 are used for interconnection between transistors, most of the wires in the second metal layer M2 are used for interconnection between circuit modules (for example, single-stage shift register circuit Cell1 and logic operation circuit Cell2), and most of the wires in the third metal layer M3 are used for interconnection between single-stage gate drive circuits GIP circuits.

[0114] Thanks to the arrangement of the transistors in the single-stage gate drive circuit GIP circuit, 3 layers of metal layers are designed in the gate drive circuit. The number of wiring layers of the metal layer is less.

[0115] Thanks to the arrangement of the transistors in the single-stage gate drive circuit GIP circuit, most of the wires in the second metal layer M2 are extended in the first direction, and most of the wires in the second metal layer are extended in the second direction. In this way, the overlapping area between different metal layers can be reduced, and the parasitic capacitance on the metal layer can be reduced.

[0116] Figure 10 is a partial layout of the single-stage gate drive circuit.

[0117] The single-stage gate drive circuits GIP1, GIP2, …, GIPn are arranged in the second direction, and the single-stage gate drive circuits GIP1, GIP2, …, GIPn correspondingly drive the single-row pixel circuits A1, A2, …, An.

[0118] The size of a pair of MOS tubes in the single-stage gate drive circuits GIP1, GIP2, …, GIPn in the second direction is 5.868um. Correspondingly, the center distance of the pixel circuits in the display area AA in the second direction should be greater than or equal to 5.868um. The display substrate can be suitable for display products with 4k resolution.

[0119] Figure 11 is a partial layout of the single-stage gate drive circuit.

[0120] Voltage drop is significant in DC signal of long signal line. The driving output circuit is the main power consumption circuit module, and the DC power signal line VDD and VSS1 connected to it needs to have a large driving capacity. Reference Figure 11 In the second direction, the DC power signal line VDD and VSS1 in the second metal layer M3 is set, and the width (size in the first direction) of the DC power signal line VDD and VSS1 is 10um or more, which can reduce the wire resistance to 100Ω or less (basically does not affect the circuit performance). The sheet resistance of the DC power signal line VDD and VSS1 is low enough to reduce the influence of the voltage drop on the DC power signal line VDD and VSS1 on the whole column gate drive circuit. The layout design helps to improve the voltage drop on the DC power signal line VDD and VSS1.

[0121] In an example of the present disclosure, the single-stage gate base drive circuit has a first direction size of about 400um and a second direction size of 6.543um, which can be used for narrow frame products, and can also be used for products with pixel size (pixel pitch) greater than or equal to 6.543um.

[0122] Figure 12 is a circuit diagram of a single-stage shift register circuit of an embodiment of the present disclosure.

[0123] In this embodiment, the single-stage shift register circuit comprises a plurality of D flip-flops numbered in sequence, and two transmission gates connected corresponding to each D flip-flop; the input end of the D flip-flop is connected to the output end of the corresponding numbered D flip-flop in the next single-stage shift register circuit through one transmission gate, and the output end of the D flip-flop is connected to the input end of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate.

[0124] Specifically, referring to Figure 12 , the nth single-stage shift register circuit comprises a plurality of D flip-flops D1, D2, D3 and D4 numbered in sequence, and transmission gates TG1 to TG8.

[0125] The input end C_Dn of the D flip-flop D3 is connected to the output end C_Qn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through one transmission gate TG1, and the output end C_Qn of the D flip-flop D3 is connected to the input end C_Dn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate TG2.

[0126] The input end B_Dn of the D flip-flop D2 is connected to the output end B_Qn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through a transmission gate TG3, and the output end B_Qn of the D flip-flop D2 is connected to the input end B_Dn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through another transmission gate TG4.

[0127] The input end A_Dn of the D flip-flop D1 is connected to the output end A_Qn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through a transmission gate TG5, and the output end A_Qn of the D flip-flop D1 is connected to the input end A_Dn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through another transmission gate TG6.

[0128] The input end D_Dn of the D flip-flop D4 is connected to the output end D_Qn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through a transmission gate TG7, and the output end D_Qn of the D flip-flop D4 is connected to the input end D_Dn+1 of the D flip-flop of the corresponding number in the next single-stage shift register circuit through another transmission gate TG8.

[0129] The signals of the output ends and the inverted output ends of the D flip-flops D1, D2, D3 and D4 are subjected to logical operation in a logical operation circuit, so as to obtain a plurality of different signal waveforms.

[0130] The reset signal end RN of each D flip-flop D1, D2, D3 and D4 receives a global control signal LF_pulse1.

[0131] The control end of each transmission gate receives global control signals: a control signal GSD_BW and a control signal GSD_FW.

[0132] Figure 13 The circuit diagram of the D flip-flop in the embodiment of the present disclosure.

[0133] The D flip-flop comprises a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, a first NAND gate NAND1, a second NAND gate NAND2, a first transmission gate TG9, a second transmission gate TG10 and a third transmission gate TG11.

[0134] The clock signal end CP of the D flip-flop is connected to the input end of the first NOT gate NOT1, and the output end of the first NOT gate NOT1 is connected to a first node CP-.

[0135] The input end of the second NOT gate NOT2 is connected to the first node CP-, and the output end of the second NOT gate NOT2 is connected to a second node CP'.

[0136] The first end of the first transmission gate TG9 is connected with the input end D of the D flip-flop, the second end of the first transmission gate TG9 is connected with the first input end of the first NAND gate NAND1 and the output end of the third NOT gate NOT3, the high level active enable end of the first transmission gate TG9 is connected with the first node CP-, and the low level active enable end of the first transmission gate TG9 is connected with the second node CP';

[0137] The second input end of the first NAND gate NAND1 is connected with the enable end RN of the D flip-flop, the output end of the first NAND gate NAND1 is connected with the input end of the third NOT gate NOT3 and the first end of the second transmission gate TG10;

[0138] The high level active enable end of the third NOT gate NOT3 is connected with the second node CP', and the low level active enable end of the third NOT gate NOT3 is connected with the first node CP-;

[0139] The second end of the second transmission gate TG10 is connected with the first end of the third transmission gate TG11 and the input end of the fourth NOT gate NOT4, the high level active enable end of the second transmission gate TG10 is connected with the second node CP', and the low level active enable end of the second transmission gate TG10 is connected with the first node CP-;

[0140] The second end of the third transmission gate TG11 is connected with the inverse output end Q- of the D flip-flop and the output end of the second NAND gate NAND2, the high level active enable end of the third transmission gate TG11 is connected with the first node CP-, and the low level active enable end of the third transmission gate TG11 is connected with the second node CP';

[0141] The output end of the fourth NOT gate NOT4 is connected with the output end Q of the D flip-flop and the first input end of the second NAND gate NAND2;

[0142] The second input end of the second NAND gate NAND2 is connected with the enable end RN of the D flip-flop.

[0143] Figure 14 The circuit diagram of the logic operation circuit is shown in FIG. 1.

[0144] The output end B_Qn of the D flip-flop D2 and the output end C_Qn of the D flip-flop D3 are connected to two input ends of a third NAND gate NAN3. The output end of the third NAND gate NAN3 is connected to the output end of a fifth NOT gate NOT5. The output end of the fifth NOT gate NOT5 and the inverted output end A_Qn- of the D flip-flop D1 are connected to two output ends of a first NOR gate NOR1. The output end of the first NOR gate NOR1 is connected to the input end of a sixth NOT gate NOT6. The output end of the sixth NOT gate NOT6 and the clock signal end CKV4 are connected to two input ends of a second NOR gate NOR2. The output end of the second NOR gate NOR2 is connected to the input end of a seventh NOT gate NOT7. The output end of the seventh NOT gate NOT7 and the output end A_Qn of the first D flip-flop D1 are connected to two input ends A, B of a multiplexer MUX2. The output end of the multiplexer MUX2 outputs a third gate drive signal WSn' to a third level shift circuit Level Shifit3.

[0145] The second global control signal LF_pulse2 is input to the third NOR gate NOR3 together with the first global control signal LF_pulse1 after being inverted by an eighth NOT gate NOT8. The third NOR gate NOR3 is connected to the enable end C of the multiplexer MUX2.

[0146] The three input ends of the fourth NOR gate NOR4 are respectively connected to the output end B_Qn of the D flip-flop D2, the output end C_Qn of the D flip-flop D3 and the output end D_Qn of the D flip-flop D4. The two input ends of the fourth NAND gate NAND4 are respectively connected to the output end of the fourth NOR gate NOR4 and the global control signal LF_pulse2. The output end of the fourth NAND gate NAND4 is connected to the first level shift circuit Level Shift1 to provide the first gate drive signal DSn' to the first level shift circuit Level Shift1.

[0147] The third gate drive signal is buffered by the ninth NOT gate NOT9, the tenth NOT gate NOT10, the eleventh NOT gate NOT11, the twelfth NOT gate NOT12, the thirteenth NOT gate NOT13 and the fourteenth NOT gate NOT17 connected in sequence and then connected to the enable end EN of the D latch D_latch. The input end D of the D latch D_latch is connected to the output end B_Qn of the D flip-flop D2. The output end Q of the D latch D_latch and the inverted output end D_Qn- of the D flip-flop D4 are respectively connected to two input ends of a fifth NOR gate NOR5. The output end of the fifth NOR gate NOR5 and the global control signal LF_pulse2 are respectively connected to two input ends of a fifth NAND gate NAND5. The output end of the fifth NAND gate NAND5 is connected to the second level shift circuit Level Shift2 to provide the second gate drive signal DSn' to the second level shift circuit Level Shift2.

[0148] Figure 15 is a block diagram of a level shift circuit and a driving output circuit in a single-stage gate driving circuit of an embodiment of the present disclosure.

[0149] The third level shift circuit Level Shift3 converts the low voltage of the third gate driving signal WSn’ from 0V to a negative voltage, keeps the high voltage of the third gate driving signal WSn’ unchanged, obtains the third gate driving signal WSn”, and simultaneously outputs the third reverse gate driving signal WSn_b”. The high voltage period of the third reverse gate driving signal WSn_b” corresponds to the low voltage period of the third gate driving signal WSn”, and the low voltage period of the third reverse gate driving signal WSn_b” corresponds to the high voltage period of the third gate driving signal WSn”. The low voltage of the third reverse gate driving signal WSn_b” is equal to the low voltage of the third gate driving signal WSn”. The high voltage of the third reverse gate driving signal WSn_b” is equal to the high voltage of the third gate driving signal WSn”.

[0150] The first level shift circuit Level Shift3 converts the low voltage of the first gate driving signal AZn’ from 0V to a negative voltage, keeps the high voltage of the first gate driving signal AZn’ unchanged, obtains the first gate driving signal AZn”, and simultaneously outputs the first reverse gate driving signal AZn_b”. The high voltage period of the first reverse gate driving signal AZn_b” corresponds to the low voltage period of the first gate driving signal AZn”, and the low voltage period of the first reverse gate driving signal AZn_b” corresponds to the high voltage period of the first gate driving signal AZn”. The low voltage of the first reverse gate driving signal AZn_b” is equal to the low voltage of the first gate driving signal AZn”. The high voltage of the first reverse gate driving signal AZn_b” is equal to the high voltage of the first gate driving signal AZn”.

[0151] The second level shift circuit Level Shift3 converts the low voltage of the second gate driving signal DSn’ from 0V to a negative voltage, keeps the high voltage of the second gate driving signal DSn’ unchanged, obtains the second gate driving signal DSn”, and simultaneously outputs the second reverse gate driving signal DSn_b”. The high voltage period of the second reverse gate driving signal DSn_b” corresponds to the low voltage period of the second gate driving signal DSn”, and the low voltage period of the second reverse gate driving signal DSn_b” corresponds to the high voltage period of the second gate driving signal DSn”. The low voltage of the second reverse gate driving signal DSn_b” is equal to the low voltage of the second gate driving signal DSn”. The high voltage of the second reverse gate driving signal DSn_b” is equal to the high voltage of the second gate driving signal DSn”.

[0152] Figure 16 is a circuit diagram of a level shift circuit of an embodiment of the present disclosure.

[0153] The level shift circuit comprises a fifteenth NOT gate NOT15, a first transistor M1 of N type, a second transistor M2 of N type, a third transistor M3 of P type, and a fourth transistor M4 of P type.

[0154] An input end in of the level shift circuit is connected to an input end of the fifteenth NOT gate NOT15 and a gate of the third transistor M3.

[0155] An output end of the fifteenth NOT gate NOT15 is connected to a gate of the fourth transistor M4.

[0156] A source of the third transistor M3 and a source of the third transistor M3 are both connected to a positive power supply end VDD.

[0157] A drain of the third transistor M3 is connected to a reverse output end out_b of the level shift circuit, a drain of the first transistor M1, and a gate of the second transistor M2.

[0158] A drain of the fourth transistor M4 is connected to an output end out of the level shift circuit, a gate of the first transistor M1, and a drain of the second transistor M2.

[0159] Sources of the first transistor M1 and the second transistor M2 are connected to a negative power supply end VSS2.

[0160] In some embodiments, the level shift circuit further comprises a fifth transistor M5 and a sixth transistor M6, a gate, a source, and a drain of the fifth transistor M5 are all connected to the negative power supply end, a gate, a source, and a drain of the sixth transistor M6 are all connected to the negative power supply end, the fifth transistor M5 and the first transistor M1 are adjacent to each other in a layout, and the sixth transistor M6 and the second transistor M2 are adjacent to each other in the layout.

[0161] The fifth transistor and the sixth transistor are dummy transistors to improve process uniformity and consistency of the first transistor M1 and the second transistor M2.

[0162] A negative power supply voltage connected by the second level shift circuit Level shift2 and the second drive output circuit Driver2 is -5V, and a negative power supply voltage connected by the first and third level shift circuits Level shift1, 3 and the first and third drive output circuits Driver1, 3 is -3V.

[0163] Figure 17 is a circuit diagram of a first drive output circuit and a second drive output circuit of an embodiment of the present disclosure. The first drive output circuit and the second drive output circuit are Class A drive output circuits.

[0164] The Class A drive output circuit comprises a sixth NAND gate NAND6, a seventh NAND gate NAND7, a sixteenth NOT gate, a seventh transistor M7 of P type, and an eighth transistor M8 of N type.

[0165] The input end in and the enable end EN of the Class A drive output circuit are connected to the input end of the sixth NAND gate NAND6, the output end of the sixth NAND gate NAND6 is connected to the gate of the seventh transistor M7, and the source of the seventh transistor M7 is connected to the positive power supply end VDD.

[0166] The inverse input end in_b and the enable end EN of the Class A drive output circuit are connected to the input end of the seventh NAND gate NAND7, the output end of the seventh NAND gate NAND7 is connected to the input end of the sixteenth NOT gate, the output end of the sixteenth NOT gate is connected to the gate of the eighth transistor M8, and the source of the eighth transistor M8 is connected to the negative power supply end VSS.

[0167] The drain of the seventh transistor M7 and the drain of the eighth transistor M8 are connected to the output end of the Class A drive output circuit.

[0168] Optionally, the Class A drive output circuit further comprises a third transmission gate TG11 which is always on, and the output end of the sixth NAND gate NAND6 is connected to the gate of the seventh transistor M7 through the third transmission gate TG11. The third transmission gate TG11 plays a role of protecting the circuit. The high-level effective enable end of the third transmission gate TG11 is connected to the positive power supply voltage, and the low-level effective enable end is connected to the negative power supply voltage.

[0169] Figure 18 FIG. 3 is a circuit diagram of a third drive output circuit according to an embodiment of the present disclosure. The third drive output circuit is a Class B drive output circuit.

[0170] The Class B drive output circuit comprises:

[0171] At least one N-type transistor M13-M16, the source of the at least one N-type transistor M13-M16 receives a negative power supply voltage VSS1, the drain of the at least one N-type transistor M13-M16 is connected to the output end out of the Class B drive output circuit, and the gate of the at least one N-type transistor M13-M16 receives a signal obtained by performing AND operation on the inverse input end in_b and the enable end EN of the Class B drive output circuit (by performing operation through the NAND gate NAND12 and the NOT gate NOT17);

[0172] At least two P-type transistors M9-M12, the sources of the at least two P-type transistors M9-M12 are connected to the positive power supply end VDD, the drains of the at least two P-type transistors M9-M12 are connected to the output end out of the class-B driving output circuit, and the gates of the at least two P-type transistors M9-M12 correspondingly receive a plurality of control signals, which are obtained by performing NAND operations on the input end in of the class-B driving output circuit and a plurality of rising edge adjustment ends trc1-tr4.

[0173] The plurality of rising edge adjustment ends trc1-tr4 are used to adjust the rising edge slope of the output waveform of the class-B driving output circuit. The more ports that provide high-level voltage in the plurality of rising edge adjustment ends trc1-tr4, the steeper the rising edge of the output waveform of the class-B driving output circuit.

[0174] Optionally, the plurality of control signals are transmitted to the gates of the corresponding P-type transistors through a plurality of always-on transmission gates TG12-TG15. The transmission gates serve a protection function.

[0175] The embodiments of the present disclosure further provide a display substrate, comprising the foregoing gate driving circuit.

[0176] The embodiments of the present disclosure further provide a display device, comprising the foregoing display substrate.

[0177] The display device is, for example, any product or component with a display function, such as a display module, a mobile phone, a head-mounted display device, etc.

[0178] Each of the embodiments in the present disclosure is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the differences from other embodiments.

[0179] The scope of protection of the present disclosure is not limited to the above-described embodiments. Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the scope and spirit of the present disclosure. If these modifications and variations belong to the scope of the claims of the present disclosure and equivalent technologies thereof, the present disclosure also intends to include these modifications and variations.

Claims

1. A display substrate, characterized by, A gate drive circuit and a plurality of pixel circuits are provided in a semiconductor substrate, the gate drive circuit includes a cascade of single-stage gate drive circuits, each single-stage gate drive circuit includes a first circuit and a second circuit, the semiconductor substrate includes a first well region and a plurality of second well regions, the first well region has a greater depth than the second well regions, the second circuit and the pixel circuits having the same polarity operating voltage as the second circuit are provided in the first well region, and the first circuit is provided in the plurality of second well regions.

2. The display substrate of claim 1, wherein, The first circuit includes a single-stage shift register circuit and a logic operation circuit, and the second circuit includes a level conversion circuit and a drive output circuit. 3.The display substrate of claim 2, wherein, The single-stage shift register circuit, the logic operation circuit, the level conversion circuit and the drive output circuit are arranged in a row along a first direction, the first direction being a connection direction of the gate drive circuit and a display region, and the plurality of pixel circuits are located in the display region.

4. The display substrate of claim 3, wherein, The single-stage gate drive circuit includes a one-to-one corresponding plurality of level conversion circuits and a plurality of drive output circuits, and the level conversion circuit and the corresponding drive output circuit have the same second operating voltage, the plurality of level conversion circuits have a plurality of second operating voltages, the level conversion circuits and the drive output circuits having the same second operating voltage are located in the same continuous region, and the level conversion circuits and the drive output circuits having different second operating voltages are located in different continuous regions.

5. The display substrate of claim 1, wherein, The first circuit includes a single-stage shift register circuit, and the second circuit includes a logic operation circuit and a drive output circuit. 6.The display substrate of claim 5, wherein, The single-stage shift register circuit, the logic operation circuit and the drive output circuit are arranged in a row along a first direction, the first direction being a connection direction of the gate drive circuit and a display region, and the plurality of pixel circuits are located in the display region. 7.The display substrate of claim 3 or 6, wherein, The single-stage gate drive circuit is a CMOS circuit, the NMOS transistors in the single-stage gate drive circuit are arranged in a row along the first direction, the PMOS transistors in the single-stage gate drive circuit are arranged in a row along the first direction, the substrate electrodes of a row of NMOS transistors in the single-stage gate drive circuit are located on a side of the active regions of the row of NMOS transistors away from the active regions of a row of PMOS transistors in the single-stage gate drive circuit, the substrate electrodes of a row of PMOS transistors in the single-stage gate drive circuit are located on a side of the active regions of the row of PMOS transistors away from the active regions of a row of NMOS transistors in the single-stage gate drive circuit, and the polarities of the two rows of MOS transistors close to each other in the adjacent two single-stage gate drive circuits are the same and the substrate electrodes are shared. 8.The display substrate of claim 7, wherein, The boundary of the substrate electrode towards the side of the corresponding active region is flush with the corresponding active region. 9.The display substrate of claim 3, wherein, The gate drive circuit comprises: a first metal layer, a second metal layer and a third metal layer arranged in sequence in a direction away from the semiconductor substrate; most of the lines in the first metal layer are used for interconnection between internal MOS tubes of the single-stage shift register circuit, the logic operation circuit, the level conversion circuit and the drive output circuit; most of the lines in the second metal layer are used for interconnection between the single-stage shift register circuit, the logic operation circuit, the level conversion circuit and the drive output circuit; and most of the lines in the third metal layer are used for interconnection between adjacent single-stage shift register circuits. 10.The display substrate of claim 6, wherein, The gate drive circuit comprises: a first metal layer, a second metal layer and a third metal layer arranged in sequence in a direction away from the semiconductor substrate; most of the lines in the first metal layer are used for interconnection between internal MOS tubes of the single-stage shift register circuit, the logic operation circuit and the drive output circuit; most of the lines in the second metal layer are used for interconnection between the single-stage shift register circuit, the logic operation circuit and the drive output circuit; and most of the lines in the third metal layer are used for interconnection between adjacent single-stage shift register circuits. 11.The display substrate of claim 9 or 10, wherein, Most of the lines in the second metal layer extend in the first direction, and most of the lines in the third metal layer extend in a second direction, which is the arrangement direction of the cascaded single-stage gate drive circuits. 12.The display substrate of claim 1, wherein, The display substrate further comprises an organic light-emitting diode driven by the pixel circuit.

13. A display device comprising: The display substrate comprises the display substrate according to any one of claims 1 to 12.

Images