Memory device performing incremental step-pulse programming operation and operating method thereof

Abstract

The present invention relates to a non-volatile memory device that can include a peripheral circuit adapted to perform program loops, each program loop including a program operation and a verify operation, the program operation including a set operation to a plurality of bit lines and an apply operation to apply a program pulse to a selected word line; and a control logic circuit adapted to control the peripheral circuit, wherein the peripheral circuit can perform a first program loop of the program loops by: applying a first program pulse and a second program pulse in a first portion and a second portion, respectively, of the apply operation; from the set operation, setting a first bit line to a first level and a second bit line to a second level lower than the first level until the end of the first portion; and in the second portion, resetting the first bit line and the second bit line to the second level.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0121887, filed on September 13, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a memory device, and more specifically, to a non-volatile memory device and a method of operating the same that executes a program loop according to an incremental step pulse programming (ISPP) scheme. Background Technology

[0004] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices that lose the data stored in them when the power supply is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain the data stored in them even when the power supply is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly classified into NOR memory and NAND memory. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a nonvolatile memory device capable of improving the programming distribution of memory cells using incremental step pulse programming (ISPP) operation, and a method of operating the nonvolatile memory device.

[0006] According to an embodiment of the present invention, a non-volatile memory device may include: a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines; peripheral circuitry adapted to execute programming cycles, each programming cycle including a programming operation and a verification operation, the programming operation including a setting operation of the plurality of bit lines and an application operation of applying a programming pulse to a selected word line, the verification operation including applying a verification voltage to the selected word line; and control logic circuitry adapted to control the peripheral circuitry to repeatedly execute the programming cycle until programming for the selected word line is completed. The peripheral circuitry may execute a first programming cycle in the programming cycle by: in a first part of the application operation, applying a first programming pulse to the selected word line; in a second part of the application operation, applying a second programming pulse to the selected word line; starting from the setting operation, setting the first bit line group to a first voltage level and setting the second bit line group to a second voltage level lower than the first voltage level until the first part of the application operation ends; and in the second part of the application operation, resetting the first bit line group and the second bit line group to the second voltage level.

[0007] According to an embodiment of the present invention, an operation method for a non-volatile memory device includes: repeatedly executing a programming cycle until programming for selected word lines is completed, each programming cycle including a programming operation and a verification operation, the programming operation including a setting operation for multiple bit lines and an application operation of applying a programming pulse to the selected word lines, the verification operation including applying a verification voltage to the selected word lines. Repeated execution may include performing a first programming cycle in the programming cycle by: in a first portion of the application operation, applying a first programming pulse to the selected word lines; in a second portion of the application operation, applying a second programming pulse to the selected word lines; starting from the setting operation, setting a first bit line group to a first voltage level and setting a second bit line group to a second voltage level lower than the first voltage level until the end of the first portion of the application operation; and in the second portion of the application operation, resetting the first bit line group and the second bit line group to the second voltage level.

[0008] The technical attributes available from this disclosure are not limited to those described herein, and those skilled in the art to which this disclosure pertains will understand other technical attributes not described herein through the following detailed embodiments. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0010] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the memory device shown.

[0011] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the storage block shown.

[0012] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the memory device shown.

[0013] Figure 5 and Figure 6 This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0014] Figure 7 and Figure 8 This is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0015] Figure 9 and Figure 10 This is a diagram illustrating programming operations according to a third embodiment of the present disclosure.

[0016] Figure 11 This is a diagram illustrating the changes in the programming state of a memory cell during programming operations according to embodiments of the present disclosure. Detailed Implementation

[0017] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments that may be variations of any of the disclosed embodiments.

[0018] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as "one embodiment," "example embodiment," "embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "optional embodiments," etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but they may be combined in the same embodiment or may not need to be combined.

[0019] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0020] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured" to perform one or more tasks. In this context, "configured" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when a particular block / unit / circuit / component is not currently operational (e.g., not turned on or not activated), it can be said that the block / unit / circuit / component is configured to perform the task. Blocks / units / circuits / components used with the language "configured" include hardware, such as circuits, memory storing program instructions operable to perform operations, etc. Furthermore, "configured" may include general structures (e.g., general-purpose circuits) that are manipulated by software and / or firmware (e.g., an FPGA or general-purpose processor running software) to operate in a manner capable of performing the task in question. "Configured" may also include adjusting a manufacturing process (e.g., a semiconductor fabrication facility) to manufacture means (e.g., an integrated circuit) for performing or implementing one or more tasks.

[0021] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) purely hardware circuit implementations (such as implementations in analog and / or digital circuits only), and (b) combinations of circuits and software (and / or firmware), such as (if applicable): (i) combinations of processors or (ii) portions of processor / software (including digital signal processors, software, and memory that work together to enable devices such as mobile phones or servers to perform various functions), and (c) circuits such as microprocessors or portions thereof that require software or firmware to operate, even if such software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of the term in this application, including any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of only one or more processors or portions thereof and their accompanying software and / or firmware. For example, if applicable to a particular claim element, the terms “circuit” or “logic” also cover integrated circuits of memory devices.

[0022] As used herein, the terms “first,” “second,” “third,” etc., are used as labels preceding terms and do not imply any type of order (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second value. Furthermore, while these terms may be used herein to identify individual elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0023] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on those factors, or at least partially on those factors. For example, the phrase "A is determined based on B," while in this case B is a factor influencing the determination of A, does not exclude the possibility that A is also determined based on C. In other instances, A may be determined solely based on B.

[0024] In this document, a data item, data entry, or data term can be a bit order. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit order. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a data packet transmitted between two different components.

[0025] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or operatively connected to the memory system 110.

[0027] The host 102 may include any one of portable electronic devices such as mobile phones, MP3 players or laptop computers, and electronic devices such as desktop computers, game consoles, televisions (TV) or projectors.

[0028] Host 102 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is coupled to memory system 110, and users of memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further categorized into personal operating systems and enterprise operating systems based on system requirements or user environment. Personal operating systems, including Windows and Chrome, can be used to support services for general purposes. However, enterprise operating systems, including Windows Server, Linux, Unix, etc., can be dedicated to ensuring and supporting higher performance. Furthermore, mobile operating systems can include Android, iOS, Windows Mobile, etc. Mobile operating systems can be used to support services or functions for mobility (e.g., power-saving features). Host 102 can include multiple operating systems. In response to user requests, host 102 can run multiple operating systems interlocked with memory system 110. Host 102 can transmit multiple commands corresponding to user requests to memory system 110, thereby performing operations corresponding to the commands within memory system 110.

[0029] The memory system 110 operates in response to a request from the host 102, and specifically, can store data to be accessed by the host 102. The memory system 110 can be used as a main memory device or an auxiliary memory device of the host 102. Depending on the host interface protocol coupled to the host 102, the memory system 110 can be implemented as any of a variety of storage devices. For example, the memory system 110 can be implemented as a solid-state drive (SSD), a multimedia card (e.g., MMC, embedded MMC (eMMC), miniaturized MMC, and micro MMC), a secure digital card (e.g., SD, mini SD, and micro SD), a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash memory (CF) card, a smart media card, and a memory stick.

[0030] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102. The controller 130 may control the operation of storing data in the memory device 150.

[0031] The controller 130 and memory device 150 included in the memory system 110 can be integrated into a single semiconductor device, which can be included in any of the various types of memory systems discussed in the examples above.

[0032] By way of example, and not limitation, the controller 130 and memory device 150 can be implemented using an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be significantly higher than the operating speed of the host 102 implemented using a hard disk. Alternatively, the controller 130 and memory device 150 can be integrated into a single semiconductor device to form a memory card, such as a PC card (PCMCIA), a compact flash memory card (CF), a memory card such as a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC), an SD card (SD, mini SD, micro SD, SDHC), a general-purpose flash memory, etc.

[0033] The memory system 110 can be configured as, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0034] The memory device 150 may be a non-volatile memory device, and the data stored therein can be retained even when no power is supplied. The memory device 150 can store data provided by the host 102 through write operations, and provide the stored data to the host 102 through read operations.

[0035] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, each page may be a unit for storing data in the memory device 150 or retrieving data stored in the memory device 150.

[0036] A memory block can be a unit for erasing data. In embodiments, the memory device 150 can take many alternative forms such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory Device, Resistive RAM (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, the memory device 150 will be described as NAND Flash Memory.

[0037] Memory device 150 can receive commands and addresses from controller 130 and can access a region of the memory cell array selected by that address. That is, memory device 150 can perform operations instructed by commands on the region selected by the address. For example, memory device 150 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 150 can program data into the region selected by the address. During a read operation, memory device 150 can read data from the region selected by the address. During an erase operation, memory device 150 can erase the data stored in the region selected by the address.

[0038] The controller 130 controls all operations of the memory system 110.

[0039] When power is supplied to the memory system 110, the controller 130 can run firmware (FW). When the memory device 150 is a flash memory device, the controller 130 can run firmware such as a flash translation layer (FTL) to control communication between the host 102 and the memory device 150.

[0040] In this embodiment, the controller 130 may receive data and a logical block address (LBA) from the host 102, and may translate the logical block address into a physical block address (PBA) indicating the address of a memory cell included in the memory device 150 where data is to be stored. In this specification, logical block address (LBA) and logical address may be used with the same meaning. In this specification, physical block address (PBA) and physical address may be used with the same meaning.

[0041] The controller 130 can control the memory device 150 to perform programming, reading, or erasing operations in response to a request received from the host 102. During a programming operation, the controller 130 can provide programming commands, physical block addresses, and data to the memory device 150.

[0042] During a read operation, the controller 130 may provide a read command and a physical block address to the memory device 150. During an erase operation, the controller 130 may provide an erase command and a physical block address to the memory device 150.

[0043] In this embodiment, controller 130 can autonomously generate commands, addresses, and data regardless of requests from host 102, and can transmit these commands, addresses, and data to memory device 150. For example, controller 130 can provide commands, addresses, and data to memory device 150 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0044] In this embodiment, the controller 130 may control two or more memory devices 100. In this case, the controller 130 may control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme may be an operational mode in which the operation periods of at least two memory devices 100 overlap with each other.

[0045] The host 102 can communicate with the memory system 110 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0046] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the memory device shown.

[0047] Reference Figure 2 The memory device 150 may include a memory cell array 151, peripheral circuitry 152, and control logic circuitry 153.

[0048] Memory cell array 151 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to address decoder 155 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to page buffer group 156 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In an embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0049] A row line RL can include at least one source select line, multiple word lines, and at least one drain select line.

[0050] The memory cells included in the memory cell array 151 can be configured as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data.

[0051] Peripheral circuitry 152 can be configured to perform programming, reading, or erasing operations on selected regions of memory cell array 151. Peripheral circuitry 152 can drive memory cell array 151. For example, peripheral circuitry 152 can apply or release various operating voltages to row lines RL and bit lines BL1 to BLm.

[0052] The peripheral circuit 152 may include an address decoder 155, a voltage generator 154, a page buffer group 156, a data input / output circuit 157, and a sensing circuit 158.

[0053] The peripheral circuitry 152 can drive the memory cell array 151. For example, the peripheral circuitry 152 can drive the memory cell array 151 to perform programming operations, reading operations, and erasing operations.

[0054] Address decoder 155 can be connected to memory cell array 151 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines.

[0055] Address decoder 155 can be configured to operate in response to control of control logic circuitry 153. Address decoder 155 can receive address RADD from control logic circuitry 153.

[0056] Address decoder 155 can be configured to decode block addresses in a received address RADD. Address decoder 155 can select at least one memory block from BLK1 to BLKz based on the decoded block address. Address decoder 155 can also be configured to decode row addresses in a received address RADD. Address decoder 155 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 155 can apply an operating voltage Vop supplied from voltage generator 154 to the selected word line.

[0057] During programming operations, address decoder 155 can apply a programming voltage to the selected word line and a pass voltage with a lower level than the programming voltage to the unselected word line. During programming verification operations, address decoder 155 can apply a verification voltage to the selected word line and a verification pass voltage with a higher level than the verification voltage to the unselected word line.

[0058] During a read operation, the address decoder 155 can apply a read voltage to the selected word line and apply a read pass voltage that is higher than the read voltage to the unselected word line.

[0059] Erasing operations on memory device 150 can be performed on a block-by-block basis. The address ADDR input to memory device 150 during the erase operation includes the block address. Address decoder 155 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, address decoder 155 can apply a ground voltage to the word line of the selected memory block.

[0060] Voltage generator 154 can be configured to generate multiple operating voltages Vop using an external power supply voltage supplied to memory device 150. Voltage generator 154 can operate in response to control of control logic circuitry 153.

[0061] In this embodiment, voltage generator 154 can adjust an external power supply voltage and generate an internal power supply voltage. The internal power supply voltage generated by voltage generator 154 can be used as the operating voltage of memory device 150.

[0062] In this embodiment, voltage generator 154 can generate multiple operating voltages Vop using either an external or internal power supply voltage. Voltage generator 154 can be configured to generate various voltages required by the memory device 150. For example, voltage generator 154 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0063] The voltage generator 154 may include multiple pumping capacitors that receive an internal power supply voltage to generate multiple operating voltages Vop with various voltage levels, and in response to the control of the control logic circuit 153, generate multiple operating voltages Vop by selectively activating the multiple pumping capacitors.

[0064] The generated operating voltage Vop can be supplied to the memory cell array 151 through the address decoder 155.

[0065] Page buffer group 156 may include multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm may be connected to memory cell array 151 via multiple bit lines BL1 to BLm respectively. The multiple page buffers PB1 to PBm may operate in response to control logic 153.

[0066] Multiple page buffers PB1 to PBm can communicate with the data input / output circuit 157 via data DATA. During programming operations, the multiple page buffers PB1 to PBm can receive the data DATA to be stored through the data input / output circuit 157 and the data line DL.

[0067] During programming operations, when a programming voltage is applied to the selected word line, multiple page buffers PB1 to PBm can transfer data DATA received through data input / output circuit 157 to the selected memory cell via bit lines BL1 to BLm. Based on the transferred data DATA, the memory cell of the selected page can be programmed. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, multiple page buffers PB1 to PBm can read data stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0068] During a read operation, page buffer group 156 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm and store the read data DATA in multiple page buffers PB1 to PBm.

[0069] During an erase operation, page buffer group 156 can float bit lines BL1 to BLm. In an embodiment, page buffer group 156 may include column select circuitry.

[0070] The data input / output circuit 157 can be connected to multiple page buffers PB1 to PBm via data lines DL. The data input / output circuit 157 can operate in response to the control logic circuit 153.

[0071] Data input / output circuitry 157 may include multiple input / output buffers (not shown) for receiving data DATA input thereto. During programming operation, data input / output circuitry 157 may be able to receive data DATA from controller 130 (see reference 130). Figure 1 The data input / output circuit 157 receives the data to be stored. During a read operation, the data input / output circuit 157 can output the data DATA transferred from the multiple page buffers PB1 to PBm included in the page buffer group 156 to the controller 130 (see reference). Figure 1 ).

[0072] During a read or verification operation, the sensing circuit 158 ​​may generate a reference current in response to the permission bit VRY_BIT generated by the control logic circuit 153, and output a pass signal PASS or a failure signal FAIL to the control logic circuit 153 by comparing the sensed voltage VPB received from the page buffer group 156 with the reference voltage generated by the reference current.

[0073] Control logic circuitry 153 can be connected to address decoder 155, voltage generator 154, page buffer group 156, data input / output circuitry 157, and sensing circuitry 158. Control logic circuitry 153 can be configured to control all operations of memory device 150. Control logic circuitry 153 can operate in response to commands (CMD) transmitted from external devices.

[0074] Control logic circuit 153 can generate various signals in response to command CMD and address ADDR, and control other components 154 to 158 included in peripheral circuit 152. For example, control logic circuit 153 can generate operation signal OPSIG, address RADD, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic circuit 153 can output operation signal OPSIG to voltage generator 154, output address RADD to address decoder 155, output read and write control signal PBSIGNALS to page buffer group 156, and output enable bit VRYBIT to sensing circuit 158. In addition, control logic circuit 153 can determine whether the verification operation is successful or unsuccessful in response to pass signal PASS or failure signal FAIL output by sensing circuit 158.

[0075] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2A detailed diagram of the storage block shown.

[0076] Reference Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple memory cell strings ST connected between bit lines BL1 to BLm and a common source line (CSL). Bit lines BL1 to BLm can be individually connected to memory cell strings ST, and the common source line (CSL) can be collectively connected to memory cell strings ST. Because multiple memory cell strings ST can have the same configuration, the memory cell string ST connected to the first bit line BL1 is described in detail representatively.

[0077] A memory cell string ST may include a source selection transistor SST connected in series between a common source line CSL and a first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A memory cell string ST may include at least one drain selection transistor DST, and may include more source selection transistors SST and memory cells MC1 to MC16 than shown in the figures.

[0078] The source of the source select transistor SST can be connected to the common source line CSL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory cell strings ST can be connected to the source select line SSL, the gates of the drain select transistors DST included in different memory cell strings ST can be connected to the drain select line DSL, and the gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells in different memory cell strings ST connected to the same word line can be referred to as a physical page PG. Therefore, the memory block BLKi can include as many physical pages PG as word lines WL1 to WL16.

[0079] A memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PG) can store the data of a logical page (LPG). A logical page (LPG) can contain as many data bits as the cells included in a physical page (PG).

[0080] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPGs) of data.

[0081] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the memory device shown.

[0082] Reference Figure 4 The memory device 150 may include a memory cell array 151, a programming and verification circuit 41, a voltage generator 154, and a programming operation control unit 43.

[0083] Reference Figure 2 The described peripheral circuitry 152 may include programming and verification circuitry 41 and voltage generator 154. Programming and verification circuitry 41 may include... Figure 2 The address decoder 155, sensing circuit 158, page buffer group 156, and data input / output circuit 157 are shown. (See reference...) Figure 2 The described control logic circuit 153 may include a programming operation control unit 43. That is, the operation of the programming and verification circuit 41 to be described may be the operation of the peripheral circuit 152, and the operation of the programming operation control unit 43 may be the operation of the control logic circuit 153.

[0084] The memory cell array 151 may include multiple memory cells. The memory cell array 151 can be connected to the programming and verification circuitry 41 via multiple word lines WL connected to the multiple memory cells. The memory cell array 151 can also be connected to the programming and verification circuitry 41 via multiple bit lines BL connected to the multiple memory cells. Figure 3 As described above, multiple word lines (WL) and multiple bit lines (BL) can be cross-connected.

[0085] Voltage generator 154 can generate the operating voltage Vop required for operation of the memory cell in response to the voltage generation signal V_Gen. In the operating voltage Vop, the voltage applied to the word line can be the word line voltage. Voltage generator 154 can provide the generated operating voltage Vop to the programming and verification circuit 41.

[0086] The programming and verification circuit 41 can receive an operating voltage Vop from the voltage generator 154. The programming and verification circuit 41 can perform programming operations, including setting operations for multiple bit lines BL and applying operations (hereinafter referred to as "programming pulse application operations") for applying programming pulses to word lines selected as programming targets (hereinafter referred to as "programming target word lines") among the multiple word lines WL. The programming and verification circuit 41 can perform verification operations, applying verification voltages to the programming target word lines among the multiple word lines WL. The programming and verification circuit 41 can execute one or more programming cycles, each programming cycle including programming operations and verification operations.

[0087] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to repeatedly execute at least one programming cycle until the programming of the target word line among the multiple word lines WL is completed.

[0088] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a first programming pulse to the programming target word line during the first part of the programming pulse application operation of the programming operation included in the first programming cycle. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to apply a second programming pulse to the programming target word line during the second part of the programming pulse application operation of the programming operation included in the first programming cycle. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to set the first bit group of multiple bit lines BL to a first voltage level and set the second bit group to a second voltage level lower than the first voltage level at the start of the bit line setting operation of the programming operation included in the first programming cycle, and maintain these levels until the end of the first part of the programming pulse application operation of the programming operation included in the first programming cycle. In other words, the programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the first bit group of multiple bit lines BL to a first voltage level and set the second bit group to a second voltage level lower than the first voltage level from the start time of the bit line setting operation of the programming operation until the end of the first part of the programming pulse application operation within the first programming cycle. The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply the second part of the operation to the programming pulse of the programming operation included in the first programming cycle, resetting the first bit group and the second bit group of the multiple bit lines BL to the second voltage level.

[0089] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a third programming pulse to the programming target word line in an incremental step pulse programming (ISPP) method in a programming operation that can be included in a subsequent programming cycle that can be repeated after the first programming cycle.

[0090] Figure 5 and Figure 6 This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0091] Reference Figure 4 and Figure 5 The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to repeatedly execute N programming cycles PL1, PL2, PL3 to PLN until programming of the target word line among multiple word lines WL is completed, where N is a natural number equal to or greater than 2.

[0092] Specifically, the N programming cycles PL1, PL2, PL3 to PLN may include their respective programming operations PGM1, PGM2, PGM3 to PGMN and their respective verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN. The programming operations PGM1, PGM2, PGM3 to PGMN included in the N programming cycles PL1, PL2, PL3 to PLN may include their respective bit line setting operations SET UP1, SET UP2, SET UP3 to SET UPN and their respective programming pulse application operations SUPPLY1, SUPPLY2, SUPPLY3 to SUPPLYN.

[0093] Each of the programming operations PGM1, PGM2, PGM3 to PGMN included in the N programming cycles PL1, PL2, PL3 to PLN can be an operation that raises the threshold voltage of the programming target memory cell to a target threshold voltage corresponding to the target programming state, based on data to be stored in the selected memory cell (hereinafter referred to as the "programming target memory cell") connected to the programming target word line. According to an embodiment, reference is made to a memory cell that is a three-level cell (TLC). Figure 11 Based on the data stored in the target programming memory cells, the threshold voltage of the target programming memory cells can be set for a total of eight programming states: E, P1, P2, P3, P4, P5, P6, and P7. Before the programming cycles PL1, PL2, PL3 through PLN begin, all target programming memory cells are in the erase state E, and the programming cycles PL1, PL2, PL3 through PLN can be repeated until each of the target programming memory cells reaches its target programming state. For example, if a memory cell is targeted for programming state P7, its threshold voltage level needs to be increased relatively significantly, and therefore the number of repetitions of programming cycles PL1, PL2, PL3 through PLN may be relatively large. On the other hand, if a memory cell is targeted for programming state P1, its threshold voltage level can be increased relatively slightly, and therefore the number of repetitions of programming cycles PL1, PL2, PL3 through PLN may be relatively small.

[0094] Each of the verification operations VERIFY1, VERIFY2, VERIFY3, to VERIFYN included in the N programming cycles PL1, PL2, PL3 to PLN can be an operation to verify whether programming operations PGM1, PGM2, PGM3 to PGMN have been correctly executed on the target memory cell. That is, each of the verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN can be an operation to check whether the threshold voltage of the memory cell for which programming operations PGM1, PGM2, PGM3 to PGMN have been executed has reached the target threshold voltage corresponding to the target programming state of the programming operation. According to an embodiment, referring to a three-level cell (TLC) memory cell... Figure 11 When the verification operation detects that the threshold voltage level of the memory cell targeted by programming state P4 is in programming state P1, P2 or P3, the programming loop needs to be repeated. However, when the verification operation detects that the threshold voltage level of the memory cell targeted by programming state P4 is in programming state P4, the programming loop does not need to be repeated.

[0095] In an embodiment, the first programming loop PL1 may be executed in a manner different from subsequent programming loops PL2, PL3, PLN among the N programming loops PL1, PL2, PL3, PLN. In this disclosure, the first programming loop PL1 is the initial loop among programming loops PL1, PL2, PL3, PLN, which are repeatedly executed until programming of the target word line among the multiple word lines WL is completed.

[0096] In other words, in the embodiments, the programming pulse application operation SUPPLY1 included in the programming operation PGM1 of the first programming cycle PL1 among the N programming cycles PL1, PL2, PL3 to PLN can be divided into a first part SEC1 and a second part SEC2. In this disclosure, the first part SEC1 and the second part SEC2 of the programming pulse application operation within the first programming cycle PL1 are the first half and the second half of the programming pulse application operation. The first half and the second half can have the same duration or different durations. On the other hand, the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN included in the programming operations PGM2, PGM3 to PGMN respectively included in the subsequent programming cycles PL2, PL3 to PLN among the N programming cycles PL1, PL2, PL3 to PLN can each have only one part.

[0097] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a first programming pulse PU1 to the programming target word line in the first part SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to apply a second programming pulse PU2 to the programming target word line in the second part SEC2 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1.

[0098] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a third programming pulse PU3 to the programming target word line in the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3 to PLN that are repeated after the first programming cycle PL1, using the ISPP method. As shown in the figure, the voltage level of the third programming pulse PU3 can be increased according to the ISPP method as the programming cycles PL2, PL3 to PLN are repeated.

[0099] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of the second programming pulse PU2 to be lower than the voltage level of the first programming pulse PU1.

[0100] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of the third programming pulse PU3 to be higher than the voltage level of the second programming pulse PU2. According to an embodiment, the voltage level of the smallest pulse in the third programming pulse PU3, whose voltage level increases according to the repetition of programming cycles PL2, PL3 to PLN, can also be set to be higher than the voltage level of the second programming pulse PU2.

[0101] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of at least one of the third programming pulses PU3 to be lower than the voltage level of the first programming pulse PU1. According to an embodiment, the voltage level of the second programming pulse PU2 corresponding to the second programming cycle PL2 can be set to be lower than the voltage level of the first programming pulse PU1, and the voltage level of the third programming pulse PU3 corresponding to the third programming cycle PL3 can be set to be the same as the voltage level of the first programming pulse PU1.

[0102] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the first type TYPE1 at the start of the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1, and maintain these voltage levels until the end of the first part SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1. The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the first type TYPE1 from the start time of the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1 until the end of the first part SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1.

[0103] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to reset the voltage level of multiple bit lines BL to the second type TYPE2 in the second part SEC2 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1.

[0104] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 in the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, and maintain these voltage levels until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 from the start time of the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN.

[0105] When bit line BL is set to the first type TYPE1, the first bit group in the multiple bit lines BL can be set to the first voltage level, and the second bit group in the multiple bit lines BL can be set to the second voltage level, which is lower than the first voltage level.

[0106] When bit line BL is set to the second type TYPE2, the first bit group and the second bit group of multiple bit lines BL can be set to the second voltage level.

[0107] According to an embodiment, the first bit line group and the second bit line group can refer to bit lines among a plurality of bit lines BL that are connected to a programmable target memory cell. The first bit line group can refer to a bit line connected to a memory cell within the programmable target memory cell that targets a first threshold voltage level. The second bit line group can refer to a bit line connected to a memory cell within the programmable target memory cell that targets a second threshold voltage level. According to an embodiment, reference is made to a three-level cell (TLC) memory cell. Figure 11 Bit lines connected to memory cells targeting threshold voltage levels included in programming state P1 can be classified as the first bit line group, and bit lines connected to memory cells targeting threshold voltage levels included in programming states P2 to P7 can be classified as the second bit line group. According to another embodiment, when the memory cell is a three-level cell (TLC), bit lines connected to memory cells targeting threshold voltage levels included in programming states P1 to P3 can be classified as the first bit line group, and bit lines connected to memory cells targeting threshold voltage levels included in programming states P4 to P7 can be classified as the second bit line group.

[0108] According to an embodiment, the first voltage level may refer to the power supply voltage VCORE level, and the second voltage level may refer to the ground voltage VSS level.

[0109] When bit line BL is set to TYPE3, the voltage levels of multiple bit lines BL can be set based on whether additional programming cycles are required as a result of the verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN-1. When bit line BL is set to TYPE3, bit lines connected to memory cells requiring further programming cycles can be set to a programming-enabled level, and bit lines connected to memory cells not requiring further programming cycles can be set to a programming-disable level. The programming-enabled level can be the level of the ground voltage VSS, and the programming-disable level can be the level of the power supply voltage VCORE.

[0110] As described above, in the embodiment, the first programming cycle PL1 can be executed in a manner different from the subsequent programming cycles PL2, PL3, PLN among the N programming cycles PL1, PL2, PL3, PLN, and therefore the programming state of the memory cell can be as follows: Figure 11 The classification is as published in the document.

[0111] Reference Figure 11As a result of executing the first programming cycle PL1, the increase in the threshold voltage level of the memory cell targeted at programming state P1 can be relatively smaller than the increase in the threshold voltage level of the memory cell targeted at programming states P2 to P7. Therefore, as Figure 11 As shown, as a result of executing the first programming cycle PL1, the programming state of the memory cell can be one of two provisional states.

[0112] In this way, each of the target memory cells can be programmed to have a target threshold voltage level by executing the first programming cycle PL1 and then repeating the subsequent programming cycles PL2, PL3 to PLN.

[0113] Reference Figure 6 It can be seen from the reference Figure 4 and Figure 5 In what order are the programming operations of the first embodiment described executed?

[0114] When programming begins, in operation S60, it can be checked whether the current programming loop is the first programming loop PL1 among programming loops PL1, PL2, PL3 to PLN. Programming loops PL1, PL2, PL3 to PLN are executed repeatedly until the programming of the target word line in the multiple word lines WL is completed.

[0115] When the check result indicates that the current programming cycle is the first programming cycle PL1 (i.e., "yes" in operation S60), in operation S61, multiple bit lines BL can be set to the first type TYPE1 in the bit line setting operation SET UP1 of programming operation PGM1. That is, the first bit line group in the multiple bit lines BL can be set to the first voltage level, and the second bit line group can be set to a second voltage level lower than the first voltage level.

[0116] In operation S62 following operation S61, the first programming pulse PU1 can be applied to the programming target word line in the first part SEC1 included in the programming pulse application operation SUPPLY1 of programming operation PGM1.

[0117] Following operation S62, in the second part SEC2 of the programming pulse application operation SUPPLY1 of programming operation PGM1, the operations of setting multiple bit lines BL to the second type TYPE2 in operation S63 and applying the second programming pulse PU2 to the programming target word line in operation S64 can be performed simultaneously. In this case, the voltage level of the second programming pulse PU2 can be lower than the voltage level of the first programming pulse PU1. That is, the voltage level of the second programming pulse PU2 can be lower than the voltage level of the first programming pulse PU1 (less than PU1).

[0118] In operation S67, which follows operations S63 and S64, the verification operation VERIFY1 can be performed.

[0119] When the check result indicates that the current programming cycle is not the first programming cycle PL1 (i.e., "No" in operation S60), meaning the current programming cycle is a subsequent programming cycle PL2, PL3 to PLN, multiple bit lines BL can be set to the third type TYPE3 in the bit line setting operations SET UP2, SET UP3 to SET UPN of programming operations PGM2, PGM3 to PGMN in operation S65. In other words, it can be determined whether an additional programming cycle is needed to set the voltage level of each of the multiple bit lines BL based on the result of the verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN-1.

[0120] In operation S66 following operation S65, a third programming pulse PU3 can be applied to the programming target word line using the ISPP method during the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN of programming operations PGM2, PGM3 to PGMN. In this case, the voltage level of the third programming pulse PU3 can be increased according to the ISPP method with the repetition of programming cycles PL2, PL3 to PLN. Moreover, the voltage level of the third programming pulse PU3 can be higher than the voltage level of the second programming pulse PU2 (greater than PU2). The voltage level of at least one of the third programming pulses PU3 can be lower than the voltage level of the first programming pulse PU1.

[0121] In operation S67, which follows operation S66, the verification operation VERIFY1 can be performed.

[0122] In operation S68, which follows operation S67, it is possible to check whether the programming is complete.

[0123] Programming can terminate when it is complete (i.e., "yes" in operation S68).

[0124] The programming loop can be repeated when programming is not completed (i.e., "No" in operation S68).

[0125] Figure 7 and Figure 8 This is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0126] Reference Figure 4 and Figure 7 , such as in Figure 5 and Figure 6The programming operation described in the first embodiment, even in the programming operation according to the second embodiment, the first programming loop PL1 can be executed in a different manner than the subsequent programming loops PL2, PL3 to PLN among the N programming loops PL1, PL2, PL3 to PLN.

[0127] In other words, in the embodiment, the programming pulse application operation SUPPLY1 included in the programming operation PGM1 of the first programming cycle PL1 among the N programming cycles PL1, PL2, PL3 to PLN can be divided into a first part SEC1 and a second part SEC2. On the other hand, the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN included in the programming operations PGM2, PGM3 to PGMN respectively included in the subsequent programming cycles PL2, PL3 to PLN among the N programming cycles PL1, PL2, PL3 to PLN can each have only one part.

[0128] In particular, in the programming operation according to the second embodiment, it can be seen that the length of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1 is relatively greater than the length of the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN of the programming operations PGM2, PGM3 to PGMN included in the subsequent programming cycles PL2, PL3 to PLN.

[0129] Specifically, the programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a first programming pulse PU1 to the programming target word line in the first portion SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to apply a second programming pulse PU2 to the programming target word line in the second portion SEC2 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1. According to an embodiment, as shown in the accompanying drawings, the length of the first portion SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1 can be set to be greater than the length of the second portion SEC2. According to another embodiment, unlike the accompanying drawings, the length of the first portion SEC1 and the length of the second portion SEC2 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1 can be set to be the same.

[0130] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a third programming pulse PU3 to the programming target word line in the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3 to PLN that are repeated after the first programming cycle PL1, using the ISPP method. As shown in the figure, the voltage level of the third programming pulse PU3 can be increased according to the ISPP method as the programming cycles PL2, PL3 to PLN are repeated.

[0131] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of the first programming pulse PU1 to be the same as the voltage level of the second programming pulse PU2.

[0132] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of the third programming pulse PU3 to be higher than the voltage levels of the first programming pulse PU1 and the second programming pulse PU2. According to an embodiment, the voltage level of the smallest pulse among the third programming pulses PU3, whose voltage level increases according to the repetition of programming cycles PL2, PL3 to PLN, can also be set to be higher than the voltage levels of the first programming pulse PU1 and the second programming pulse PU2.

[0133] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the first type TYPE1 at the start of the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1, and maintain these voltage levels until the end of the first part SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1. The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the first type TYPE1 from the start time of the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1 until the end of the first part SEC1 of the programming pulse application operation SUPPLY1 of the programming operation PGM1.

[0134] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to reset the voltage level of multiple bit lines BL to the second type TYPE2 in the second part SEC2 of the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1.

[0135] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 in the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, and maintain these voltage levels until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 from the start time of the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN.

[0136] Reference Figure 8 It can be seen from the reference Figure 4 and Figure 7 In what order are the programming operations of the second embodiment described executed?

[0137] When programming begins, in operation S80, it can be checked whether the current programming loop is the first programming loop PL1 among programming loops PL1, PL2, PL3 to PLN. Programming loops PL1, PL2, PL3 to PLN are executed repeatedly until the programming of the target word line in the multiple word lines WL is completed.

[0138] When the check result indicates that the current programming cycle is the first programming cycle PL1 (i.e., "yes" in operation S80), in operation S89, the length of the programming operation PGM1 included in the first programming cycle PL1 can be set to be greater than the length of the programming operations PGM2, PGM3 to PGMN included in the subsequent programming cycles PL2, PL3 to PLN (greater than PGM<2:N>).

[0139] In operation S81 following operation S89, multiple bit lines BL can be set to the first type TYPE1 in the bit line setting operation SET UP1 of programming operation PGM1. The first bit group of multiple bit lines BL can be set to the first voltage level, and the second bit group of multiple bit lines BL can be set to a second voltage level lower than the first voltage level.

[0140] In operation S82 following operation S81, the first programming pulse PU1 can be applied to the programming target word line in the first part SEC1 included in the programming pulse application operation SUPPLY1 of programming operation PGM1.

[0141] After operation S82, in the second part SEC2 of the programming pulse application operation SUPPLY1 of programming operation PGM1, the operation of setting multiple bit lines BL to the second type TYPE2 in operation S83 and the operation of applying the second programming pulse PU2 to the programming target word line in operation S84 can be performed simultaneously. In this case, the second programming pulse PU2 can have the same voltage level as the first programming pulse PU1. That is, although the first programming pulse PU1 set in the first embodiment above has a relatively high voltage level (higher level, refer to...), the second programming pulse PU2 can have the same voltage level as the first programming pulse PU1. Figure 6 However, in the second embodiment, the first programming pulse PU1 can have a relatively low voltage level (smaller level). Furthermore, in the second embodiment, the second programming pulse PU2 can have the same voltage level as the first programming pulse PU1 (same as PU1).

[0142] In operation S87, which follows operations S83 and S84, the verification operation VERIFY1 can be performed.

[0143] When the check result indicates that the current programming cycle is not the first programming cycle PL1 (i.e., "No" in operation S80), meaning the current programming cycle is a subsequent programming cycle PL2, PL3 to PLN, multiple bit lines BL can be set to the third type TYPE3 in the bit line setting operations SET UP2, SET UP3 to SET UPN of programming operations PGM2, PGM3 to PGMN in operation S85. In other words, the voltage level of each of the multiple bit lines BL can be set based on the result of the verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN-1.

[0144] In operation S86 following operation S85, a third programming pulse PU3 can be applied to the programming target word line using the ISPP method during the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN of programming operations PGM2, PGM3 to PGMN. In this case, the voltage level of the third programming pulse PU3 can be increased according to the ISPP method with the repetition of programming cycles PL2, PL3 to PLN. Moreover, the voltage level of the third programming pulse PU3 can be higher than the voltage levels of the first programming pulse PU1 and the second programming pulse PU2 (greater than PU1 and PU2).

[0145] In operation S87, which follows operation S86, the verification operation VERIFY1 can be performed.

[0146] In operation S88, which follows operation S87, it is possible to check whether the programming is complete.

[0147] Programming can terminate when it is complete (i.e., "yes" in operation S88).

[0148] The programming loop can be repeated when programming is not completed (i.e., "No" in operation S88).

[0149] Figure 9 and Figure 10 This is a diagram illustrating programming operations according to a third embodiment of the present disclosure.

[0150] Reference Figure 4 and Figure 9 , such as in Figure 5 and Figure 6 In the first embodiment and Figure 7 and Figure 8 The programming operation described in the second embodiment, even in the programming operation according to the third embodiment, the first programming loop PL1 can be executed in a different manner than the subsequent programming loops PL2, PL3 to PLN among the N programming loops PL1, PL2, PL3 to PLN.

[0151] In one embodiment, the programming pulse application operation SUPPLY1 included in the programming operation PGM1 of the first programming cycle PL1, one of the N programming cycles PL1, PL2, PL3 to PLN, may include only one part. On the other hand, in a third embodiment different from the first and second embodiments, similar to the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN included in the programming operations PGM2, PGM3 to PGMN respectively included in the subsequent programming cycles PL2, PL3 to PLN, the programming pulse application operation SUPPLY1 included in the programming operation PGM1 of the first programming cycle PL1 may include only one part.

[0152] The difference lies in that the programming operation control unit 43 can control the operation of the programming and verification circuit 41 to apply a fourth programming pulse PU4 to the programming target word line in the programming pulse application operation SUPPLY1 included in the programming operation PGM1 included in the first programming cycle PL1. In this case, the voltage level of the fourth programming pulse PU4 can be lower than the voltage level of the first programming pulse PU1 shown in the first embodiment and higher than the voltage level of the second programming pulse PU2 shown in the first embodiment. The voltage level of the fourth programming pulse PU4 can be lower than the voltage level of the third programming pulse PU3 applied to the programming target word line in the programming operations PGM2, PGM3 to PGMN included in the subsequent programming cycles PL2, PL3 to PLN repeated after the first programming cycle PL1.

[0153] Another difference is that the programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the fourth type TYPE4 in the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1, and maintain these voltage levels until the programming pulse application operation SUPPLY1 of the programming operation PGM1 included in the first programming cycle PL1 ends. The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage levels of multiple bit lines BL to the fourth type TYPE4 from the start time of the bit line setting operation SET UP1 of the programming operation PGM1 included in the first programming cycle PL1 until the programming pulse application operation SUPPLY1 of the programming operation PGM1 ends.

[0154] The programming operation control unit 43 can control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 in the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, and maintain these voltage levels until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN. The programming operation control unit 43 can also control the operation of the programming and verification circuit 41 to set the voltage level of multiple bit lines BL to the third type TYPE3 from the start time of the bit line setting operations SETUP2, SETUP3, to SET UPN of the programming operations PGM2, PGM3, to PGMN included in the subsequent programming cycles PL2, PL3, to PLN, until the end of the programming pulse application operations SUPPLY2, SUPPLY3, to SUPPLYN.

[0155] When bit lines BL are set to TYPE4, similar to TYPE1 described in the first and second embodiments, the first bit group of multiple bit lines BL can be set to a first voltage level, and the second bit group can be set to a second voltage level lower than the first voltage level. However, although the first and second embodiments show the first voltage level as the power supply voltage VCORE level in TYPE1, the first voltage level in TYPE4 described in the third embodiment can refer to a reference voltage level lower than the power supply voltage VCORE level and higher than the ground voltage VSS level. Even in TYPE4, the second voltage level can refer to the ground voltage VSS level.

[0156] For reference, although the first voltage level in the first type TYPE1 described in the first and second embodiments is the power supply voltage VCORE level, the first voltage level can be a reference voltage level that is lower than the power supply voltage VCORE level and higher than the ground voltage VSS level. That is, the first type TYPE1 and the fourth type TYPE4 can be set identically according to the designer's decision.

[0157] Reference Figure 10 It can be seen from the reference Figure 4 and Figure 9 In what order are the programming operations of the third embodiment described executed?

[0158] When programming begins, in operation S100, it can be checked whether the current programming loop is the first programming loop PL1 among programming loops PL1, PL2, PL3 to PLN. Programming loops PL1, PL2, PL3 to PLN are executed repeatedly until the programming of the target word line in the multiple word lines WL is completed.

[0159] When the check result indicates that the current programming cycle is the first programming cycle PL1 (i.e., "Yes" in operation S100), in operation S101, multiple bit lines BL can be set to the fourth type TYPE4 in the bit line setting operation SET UP1 of programming operation PGM1. That is, the first bit group in the multiple bit lines BL can be set to a first voltage level, and the second bit group can be set to a second voltage level lower than the first voltage level. Specifically, the first bit group can be set to a reference voltage level lower than the power supply voltage VCORE level and higher than the ground voltage VSS level, and the second bit group can be set to the ground voltage VSS level.

[0160] In operation S102 following operation S101, a fourth programming pulse PU4 can be applied to the programming target word line in the first part SEC1 included in the programming pulse application operation SUPPLY1 of programming operation PGM1. The fourth programming pulse PU4 may have a voltage level (intermediate level) that is lower than that of the first programming pulse PU1 set in the first embodiment above and higher than that of the second programming pulse PU2 set in the first embodiment above.

[0161] In operation S107, which follows operation S102, the verification operation VERIFY1 can be performed.

[0162] When the check result indicates that the current programming cycle is not the first programming cycle PL1 (i.e., "No" in operation S100), meaning the current programming cycle is a subsequent programming cycle PL2, PL3 to PLN, multiple bit lines BL can be set to the third type TYPE3 in the bit line setting operations SET UP2, SET UP3 to SET UPN of programming operations PGM2, PGM3 to PGMN in operation S105. In other words, it can be determined whether an additional programming cycle is needed to set the voltage level of each of the multiple bit lines BL based on the result of the verification operations VERIFY1, VERIFY2, VERIFY3 to VERIFYN-1.

[0163] In operation S106 following operation S105, a third programming pulse PU3 can be applied to the programming target word line using the ISPP method during the programming pulse application operations SUPPLY2, SUPPLY3 to SUPPLYN of programming operations PGM2, PGM3 to PGMN. In this case, the voltage level of the third programming pulse PU3 can be increased according to the ISPP method with the repetition of programming cycles PL2, PL3 to PLN. Moreover, the voltage level of the third programming pulse PU3 can be higher than the voltage level of the fourth programming pulse PU4 (greater than PU4).

[0164] In operation S107, which follows operation S106, the verification operation VERIFY1 can be performed.

[0165] In operation S108, which follows operation S107, you can check whether the programming is complete.

[0166] When programming is complete (i.e., "yes" in operation S108), programming can be terminated.

[0167] The programming loop can be repeated when programming is not completed (i.e., "No" in operation S108).

[0168] According to embodiments of this disclosure, the programming pulse applied in the first programming operation of an incremental step-pulse programming (ISPP) operation can be divided into two, and the bit line setting levels can be set differently based on the two divided programming pulses. Therefore, when the first programming operation is completed, the programming distribution of memory cells can be improved.

[0169] The effects and advantages that can be obtained from this disclosure are not limited to those described herein. Based on the detailed description above, those skilled in the art to which this disclosure pertains will clearly understand other effects and advantages not described herein.

[0170] While this disclosure has been illustrated and described with reference to specific embodiments and drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that this disclosure can be implemented in various ways by substitution, alteration, and modification, as will be recognized by those skilled in the art based on this disclosure, without departing from the spirit and / or scope of this disclosure and the appended claims.

[0171] For example, the arrangement and type of logic gates and transistors described in the foregoing embodiments can be implemented differently depending on the polarity of the input signal. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A non-volatile memory device, comprising: a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; peripheral circuitry that performs program loops, each program loop including a program operation and a verify operation, the program operation including a set operation to the plurality of bit lines and an apply operation that applies a program pulse to a selected word line, and the verify operation including applying a verify voltage to the selected word line; and control logic circuitry that controls the peripheral circuitry to repeatedly perform the program loops until programming to the selected word line is completed, wherein the peripheral circuitry performs a first program loop of the program loops by: applying a first program pulse to the selected word line for a first portion of the apply operation, applying a second program pulse to the selected word line for a second portion of the apply operation, from the start of the set operation, setting a first group of bit lines to a first voltage level and a second group of bit lines to a second voltage level that is lower than the first voltage level until the end of the first portion of the apply operation, and resetting the first group of bit lines and the second group of bit lines to the second voltage level for the second portion of the apply operation.

2. The non-volatile memory device of claim 1, wherein a voltage level of the second program pulse is lower than a voltage level of the first program pulse.

3. The non-volatile memory device of claim 2, wherein the peripheral circuitry performs subsequent program loops of the first program loop by applying, in an apply operation included in the subsequent program loops, a third program pulse that has a voltage level higher than the voltage level of the second program pulse.

4. The non-volatile memory device of claim 3, wherein a voltage level of the third program pulse is lower than the voltage level of the first program pulse.

5. The non-volatile memory device of claim 1, wherein a voltage level of the first program pulse is the same as a voltage level of the second program pulse, and wherein the peripheral circuitry repeatedly performs the program loops by performing the apply operation for longer in the first program loop than in subsequent program loops of the first program loop.

6. The non-volatile memory device of claim 5, wherein the peripheral circuitry further repeatedly performs the program loops by applying, in an apply operation included in the subsequent program loops, a third program pulse that has a voltage level equal to or higher than a voltage level of each of the first program pulse and the second program pulse.

7. The non-volatile memory device of claim 1, wherein the first voltage level is a power supply voltage level and the second voltage level is a ground voltage level.

8. The non-volatile memory device of claim 1, wherein the first voltage level is a reference voltage level that is lower than a power supply voltage level and higher than a ground voltage level, and the second voltage level is the ground voltage level.

9. A method of operating a non-volatile memory device, the method comprising: ​ repeatedly performing a program loop until programming of a selected word line is completed, each program loop including a program operation and a verify operation, the program operation including a set operation to a plurality of bit lines and an apply operation to apply a program pulse to the selected word line, and the verify operation including applying a verify voltage to the selected word line, wherein the repeatedly performing includes performing a first program loop of the program loops by: applying a first program pulse to the selected word line for a first portion of the apply operation, applying a second program pulse to the selected word line for a second portion of the apply operation, from the start of the set operation, setting a first bit line group to a first voltage level and a second bit line group to a second voltage level lower than the first voltage level until the end of the first portion of the apply operation, and resetting the first bit line group and the second bit line group to the second voltage level for the second portion of the apply operation.

10. The operating method of claim 9, wherein a voltage level of the second program pulse is lower than a voltage level of the first program pulse.

11. The operating method of claim 10, wherein the repeatedly performing further comprises: the subsequent program loop is performed by including, in an apply operation included in the subsequent program loop of the first program loop, a third program pulse having a voltage level higher than the voltage level of the second program pulse.

12. The operating method of claim 11, wherein a voltage level of the third program pulse is lower than the voltage level of the first program pulse.

13. The operating method of claim 9, wherein the voltage level of the first program pulse is the same as a voltage level of the second program pulse, and wherein the program loop is repeatedly performed by performing the apply operation for longer in the first program loop than in a subsequent program loop of the first program loop.

14. The operating method of claim 13, wherein the program loop is further repeatedly performed by including, in an apply operation included in the subsequent program loop, a third program pulse having a voltage level equal to or higher than the voltage level of each of the first program pulse and the second program pulse.

15. The operating method of claim 9, wherein the first voltage level is a power supply voltage level and the second voltage level is a ground voltage level.

16. The operating method of claim 9, wherein the first voltage level is a reference voltage level lower than a power supply voltage level and higher than a ground voltage level, and the second voltage level is the ground voltage level.

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