A method for manufacturing a high-voltage fast-recovery diode

Abstract

The application discloses a preparation method of a high-voltage fast recovery diode, and the technical scheme comprises the following steps: S1, selecting an N-Sub substrate; S2, growing a layer of thick oxide layer on the front surface of the wafer; S3, anode photolithography and wet etching of the wafer, first B ion implantation, first annealing treatment, second B ion implantation, and second annealing treatment; S4, growing TEOS on the anode P region and terminal ring region of the wafer and performing reflow; S5, anode photolithography and wet etching of the wafer; S6, depositing metal aluminum on the front surface of the wafer to form an anode electrode; S7, depositing and solidifying polyimide on the front surface of the wafer, and performing photolithography and wet etching; S8, performing N+ implantation on the back surface of the wafer after thinning treatment, and performing vacuum activation; and S9, growing a back electrode of the wafer, and the application has the advantages that the life control method is successfully avoided to cause the forward conduction voltage drop of the diode to increase on the basis of guaranteeing sufficient reverse withstand voltage and reverse recovery time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor preparation, and particularly relates to a preparation method of a high-voltage fast recovery diode. BACKGROUND

[0002] Fast recovery diode is widely used in electronic circuits as one of the most commonly used basic elements. Short reverse recovery time, high breakdown voltage, low reverse cut-off current, soft recovery characteristics and low forward on-voltage are important requirements for fast recovery diodes. In recent years, the switching speed of semiconductor power devices has been rapidly improved, and the reverse recovery speed of diodes connected in parallel with the semiconductor power devices has been increasingly required.

[0003] At present, there is a PIN diode as shown in Figure 1 which is composed of anode P region, base region N- region and cathode N+ region. When forward conducting, a large number of carriers from P+ region and N+ region are stored in N- region, the carriers injected into N- region form excess carriers, a high conductance modulation effect occurs, the resistance of N- region is reduced, and thus the forward on-voltage of the fast recovery diode is reduced. When a reverse bias is applied, under the action of an external electric field, the carriers in N- region are extracted to form a depletion region, and the diode is converted into a reverse blocking state. It takes a certain time to extract the carriers from N- region in reverse direction, and this process which will affect the turn-off speed of the diode is called reverse recovery of the diode, and the time required during the process is the reverse recovery time. The reverse recovery characteristics of the diode are as shown in Figure 2 . The shorter the reverse recovery time, the higher the working frequency of the diode, and the lower the energy consumption. The reverse recovery time t rr is the sum of the storage time t a and the falling time t b , that is, t rr =t a +t b . The total charge amount extracted or recombined from N- region during the reverse recovery period is called reverse recovery charge Qrr. The ratio of t b to t a is called softness factor S, and the greater S is, the better the reverse recovery softness is, the device can effectively avoid voltage overshoot and oscillation caused by hard recovery, and has better stability and reliability.

[0004] At present, in order to improve the reverse recovery speed of the diode, three methods are commonly used, which are heavy metal doping method, electron irradiation method and local method. However, the following problems are encountered:

[0005] 1. Heavy metal doping typically involves adding heavy metals such as platinum or gold to the diode. The heavy metal diffuses into the device as substitutional or interstitial atomic defects. These defects act as recombination centers, accelerating carrier recombination and thus improving the device's reverse recovery. However, heavy metal doping can seriously contaminate the device and production equipment. Furthermore, the defects formed by doping typically exhibit a U-shaped distribution, concentrating on the device surface and affecting the ohmic contact. This increases the forward voltage drop and reverse cutoff current, significantly negatively impacting device performance.

[0006] 2. Electron irradiation is a method of bombarding semiconductors with high-energy electron beams, causing electrons to enter the semiconductor and collide with silicon atoms to form defects. These defects can act as recombination centers to control the minority carrier lifetime, thereby reducing the reverse recovery time of the diode. The advantage of electron irradiation is that the operation is flexible and simple, but the disadvantage of this method is that the defects generated by electron irradiation will attenuate or even decrease, making it extremely unstable. In addition, compared with the traditional platinum diffusion process, the device generates greater leakage and has poor high-temperature characteristics. These factors make the promotion of this technology difficult.

[0007] 3. Local lifetime control technology refers to the H + or He 2+ This type of light-ion irradiation-induced defects act as recombination centers, reducing minority carrier lifetimes. This type of hydrogen ion irradiation has attracted widespread attention due to its ability to achieve localized lifetime control. However, a single light-ion irradiation exposure can only produce a recombination center region of fixed width within the device. To achieve a distribution of recombination centers of any concentration, the device must be irradiated multiple times. This significantly increases device cost and reduces production efficiency, making it impractical for large-scale application. Summary of the Invention

[0008] In view of the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a method for preparing a high-voltage fast recovery diode. The advantage of the present invention is that it successfully avoids the shortcomings of the lifetime control method that lead to increased forward conduction voltage drop, increased reverse leakage and poor high-temperature characteristics of the diode on the basis of ensuring sufficient reverse withstand voltage and reverse recovery time. It has no unnecessary parasitic steps and technical difficulties, is efficient and convenient, and is suitable for wide promotion and application.

[0009] The above technical objectives of the present invention are achieved through the following technical solutions:

[0010] A method for preparing a high-voltage fast recovery diode comprises the following steps:

[0011] Step S1: The wafer uses an N-Sub substrate with a resistivity of 80 to 100 ohm-cm.

[0012] Step S2, growing a thick oxide layer on the front side of the wafer;

[0013] Step S3, the anode P region and the terminal Ring region of the wafer are photoetched and wet etched, the first B ion implantation is performed with the ion concentration ranging from 4E13 to 2E15, then the first annealing treatment is performed, the second B ion implantation is performed with the ion concentration ranging from 4E12 to 8E16, and finally the second annealing treatment is performed;

[0014] Step S4, a layer of tetraethoxysilane TEOS is grown on the anode P region and the terminal Ring region of the wafer, and reflow is performed;

[0015] Step S5, the contact hole region of the wafer is photoetched and wet etched;

[0016] Step S6, 4 microns of metal aluminum is deposited on the front surface of the wafer, and photoetching and wet etching are performed to form the anode electrode;

[0017] Step S7, 5 microns of polyimide is deposited and solidified on the front surface of the wafer, and photoetching and wet etching are performed;

[0018] Step S8, the wafer is thinned, the thickness of the substrate after thinning is 70-100 microns, then N+ implantation is performed on the back surface, the implanted ion is P, and then vacuum activation is performed;

[0019] Step S9, the back surface electrode of the wafer is grown.

[0020] Further, in step S2, the thickness of the thick oxide layer ranges from 1.4K to 2.0K nm.

[0021] Further, in the first B ion implantation of step S3, the energy is 70-90 kev.

[0022] Further, in the first annealing treatment of step S3, the annealing temperature is 1000-1200℃, and the holding time is 340-400 min.

[0023] Further, in the first B ion implantation of step S3, the energy is 30-60 kev.

[0024] Further, in the second annealing treatment of step S3, the annealing temperature is 1000-1200℃, and the holding time is 60-90 min.

[0025] Further, in step S4, the thickness of the tetraethoxysilane TEOS is 1.2 knm, the reflow conditions are: reflow temperature 880-1000℃, reflow time 80-120 min, and oxygen and nitrogen are passed.

[0026] Further, in step S8, the implanted ion impurity concentration is controlled to be 2E14-2E16.

[0027] Further, in step S8, the injection energy is controlled at 50-80kev.

[0028] Further, in step S8, the activation temperature is 300-500℃ under vacuum condition for 10-50min.

[0029] In summary, the present application has the following advantages:

[0030] 1. On the basis of ensuring the sufficient reverse voltage of the device, the N-region of the diode is thinned as much as possible to reduce the reverse charge storage of the diode, thereby effectively reducing the reverse recovery time, and at the same time, the lifetime control is not introduced to reduce the lifetime of the minority carrier, so that the minority carrier in the base region has a longer lifetime to increase the carrier recombination time, and the reverse recovery characteristics of the device are softened.

[0031] 2. The anode emission efficiency control technology is used to reduce the anode injection concentration, reduce the anode emission efficiency, reduce the minority carrier concentration near the PN junction, thereby reducing the charge storage, which is more conducive to reducing the reverse recovery time and increasing the reverse recovery softness. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a schematic diagram of the structure of the PIN diode.

[0033] Figure 2 is a schematic diagram of the reverse recovery waveform of the PIN diode.

[0034] Figure 3 is a schematic diagram of the influence of the N-region width on the reverse recovery waveform.

[0035] Figure 4 is a schematic diagram of the influence of the anode injection concentration on the reverse recovery waveform.

[0036] Figure 5 is a schematic diagram of the diode structure in step S1.

[0037] Figure 6 is a schematic diagram of the diode structure in step S2.

[0038] Figure 7 is a schematic diagram of the diode structure in step S3.

[0039] Figure 8 is a schematic diagram of the diode structure in step S4.

[0040] Figure 9 is a schematic diagram of the diode structure in step S5.

[0041] Figure 10 is a schematic diagram of the diode structure in step S6.

[0042] Figure 11is a schematic diagram of the diode structure in step S7.

[0043] Figure 12 is a schematic diagram of the diode structure in step S8. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present application more clear, the device proposed by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more clear according to the following description. It should be noted that the drawings are very simplified and all use non-precise proportions, only to facilitate, clear and assist the purpose of describing the embodiments of the present application. In order to make the purpose, features and advantages of the present application more obvious and easy to understand, please refer to the drawings. It should be noted that the structure, proportion, size and the like shown in the drawings attached to the present specification are only used to cooperate with the content disclosed in the specification, so that those skilled in the art can understand and read, and are not used to limit the conditions of the implementation of the present application, therefore, any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effect and purpose that can be produced by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0045] Example 1

[0046] A preparation method of a high-voltage fast-recovery diode, comprising the following steps:

[0047] Step S1, as shown in Figure 5 , the wafer is selected from N-Sub substrate, and the resistivity of the N-Sub substrate is 80-100 ohm-cm.

[0048] Step S2, as shown in Figure 6 , a layer of thick oxide layer (Oxide) is grown on the front surface of the wafer, and the thick oxide layer is arranged on the N-Sub substrate, and the thickness of the thick oxide layer ranges from 1.4K to 2.0K nm.

[0049] Step S3, as shown in Figure 7 , the anode P region and the terminal Ring region of the wafer are photoetched and wet etched, the first B ion implantation is performed, the ion concentration ranges from 4E13 to 2E15, the energy is 70kev, then the first annealing treatment is performed, the annealing temperature is 1000℃, and the holding time is 340min; then the second B ion implantation is performed, the ion concentration ranges from 4E12 to 8E16, and finally the second annealing treatment is performed, the annealing temperature is 1000℃, and the holding time is 60min.

[0050] Step S4, as shown in Figure 8As shown, a layer of tetraethoxysilane TEOS is grown on the anode P region and terminal ring region of the wafer, with a thickness of 1.2 knm, and reflow is performed, with a reflow temperature of 880-1000℃, a reflow time of 80-120 min, and oxygen and nitrogen gas being passed through.

[0051] As shown, the contact hole region of the wafer is photoetched and wet etched. Figure 9

[0052] As shown, 4 microns of metal aluminum are deposited on the front side of the wafer, and photoetching and wet etching are performed to form an anode electrode. Figure 10

[0053] As shown, 5 microns of polyimide are deposited and solidified on the front side of the wafer, and photoetching and wet etching are performed. Figure 11

[0054] As shown, the wafer is thinned, with the thickness of the substrate after thinning being 70-100 microns, and then N+ implantation is performed on the back side, with the implanted ions being P, the implanted ion impurity concentration being controlled at 2E14-2E16, and the implantation energy being controlled at 30 kev, and then vacuum activation is performed, with the activation temperature being 300℃ under vacuum conditions and the time being 10 min. Figure 12

[0055] As shown, the wafer back side electrode is grown, and the device fabrication is completed.

[0056] The present application reduces the N- region of the diode as much as possible to reduce the reverse charge storage of the diode, thereby effectively reducing the reverse recovery time, and the curve of the influence of the N- region width on the reverse recovery waveform is as shown in Figure 3 .

[0057] The anode emission efficiency control technique is used to reduce the anode implantation concentration, reduce the anode emission efficiency, reduce the minority carrier concentration near the PN junction to reduce the charge storage, and more effectively reduce the reverse recovery time and increase the reverse recovery softness, and the curve of the influence of the anode implantation concentration on the reverse recovery waveform is as shown in Figure 4 .

[0058] Example 2:

[0059] The difference between the steps of the present application and example 1 is that:

[0060] ​​​​Step S3, the anode P region and terminal ring region of the wafer are photoetched and wet etched, first B ion implantation is performed, ion concentration is 4E13-2E15, energy is 80 kev, then first annealing treatment is performed, annealing temperature is 1080 °C, holding time is 350 min; then second B ion implantation is performed, ion concentration is 4E12-8E16, and finally second annealing treatment is performed, annealing temperature is 1100 °C, holding time is 80 min.

[0061] Step S8, wafer thinning treatment is performed, the thickness of the substrate after thinning is 70-100 μm, then N+ implantation is performed on the back surface, the implanted ion is P, the implanted ion impurity concentration is controlled to be 2E14-2E16, and the implantation energy is controlled to be 120 kev, then vacuum activation is performed, the activation temperature under vacuum condition is 420 °C, and the time is 30 min. Figure 12

[0062] Example 3:

[0063] The difference between the example 1 and the example 3 is that:

[0064] Step S3, the anode P region and terminal ring region of the wafer are photoetched and wet etched, first B ion implantation is performed, ion concentration is 4E13-2E15, energy is 90 kev, then first annealing treatment is performed, annealing temperature is 1200 °C, holding time is 400 min; then second B ion implantation is performed, ion concentration is 4E12-8E16, and finally second annealing treatment is performed, annealing temperature is 1200 °C, holding time is 90 min.

[0065] Step S8, wafer thinning treatment is performed, the thickness of the substrate after thinning is 70-100 μm, then N+ implantation is performed on the back surface, the implanted ion is P, the implanted ion impurity concentration is controlled to be 2E14-2E16, and the implantation energy is controlled to be 200 kev, then vacuum activation is performed, the activation temperature under vacuum condition is 500 °C, and the time is 50 min.

[0066]

[0067]

[0068] Diode test:

[0069] The test results are shown in Table 1.

[0070]

[0071] Table 1

[0072] ​​The diode made by the method has a reverse leakage current reduced to 37.5% (test condition: reverse voltage 1250V) and a forward voltage drop reduced to 56% (test condition: forward current 200A) compared with a conventional Pt-extended fast recovery diode of the same type.

[0073] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, however, as long as the combinations of the technical features do not result in contradictions, they should be considered as falling within the scope of the present disclosure.

[0074] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a high-voltage fast recovery diode, characterized in that: The following steps are involved: Step S1: The wafer uses an N-Sub substrate, and the resistivity of the N-Sub substrate is 80-100 ohm-cm; Step S2, a thick oxide layer is grown on the front side of the wafer. The thick oxide layer is disposed on the upper N-Sub substrate. In step S2, the thickness of the thick oxide layer ranges from 1.4K to 2.0K nm. Step S3: Photolithography and wet etching of the anode P region and the terminal ring region of the wafer, performing a first B ion implantation with an ion concentration ranging from 4E13 to 2E15, followed by a first annealing treatment, and then a second B ion implantation with an ion concentration ranging from 4E12 to 8E16, and finally a second annealing treatment; In the first B ion implantation in step S3, the energy is 70-90 keV; Step S4, growing a layer of tetraethoxysilane (TEOS) on the anode P region and the terminal Ring region of the wafer, and reflowing the layer; In step S4, the thickness of tetraethoxysilane TEOS is 1.2 knm, and the reflux conditions are as follows: reflux temperature 880-1000°C, reflux time 80-120 min, and oxygen and nitrogen are passed through; Step S5, photolithography and wet etching of the contact hole region of the wafer; Step S6, depositing 4 microns of aluminum on the front side of the wafer, and performing photolithography and wet etching to form an anode electrode; Step S7, depositing and curing 5 micron polyimide on the front side of the wafer, and performing photolithography and wet etching; Step S8, wafer thinning, after thinning the substrate thickness to 70-100µm, then N+ implantation is performed on the back side, the implanted ions are P, and then vacuum activation is performed; In step S8, the implanted ion impurity concentration is controlled at 2E14~2E16; In step S8, the injection energy is controlled at 50-80 keV; In step S8, the activation temperature is 300-500°C under vacuum conditions and the activation time is 10-50 min; Step S9: growing an electrode on the back side of the wafer.

2. The method for preparing a high-voltage fast recovery diode according to claim 1, wherein: In the first annealing treatment in step S3 , the annealing temperature is 1000-1200° C., and the holding time is 340-400 min.

3. The method for preparing a high-voltage fast recovery diode according to claim 1, wherein: In the second annealing treatment in step S3, the annealing temperature is 1000-1200° C., and the holding time is 60-90 min.

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