Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device with good characteristics. The semiconductor storage device of the embodiments includes a plurality of conductive layers arranged in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge accumulation layer provided between the plurality of conductive layers and the semiconductor layer; a first structure arranged apart from the semiconductor layer in a second direction intersecting the first direction, extending in a third direction intersecting the first and second directions, and facing the plurality of conductive layers; and a plurality of first nitride films covering facing surfaces of the plurality of conductive layers and the first structure and containing nitrogen (N).

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-146058 (filed on September 8, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising a plurality of conductive layers arranged along a first direction, a semiconductor layer extending along the first direction and facing the plurality of conductive layers, and a charge storage layer disposed between the plurality of conductive layers and the semiconductor layer. Summary of the Invention

[0005] The implementation provides a semiconductor memory device with good performance.

[0006] One embodiment of a semiconductor memory device includes: a plurality of conductive layers arranged along a first direction; a semiconductor layer extending along the first direction and facing the plurality of conductive layers; a charge storage layer disposed between the plurality of conductive layers and the semiconductor layer; a first structure disposed spaced apart from the semiconductor layer in a second direction intersecting the first direction, extending along a third direction intersecting the first and second directions and facing the plurality of conductive layers; and a plurality of first nitride films covering the surfaces of the plurality of conductive layers facing the first structure and containing nitrogen (N).

[0007] In addition, the multiple conductive layers may also contain at least one of molybdenum (Mo) and ruthenium (Ru).

[0008] In addition, the plurality of first nitride films may also include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti) and aluminum (Al).

[0009] In addition, the multiple conductive layers and the multiple first nitride films may also commonly include at least one of molybdenum (Mo) and ruthenium (Ru).

[0010] Alternatively, a plurality of second nitride films may be provided, which cover one and the other side of the plurality of conductive layers in the first direction, as well as the side opposite to the semiconductor layer, and contain nitrogen (N).

[0011] In addition, the plurality of second nitride films may also include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti) and aluminum (Al).

[0012] In addition, the multiple conductive layers and the multiple second nitride films may also commonly include at least one of molybdenum (Mo) and ruthenium (Ru).

[0013] In addition, the plurality of first nitride films and the plurality of second nitride films may also commonly include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti) and aluminum (Al).

[0014] Alternatively, it may have a first insulating layer disposed between two adjacent conductive layers in the first direction among a plurality of conductive layers, and a third nitride film covering the first insulating layer and opposite to the first structure and containing nitrogen (N).

[0015] In addition, the third nitride film may also contain at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si) and aluminum (Al).

[0016] Alternatively, a second insulating layer may be provided between multiple conductive layers and semiconductor layers and may include at least one of aluminum (Al), hafnium (Hf), zirconium (Zr) and lanthanum (La).

[0017] In addition, the thickness of the first nitride film can also be greater than the thickness of the second nitride film.

[0018] In addition, the thickness of the first nitride film can be less than that of the second nitride film.

[0019] According to the implementation method, a semiconductor memory device with good characteristics can be provided. Attached Figure Description

[0020] Figure 1 This is a schematic circuit diagram showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0021] Figure 2 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0022] Figure 3 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0023] Figure 4 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0024] Figure 5 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0025] Figures 6 to 20 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device.

[0026] Figure 21 This is a schematic cross-sectional view showing a portion of the semiconductor memory device of a comparative example.

[0027] Figure 22 This is a schematic cross-sectional view used to illustrate a variation of the semiconductor memory device of the first embodiment.

[0028] Figure 23 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0029] Figures 24-28 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device.

[0030] Figure 29 This is a schematic cross-sectional view used to illustrate a variation of the semiconductor memory device.

[0031] Figure 30 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the third embodiment.

[0032] Figure 31 This is a schematic cross-sectional view used to illustrate a variation of the semiconductor memory device.

[0033] Figure 32 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the fourth embodiment.

[0034] Figure 33 This is a schematic cross-sectional view used to illustrate a variation of the semiconductor memory device. Detailed Implementation

[0035] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, regarding multiple embodiments, common parts are labeled with the same symbols, and descriptions may sometimes be omitted.

[0036] Furthermore, in this specification, when referred to as a "semiconductor memory device," it may refer to a memory die, or it may refer to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a component including a host, such as a smartphone, tablet, or personal computer.

[0037] Additionally, in this specification, when it is referred to as the first component being "connected" between the second and third components, it may mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0038] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0039] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond.

[0040] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when a component is referred to as a lower surface or lower end, it refers to the surface or end of that component on the substrate side; when referred to as an upper surface or upper end, it refers to the surface or end of that component on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0041] In addition, when the components, parts, etc. are referred to as “width,” “length,” or “thickness” in this specification, they may refer to the width, length, or thickness of the cross-section when observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0042] [First Implementation]

[0043] Figure 1 This is a schematic circuit diagram showing a portion of the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of the first embodiment includes a memory cell array (MCA) and peripheral circuitry (PC).

[0044] The memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0045] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), and a source-side select transistor (STS). The STD, MCs, and STS are connected in series between the bit line BL and the source line SL. Hereinafter, the STD and STS are sometimes simply referred to as select transistors (STD, STS).

[0046] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. The memory cell MC stores one bit or more bits of data. Furthermore, the gate electrodes of multiple memory cells MC corresponding to a memory string MS are connected to word lines WL. These word lines WL are collectively connected to all memory strings MS in a memory block BLK.

[0047] The select transistor (STD, STS) is a field-effect transistor. The select transistor (STD, STS) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistor (STD, STS). One drain-side select gate line SGD is connected to all memory strings MS in a string assembly SU. One source-side select gate line SGS is connected to all memory strings MS in a memory block BLK.

[0048] The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage, a voltage transmission circuit that transmits the generated operating voltage to the selected bit line BL, word line WL, source line SL, select gate line (SGD, SGS), etc., a sense amplifier module connected to the bit line BL, and a sequencer that controls them.

[0049] Figure 2 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) containing P-type impurities such as boron (B). In the illustrated example, four memory cell array regions R arranged along the X and Y directions are provided on the semiconductor substrate 100. MCA Additionally, in each memory cell array region R MCA It sets up multiple storage blocks (BLKs) arranged along the Y direction.

[0050] Figure 3This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. Figure 3 In the example, the storage block BLK has one side from the Y direction (in Figure 3 From the positive side of the Y direction to the other side of the Y direction (in the middle) Figure 3 Five string components SUa to SUe are set on the negative side of the Y direction. These multiple string components SUa to SUe correspond to the reference. Figure 1 The string assembly SU is described. An inter-string assembly insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string assemblies SU in the Y direction. An inter-block structure ST is provided between two adjacent memory blocks BLK in the Y direction.

[0051] Figure 4 It is Figure 3 The structure shown is a schematic cross-sectional view when viewed along the direction of the arrow, cut along line B-B'. Figure 5 It is Figure 4 The schematic cross-sectional view shown is an enlarged view of region R1.

[0052] like Figure 4 As shown, the memory block BLK includes a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor layers 120 extending along the Z direction, and a plurality of gate insulating layers 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0053] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 contains at least one of molybdenum (Mo), tungsten (W), and ruthenium (Ru). Figure 5 As shown, a nitride film 181 is provided on the side surface of the conductive layer 110 in the Y direction. Furthermore, a multilayer film comprising a nitride film 182 and an insulating layer 134 is provided on the upper and lower surfaces of the conductive layer 110 and on the surface facing the semiconductor layer 120. The configuration of the side surface, upper and lower surfaces, and surface facing the semiconductor layer 120 of these conductive layers 110 will be described below. An insulating layer 101, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged along the Z direction.

[0054] Below the multiple conductive layers 110, such as Figure 4 As shown, semiconductor layers 111, 113, and 112 are disposed in the dielectric insulating layer 101. A portion of the gate insulating layer 130 is disposed between semiconductor layers 111 and 112 and semiconductor layer 120. Semiconductor layer 113 is connected to the lower end of semiconductor layer 120.

[0055] The upper surface of semiconductor layer 113 is connected to semiconductor layer 111, and the lower surface is connected to semiconductor layer 112. Alternatively, a conductive layer 114 can be disposed on the lower surface of semiconductor layer 112. Semiconductor layers 111, 113, 112, and conductive layer 114 serve as the source line SL. Figure 1 ) to perform its function. The source line SL, for example, is used for the memory cell array region R. MCA ( Figure 2 All memory blocks (BLKs) contained herein share common settings. Semiconductor layers 111, 113, and 112 may contain, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Conductive layer 114 may also contain, for example, a conductive layer of a metal such as tungsten (W), tungsten silicide, or other conductive layers.

[0056] One or more of the bottommost conductive layers 110 among the multiple conductive layers 110 serve as the source-side selected gate line (SGS). Figure 1 ) and multiple source-side selection transistors (STS) connected to it. Figure 1 The gate electrode of the ) functions. The conductive layer 110 is electrically independent in each memory block BLK.

[0057] Additionally, multiple conductive layers 110 located above it serve as word lines WL ( Figure 1 ) and multiple storage units MC connected to it Figure 1 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0058] Additionally, one or more conductive layers 110 located above it serve as drain-side selected gate lines (SGD). Figure 1 ) and multiple drain-side selection transistors STD connected thereto. Figure 1 The gate electrode of the multiple conductive layers 110 functions. The width of these multiple conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. In addition, an inter-string insulating layer SHE is disposed between two adjacent conductive layers 110 in the Y direction. These multiple conductive layers 110 are electrically independent in each string assembly SU.

[0059] Semiconductor layer 120, for example Figure 3 As shown, the semiconductor layer 120 is arranged in a specified pattern along the X and Y directions. Additionally, the semiconductor layer 120 is, for example, as shown... Figure 4 As shown, it has a generally cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is disposed in the central part. The outer peripheral surface of the semiconductor layer 120 is surrounded by a plurality of conductive layers 110, and faces the plurality of conductive layers 110. The semiconductor layer 120 serves as a memory string (MS). Figure 1The multiple memory cells MC and the channel regions of the selection transistors (STD, STS) contained in the semiconductor layer 120 function as such. The semiconductor layer 120 is, for example, a semiconductor layer such as polysilicon (Si).

[0060] An impurity region 121 is connected to the upper end of the semiconductor layer 120. The impurity region 121 contains, for example, N-type impurities such as phosphorus (P). The impurity region 121 is connected to the bit line BL via contacts Ch and Vy.

[0061] An impurity region 122 is provided at the lower end of the semiconductor layer 120. The impurity region 122 may contain, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0062] The gate insulating layer 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating layer 130 is, for example, as shown in... Figure 5 As shown, the device comprises a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films made of silicon oxide (SiO2). The charge storage film 132 is, for example, a silicon nitride (Si3N4) film capable of storing charge. The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the Z-direction along the outer peripheral surface of the semiconductor layer 120.

[0063] Furthermore, the gate insulating layer 130 may also have a floating gate, for example, containing polysilicon or other materials with N-type or P-type impurities.

[0064] Inter-block construction ST, for example, Figure 3 and Figure 4 As shown, it extends along the Z and X directions. Additionally, the inter-block structure ST is, for example, as shown... Figure 4 As shown, this is a structure in which multiple insulating layers 101, multiple conductive layers 110, semiconductor layers 111 and 113 are separated in the Y direction to reach semiconductor layer 112. The inter-block structure ST may also include an insulating layer 170 such as silicon oxide (SiO2) and a conductive layer LI such as tungsten (W). The lower end of the conductive layer LI is connected to the semiconductor layer 112.

[0065] [Nitride films 181, 182]

[0066] As mentioned above Figure 5 A nitrogen (N) nitride film 181 is disposed on the side of the conductive layer 110 in the Y direction. The conductive layer 110 separates the nitride film 181 from the inter-block structure ST.

[0067] The nitride film 181 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 181 may include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). The nitride film 181 may also be, for example, molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0068] The multiple conductive layers 110 and the nitride film 181 may also commonly contain at least one of molybdenum (Mo), tungsten (W), and ruthenium (Ru). For example, if the conductive layer 110 contains molybdenum (Mo), the nitride film 181 may contain molybdenum nitride (MoN). For example, if the conductive layer 110 contains tungsten (W), the nitride film 181 may contain tungsten nitride (WN). For example, if the conductive layer 110 contains ruthenium (Ru), the nitride film 181 may contain ruthenium nitride (RuN).

[0069] Additionally, as mentioned above... Figure 5 The conductive layer 110 has a nitrogen (N) nitride film 182 disposed on one side and the other side of the conductive layer 110 in the Z direction, as well as on the side opposite to the semiconductor layer 120.

[0070] The nitride film 182 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 182 comprises at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). For example, the nitride film 182 can also be molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0071] The multiple conductive layers 110 and the nitride film 182 may also commonly contain at least one of molybdenum (Mo), tungsten (W), and ruthenium (Ru). For example, if the conductive layer 110 contains molybdenum (Mo), the nitride film 182 may contain molybdenum nitride (MoN). For example, if the conductive layer 110 contains tungsten (W), the nitride film 182 may contain tungsten nitride (WN). For example, if the conductive layer 110 contains ruthenium (Ru), the nitride film 182 may contain ruthenium nitride (RuN).

[0072] In addition, nitride film 181 and nitride film 182 may also commonly include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si) and aluminum (Al).

[0073] In addition, the film thickness T of the nitride film 181 11It can also be greater than the film thickness T of the nitride film 182. 12 .

[0074] In addition, the film thickness T of the nitride film 181 11 The film thickness T can also be less than that of the nitride film (182). 12 .

[0075] In addition, such as Figure 5 As shown, an insulating layer 134 is disposed between the nitride film 182 and the insulating layer 101, and between the nitride film 182 and the semiconductor layer 120. The insulating layer 134 may also contain at least one of aluminum (Al), hafnium (Hf), zirconium (Zr), and lanthanum (La). For example, the insulating layer 134 may be aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), etc.

[0076] [Manufacturing Method]

[0077] Next, refer to Figures 6 to 20 The manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figures 6 to 14 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 4 The corresponding cross section. Figures 15-20 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 5 The corresponding cross section.

[0078] When manufacturing the semiconductor memory device of the first embodiment, peripheral circuit PC is first formed on the semiconductor substrate 100. Figure 1 Additionally, an insulating layer 101 is formed above the peripheral circuit PC.

[0079] Next, for example, Figure 6 As shown, a conductive layer 114, a semiconductor layer 112, a sacrificial layer 113A (such as silicon oxide), a sacrificial layer 113B (such as silicon nitride), a sacrificial layer 113C (such as silicon oxide), and a semiconductor layer 111 are formed on the insulating layer 101. Furthermore, multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0080] Next, for example, Figure 7As shown, multiple openings MHa are formed at positions corresponding to semiconductor layer 120. The openings MHa extend along the Z direction, penetrating multiple insulating layers 101 and multiple sacrificial layers 110A, semiconductor layer 111, sacrificial layer 113C, sacrificial layer 113B, and sacrificial layer 113A, exposing semiconductor layer 112. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0081] Next, for example, Figure 8 As shown, a gate insulating layer 130, a semiconductor layer 120, and an insulating layer 125 are formed on the upper surface of the uppermost insulating layer 101 and the inner peripheral surface of the opening MHa, forming a columnar structure MH. When forming the gate insulating layer 130, a barrier insulating film 133, a charge storage film 132, and a tunnel insulating film 131 are formed sequentially, for example, by CVD. When forming the semiconductor layer 120, an amorphous silicon film is formed inside the columnar structure MH, for example, by CVD. Furthermore, the crystal structure of this amorphous silicon film is modified, for example, by annealing.

[0082] Next, for example, Figure 9 As shown, a portion of the insulating layer 125 and the semiconductor layer 120 is removed to a position between the upper and lower surfaces of the uppermost insulating layer 101, such as the upper surface of the semiconductor layer 120. This step is performed, for example, by a method such as RIE. Additionally, for example, as... Figure 9 As shown, an impurity region 121 is formed at the upper end of the columnar structure MH. In this step, a semiconductor layer, such as amorphous silicon containing N-type impurities such as phosphorus (P), is formed at the upper end of the columnar structure MH by a method such as CVD.

[0083] Next, for example, Figure 10 As shown, a trench STA' is formed. The trench STA' extends along the Z and X directions, and multiple insulating layers 101 and sacrificial layers 110A are separated in the Y direction to expose the semiconductor layer 111. This step is performed, for example, by a method such as RIE. In addition, an insulating layer 161 of silicon oxide and a semiconductor layer 162 of amorphous silicon are formed on the inner wall of the trench STA' by a method such as CVD.

[0084] Next, for example, Figure 11 As shown, a trench STA is formed. From the bottom surface of the trench STA', the semiconductor layer 162, insulating layer 161, semiconductor layer 111, and sacrificial layers 113C, 113B, and 113A are separated in the Y direction, exposing the semiconductor layer 112. This step is performed, for example, by a re-emulation (RIE) process. Furthermore, the semiconductor layer 162 on the Y-direction side of the trench STA and a portion of the semiconductor layer 112 exposed on the bottom surface are oxidized to form an insulating layer 163 such as silicon oxide. This step is performed, for example, by thermal oxidation.

[0085] Next, for example, Figure 12 As shown, the sacrificial layer 113B is removed via the trench STA, followed by the removal of sacrificial layers 113A and 113C, and a portion of the gate insulating layer 130, to form a cavity CAV1, exposing a portion of the semiconductor layer 120. This step is performed, for example, by a wet etching method.

[0086] Next, for example, Figure 13 As shown, a semiconductor layer 113 is formed at the location of cavity CAV1 via a trench STA. This step is performed, for example, by epitaxial growth. Additionally, the semiconductor layer 162 and insulating layer 161 disposed on the Y-direction side of the trench STA are removed. This step is performed, for example, by wet etching.

[0087] Next, for example, Figure 14 As shown, the sacrificial layer 110A is removed via trench STA to form multiple cavities CAV2. This creates a hollow structure comprising multiple insulating layers 101 arranged along the Z direction and columnar structures MH supporting the insulating layers 101. This step is performed, for example, by a wet etching method.

[0088] Next, for example, Figure 15 As shown, an insulating layer 134 is formed on the inner wall of the cavity CAV2 and the inner wall of the groove STA via the groove STA. This step is performed, for example, by a method such as CVD.

[0089] Next, for example, Figure 16 As shown, a nitride film 182 is formed on the inner wall of the cavity CAV2 via the trench STA. This step is performed, for example, by a method such as CVD. In addition, during this step, a nitride film identical to the nitride film 182 may also be formed on the inner wall of the trench STA, but these nitride films can also be removed, for example, by a process such as RIE.

[0090] Next, for example, Figure 17 As shown, a conductive layer 110' is formed within the cavity CAV2 via a trench STA. The conductive layer 110' comprises, for example, the same material as the conductive layer 110. In this step, a portion of the conductive layer 110' is also formed on the Y-direction side of the trench STA. This step is performed, for example, by a method such as CVD.

[0091] Next, for example, Figure 18 As shown, a portion of the conductive layer 110' isotropically removed via trench STA to form a plurality of conductive layers 110 spaced apart in the Z direction. This step is performed, for example, by fluorine (F)-based dry etching or wet etching. Furthermore, this etching step is performed under etching conditions where the etching rate of the conductive layer 110' is high, while the etching rate of the insulating layer 134 and the nitride film 182 is low.

[0092] Next, for example, Figure 19 As shown, a continuous nitride film 181' in the Z direction is formed on the side surfaces of multiple insulating layers 101 and multiple conductive layers 110 in the Y direction via trench STA. The nitride film 181' includes, for example, elements similar to those shown in the reference diagram. Figure 5 The nitride film 181 described is made of the same material. This step is performed, for example, by a method such as CVD. In addition, before forming the nitride film 181', the side surface of the conductive layer 110 in the Y direction (the surface exposed to the trench STA) can be reduced using hydrogen (H2), or the oxide layer formed on the side surface of the conductive layer 110 in the Y direction can be removed by wet etching or the like.

[0093] Next, for example, Figure 20 As shown, a portion of the nitride film 181' isotropically removed via the trench STA to form a plurality of nitride films 181 spaced apart in the Z direction. This step is performed, for example, by fluorine (F) based dry etching or wet etching.

[0094] Next, an insulating layer 170 and a conductive layer 11 are formed within the trench STA to form an inter-block structure ST, and a contact Ch connecting to the impurity region 121 and an inter-string component insulating layer SHE are formed, thereby forming a reference. Figure 4 The structure described.

[0095] [Comparative Example]

[0096] Next, refer to Figure 21 The comparative example semiconductor memory device will be described. Figure 21 This is a schematic cross-sectional view used to illustrate a comparative example of a semiconductor memory device, showing the relationship with... Figure 5 A considerable cross-section.

[0097] The semiconductor memory device of the comparative example and the semiconductor memory device of the first embodiment ( Figure 5 Unlike other materials, a nitride film 181 is not provided on the surface of the conductive layer 110 opposite to the inter-block structure ST. Furthermore, a nitride film 182 is not provided on one and the other side of the conductive layer 110 in the Z direction, nor on the surface opposite to the semiconductor layer 120. Figure 21 ).

[0098] When manufacturing the comparative example semiconductor memory device, the reference process is not performed. Figure 19 and Figure 20 The steps described.

[0099] When manufacturing this configuration, for example, the following situation exists: Figure 18In the steps following the steps shown, impurities enter the side of the conductive layer 110 exposed in the trench STA' in the Y direction. Examples of such impurities include hydrogen (H), oxygen (O), fluorine (F), and chlorine (Cl). These impurities may be introduced via dotted lines such as Px1 (…). Figure 21 The path shown diffuses in the conductive layer 110, reaching the barrier insulating film 133 and the charge storage film 132.

[0100] Furthermore, when manufacturing this configuration, for example, the following situation exists: Figure 17 In the steps following the steps shown, the impurities described above enter the conductive layer 110. These impurities may be introduced via dotted lines such as Px2 (…). Figure 21 The path shown diffuses in the insulating layer 101 and the conductive layer 110, reaching the barrier insulating film 133 and the charge storage film 132.

[0101] In this case, if the impurities mentioned above are mixed into the barrier insulating film 133 and the charge storage film 132 in a relatively large amount, undesirable impurity energy levels may be formed in the barrier insulating film 133 and the charge storage film 132, which may degrade the data storage characteristics of the memory cell MC or cause channel leakage.

[0102] [Effects of the first embodiment]

[0103] When manufacturing the semiconductor memory device of the first embodiment, referring to Figure 19 and Figure 20 In the described steps, a nitride film 181 is formed on the side surface of the conductive layer 110 in the Y direction. Here, the diffusion coefficient of the impurities described above is relatively small in the nitride film 181. Therefore, when manufacturing the semiconductor memory device of the first embodiment, it is possible to refer to... Figure 20 In the steps following the steps described, impurities as described above are suppressed from entering the side surface of the conductive layer 110 in the Y direction.

[0104] Furthermore, when manufacturing the semiconductor memory device of the first embodiment, referring to Figure 16 In the described steps, a nitride film 182 is formed on the upper and lower surfaces of the covering insulating layer 101 and at the location of the gate insulating layer 130. Here, the diffusion coefficient of the impurities described above is relatively small in the nitride film 182. Therefore, when manufacturing the semiconductor memory device of the first embodiment, it is possible to refer to... Figure 17 In the steps following the steps described, impurities as described above are suppressed from entering the conductive layer 110.

[0105] Therefore, the semiconductor memory device according to the first embodiment can provide a memory cell MC that prevents channel leakage and exhibits good data retention characteristics.

[0106] [Examples of variations of the first embodiment]

[0107] Next, refer to Figure 22 A variation of the semiconductor memory device of the first embodiment will be described. Figure 22 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device of this variation.

[0108] [Nitride film 183]

[0109] For example, Figure 22 As shown, in the semiconductor memory device of the variation of the first embodiment, the nitride film 181 as in the first embodiment is not provided. Figure 5 However, in the semiconductor memory device of the variation of the first embodiment, a continuous nitride film 183 in the Z direction is provided on the side surfaces (opposite to the inter-block structure ST) of the plurality of insulating layers 101 and the plurality of conductive layers 110 in the Y direction. The nitride film 183 contains nitrogen (N).

[0110] The nitride film 183 includes multiple regions 183w corresponding to multiple conductive layers 110 and multiple regions 183s corresponding to multiple insulating layers 101. Region 183w covers the side surface of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST). Region 183s covers the side surface of the insulating layer 101 in the Y direction (opposite to the inter-block structure ST).

[0111] The nitride film 183 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 183 may include at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). The nitride film 183 may also be, for example, molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0112] [Manufacturing Method]

[0113] The semiconductor memory device of the variation of the first embodiment is manufactured in essentially the same manner as the semiconductor memory device of the first embodiment. However, in the manufacturing method of the semiconductor memory device of this variation, the same procedures as those in the reference embodiment are not followed. Figure 20 The steps described correspond to the steps of isotropically removing a portion of the nitride film 181' to form a plurality of nitride films 181 spaced apart in the Z direction. In the semiconductor memory device manufacturing method of this variation, a continuous nitride film 183 in the Z direction is formed by leaving a nitride film on the side of the insulating layer 101 in the Y direction.

[0114] [Second Implementation]

[0115] Next, refer to Figure 23 The semiconductor memory device of the second embodiment will be described. Figure 23 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the second embodiment.

[0116] [Nitride film 201]

[0117] The semiconductor memory device of the second embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment, as... Figure 23 As shown, a nitrogen (N) nitride film 201 is provided on the side of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST), instead of a nitrogen (N) nitride film 181. Figure 5 ).

[0118] The nitride film 201 is a conductive film. The nitride film 201 may contain, for example, titanium (Ti). For example, the nitride film 201 may also be titanium nitride (TiN).

[0119] In addition, such as Figure 23 As shown, in the semiconductor memory device of the second embodiment, a nitrogen (N) nitride film 202 is provided on one side and the other side of the conductive layer 110 in the Z direction, and on the side opposite to the semiconductor layer 120.

[0120] The nitride film 202 is a conductive film. The nitride film 202 includes, for example, titanium (Ti). For example, the nitride film 202 can also be titanium nitride (TiN) or the like.

[0121] In addition, nitride film 201 and nitride film 202 may also contain titanium (Ti) or the like.

[0122] In addition, the film thickness T of the nitride film 201 21 It can also be greater than the film thickness T of the nitride film 202. 22 .

[0123] In addition, the film thickness T of the nitride film 201 21 It can also be less than the film thickness T of the nitride film 202. 22 .

[0124] [Manufacturing Method]

[0125] Next, refer to Figures 24-28 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 24-28 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 23 The corresponding cross section.

[0126] The semiconductor memory device of the second embodiment is manufactured in essentially the same manner as the semiconductor memory device of the first embodiment. However, in the manufacturing method of the semiconductor memory device of the second embodiment, in relation to... Figure 16 In the corresponding steps, such as Figure 24 As shown, a nitride film 202' is formed instead of a nitride film 182. The nitride film 202' contains the same material as the nitride film 202. This step is performed, for example, by a method such as CVD. Furthermore, in this step, a nitride film identical to the nitride film 202' may also be formed on the inner wall of the trench STA, but these nitride films can also be removed, for example, by a process such as RIE.

[0127] Next, for example, Figure 25 As shown, a conductive layer 110' is formed within the cavity CAV2 via a trench STA. This step is performed, for example, by a method such as CVD.

[0128] Next, for example, Figure 26 As shown, a portion of the conductive layer 110' and the nitride film 202' isotropically removed via trench STA to form a plurality of conductive layers 110 and a plurality of nitride films 202 spaced apart in the Z direction. This step is performed, for example, by fluorine (F)-based dry etching or wet etching. Furthermore, this etching step is performed under etching conditions where the etching rate of the conductive layer 110' and the nitride film 202' is high, while the etching rate of the insulating layer 134 is slow.

[0129] Next, for example, Figure 27 As shown, a continuous nitride film 201' in the Z direction is formed on the side surfaces of multiple insulating layers 101 and multiple conductive layers 110 in the Y direction via trench STA. The nitride film 201' includes, for example, elements similar to those shown in the reference diagram. Figure 23 The nitride film 201 described is made of the same material. This step is performed, for example, by a method such as CVD. Furthermore, before forming the nitride film 201', a reference can be made to the side surface of the conductive layer 110 in the Y direction. Figure 19 The described restoration process, etc.

[0130] Next, for example, Figure 28 As shown, a portion of the nitride film 201' isotropically removed via the trench STA to form a plurality of nitride films 201 spaced apart in the Z direction. This step is performed, for example, by fluorine (F) based dry etching or wet etching.

[0131] [Effects of the second implementation method]

[0132] The semiconductor memory device according to the second embodiment, like the semiconductor memory device according to the first embodiment, is able to provide a memory cell MC that prevents channel leakage and exhibits good data retention characteristics.

[0133] Furthermore, in this embodiment, conductive nitride films 202 are provided on the upper and lower surfaces of the conductive layer 110. With this configuration, the nitride film 202 can function as part of the word line WL, thereby reducing the actual resistance of the word line WL. This results in a memory cell MC with excellent characteristics.

[0134] [Example of a variation of the second embodiment]

[0135] Next, refer to Figure 29 A variation of the semiconductor memory device of the second embodiment will be described. Figure 29 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device of this variation.

[0136] [Nitride 203]

[0137] For example, Figure 29 As shown, the semiconductor memory device of the variation of the second embodiment includes a nitride film 203 covering the side surface (opposite to the inter-block structure ST) in the Y direction of a plurality of insulating layers 101 and a plurality of conductive layers 110. The nitride film 203 is continuous in the Z direction. In addition, the nitride film 203 contains nitrogen (N).

[0138] The nitride film 203 includes multiple regions 203w corresponding to multiple conductive layers 110 and multiple regions 203s corresponding to multiple insulating layers 101. Regions 203w are separated from the nitride film 201 and cover the side surface of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST). Regions 203s cover the side surface of the insulating layer 101 in the Y direction (opposite to the inter-block structure ST).

[0139] The nitride film 203 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 203 may contain at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). The nitride film 203 may also be, for example, molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0140] [Manufacturing Method]

[0141] The semiconductor memory device of the variation of the second embodiment is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, in the manufacturing method of the semiconductor memory device of this variation, in relation to... Figure 28The corresponding step, namely the step of forming multiple nitride films 201 spaced apart in the Z direction, is to form nitride films 203 on the sides of the multiple insulating layers 101 and the multiple nitride films 201 in the Y direction via trench STA by CVD or the like.

[0142] [Third Implementation]

[0143] Next, refer to Figure 30 The semiconductor memory device of the third embodiment will be described. Figure 30 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the third embodiment.

[0144] [Nitride film 301]

[0145] The semiconductor memory device of the third embodiment is configured in essentially the same way as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of the third embodiment, as... Figure 30 As shown, a nitrogen (N) nitride film 301 is provided on the side of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST), instead of a nitrogen (N) nitride film 201. Figure 23 ).

[0146] The nitride film 301 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 301 may contain at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). For example, the nitride film 301 may also be molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0147] The multiple conductive layers 110 and the nitride film 301 may also commonly contain at least one of molybdenum (Mo), tungsten (W), and ruthenium (Ru). For example, if the conductive layer 110 contains molybdenum (Mo), the nitride film 301 may contain molybdenum nitride (MoN). For example, if the conductive layer 110 contains tungsten (W), the nitride film 301 may contain tungsten nitride (WN). For example, if the conductive layer 110 contains ruthenium (Ru), the nitride film 301 may contain ruthenium nitride (RuN). Additionally, as... Figure 30 As shown, a nitrogen (N) nitride film 302 is provided on the upper and lower surfaces of the conductive layer 110 and on the surface opposite to the semiconductor layer 120.

[0148] The nitride film 302 is a conductive film. The nitride film 302 may contain, for example, titanium (Ti). The nitride film 302 may also be, for example, titanium nitride (TiN).

[0149] In addition, the film thickness T of the nitride film 30131 It can also be greater than the film thickness T of the 302 nitride film. 32 .

[0150] In addition, the film thickness T of the nitride film 301 31 It can also be less than the film thickness T of the 302 nitride film. 32 .

[0151] [Manufacturing Method]

[0152] The semiconductor memory device of the third embodiment is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, in the manufacturing method of the semiconductor memory device of this embodiment, in relation to... Figure 27 and Figure 28 In the corresponding steps, nitride film 301 is formed instead of nitride film 201.

[0153] [Example of a variation of the third embodiment]

[0154] Next, refer to Figure 31 A variation of the semiconductor memory device in the third embodiment will be described. Figure 31 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device of this variation.

[0155] [Nitride film 303]

[0156] For example, Figure 31 As shown, the semiconductor memory device of the variation of the third embodiment does not include the nitride film 301. However, the semiconductor memory device of the variation of the third embodiment includes a nitride film 303 disposed on the side surfaces (opposite to the inter-block structure ST) in the Y direction of the plurality of insulating layers 101 and the plurality of conductive layers 110. The nitride film 303 is continuous in the Z direction. Furthermore, the nitride film 303 contains nitrogen (N).

[0157] The nitride film 303 includes multiple regions 303w corresponding to multiple conductive layers 110 and multiple regions 303s corresponding to multiple insulating layers 101. Regions 303w cover the side surface of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST). Regions 303s cover the side surface of the insulating layer 101 in the Y direction (opposite to the inter-block structure ST).

[0158] The nitride film 303 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 303 may contain at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). The nitride film 303 may also be, for example, molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0159] [Manufacturing Method]

[0160] The semiconductor memory device of the third embodiment is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, in the manufacturing method of the semiconductor memory device of this embodiment, in relation to... Figure 27 In the corresponding steps, nitride film 303 is formed instead of nitride film 201'. Furthermore, the steps described in the reference are not performed. Figure 28 The steps described are the steps of isotropically removing a portion of the nitride film to form a plurality of nitride films 201 spaced apart in the Z direction.

[0161] [Fourth Implementation]

[0162] Next, refer to Figure 32 The semiconductor memory device of the fourth embodiment will be described. Figure 32 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the fourth embodiment.

[0163] The semiconductor memory device of the fourth embodiment is constructed in essentially the same manner as the semiconductor memory devices of the first to third embodiments. However, unlike the semiconductor memory devices of the first to third embodiments, the semiconductor memory device of the fourth embodiment does not have a nitrogen (N) nitride film provided on the upper and lower surfaces of the conductive layer 110 and opposite to the semiconductor layer 120. In the semiconductor memory device of the fourth embodiment, as... Figure 32 As shown, a nitrogen (N) nitride film 401 is provided on the side of the conductive layer 110 in the Y direction (opposite to the inter-block structure ST).

[0164] The nitride film 401 is a conductive film. The nitride film 401 may contain, for example, titanium (Ti). The nitride film 401 may also be, for example, titanium nitride (TiN).

[0165] [Manufacturing Method]

[0166] The semiconductor memory device of the fourth embodiment is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, in the manufacturing method of the semiconductor memory device of the fourth embodiment, in relation to... Figure 24In the corresponding steps, the nitride film 202' is not formed. Furthermore, in the semiconductor memory device manufacturing method of the fourth embodiment, in conjunction with... Figure 27 and Figure 28 In the corresponding steps, nitride film 401 is formed instead of nitride film 201.

[0167] [Example of a variation of the fourth embodiment]

[0168] Next, refer to Figure 33 A variation of the semiconductor memory device in the fourth embodiment will be described. Figure 33 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device of this variation.

[0169] For example, Figure 33 As shown, the semiconductor memory device of the variation of the fourth embodiment does not include the nitride film 401, but instead includes the nitride film 403.

[0170] The nitride film 403 is either an insulating film or a conductive film exhibiting high resistance. The nitride film 403 may contain at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al). The nitride film 403 may also be, for example, molybdenum nitride (MoN), ruthenium nitride (RuN), tungsten nitride (WN), silicon nitride (SiN), and aluminum nitride (AlN). For example, molybdenum nitride (MoN), ruthenium nitride (RuN), and tungsten nitride (WN) are commonly used as conductive films exhibiting high resistance.

[0171] The multiple conductive layers 110 and the nitride film 403 may also commonly contain at least one of molybdenum (Mo), tungsten (W), and ruthenium (Ru). For example, if the conductive layer 110 contains molybdenum (Mo), the nitride film 403 may contain molybdenum nitride (MoN). For example, if the conductive layer 110 contains tungsten (W), the nitride film 403 may contain tungsten nitride (WN). For example, if the conductive layer 110 contains ruthenium (Ru), the nitride film 403 may contain ruthenium nitride (RuN).

[0172] [other]

[0173] In the manufacturing methods of the semiconductor memory device in the first and third embodiments, for example in Figure 19 In the steps shown or the corresponding steps, a nitride film 181 is formed on the side surface of the conductive layer 110 in the Y direction. Figure 5 ) and nitride film 301 ( Figure 30 However, nitride film 181 and nitride film 301 can also be formed through another manufacturing step. For example, it can be formed by... Figure 18After the steps shown, a nitride film 181 and a nitride film 301 are formed by thermally nitriding the side surface (the surface exposed to the trench STA) in the Y direction of the conductive layer 110 under a high-temperature nitrogen atmosphere.

[0174] Thus, when nitride films 181 and 301 are formed by thermal nitriding, for example, if the conductive layer 110 contains molybdenum (Mo), nitride films 181 and 301 may contain molybdenum nitride (MoN). Alternatively, for example, if the conductive layer 110 contains tungsten (W), nitride films 181 and 301 may contain tungsten nitride (WN). Furthermore, for example, if the conductive layer 110 contains ruthenium (Ru), nitride films 181 and 301 may contain ruthenium nitride (RuN).

[0175] In the case where a nitride film 181 is formed by thermal nitriding, the film thickness T of the nitride film 181 is... 11 The film thickness T can be less than 182 of the nitride film. 12 Furthermore, when the nitride film 301 is formed by thermal nitriding, the film thickness T of the nitride film 301 is... 31 The film thickness T can be less than that of the 302 nitride film. 32 .

[0176] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as set forth in the claims and its equivalents.

[0177] [Explanation of Symbols]

[0178] BLK storage block

[0179] SU string component

[0180] 110 conductive layer

[0181] 120 Semiconductor Layer

[0182] 130 gate insulating film

[0183] 181 Nitride film

[0184] 182 Nitrided film.

Claims

1. A semiconductor memory device comprising: Multiple conductive layers are arranged along the first direction; A semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the semiconductor layer; The first configuration is arranged at a distance from the semiconductor layer in a second direction intersecting the first direction, extends along a third direction intersecting the first and second directions, and faces the plurality of conductive layers; A plurality of first nitride films cover the opposing surfaces of the plurality of conductive layers to the first configuration and contain nitrogen (N); The first insulating layer is disposed between two adjacent conductive layers in the first direction among the plurality of conductive layers; as well as The third nitride film covers the opposing surface of the first insulating layer to the first structure and contains nitrogen (N).

2. The semiconductor memory device according to claim 1, wherein The plurality of conductive layers comprise at least one of molybdenum (Mo) and ruthenium (Ru).

3. The semiconductor memory device according to claim 1 or 2, wherein The plurality of first nitride films comprise at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti), and aluminum (Al).

4. The semiconductor memory device according to claim 1 or 2, wherein The plurality of conductive layers and the plurality of first nitride films collectively comprise at least one of molybdenum (Mo) and ruthenium (Ru).

5. The semiconductor memory device according to claim 1 or 2, The device comprises a plurality of second nitride films, which cover one and the other side of the plurality of conductive layers in the first direction, as well as the side opposite to the semiconductor layer, and contain nitrogen (N).

6. The semiconductor memory device according to claim 5, wherein The plurality of second nitride films comprise at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti), and aluminum (Al).

7. The semiconductor memory device according to claim 5, wherein The plurality of conductive layers and the plurality of second nitride films collectively comprise at least one of molybdenum (Mo) and ruthenium (Ru).

8. The semiconductor memory device according to claim 5, wherein The plurality of first nitride films and the plurality of second nitride films collectively comprise at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), titanium (Ti), and aluminum (Al).

9. The semiconductor memory device according to claim 1 or 2, wherein The third nitride film contains at least one of molybdenum (Mo), ruthenium (Ru), tungsten (W), silicon (Si), and aluminum (Al).

10. The semiconductor memory device according to claim 1 or 2, The device comprises a second insulating layer disposed between the plurality of conductive layers and the semiconductor layer and comprising at least one of aluminum (Al), hafnium (Hf), zirconium (Zr) and lanthanum (La).

11. The semiconductor memory device according to claim 5, wherein The thickness of the first nitride film is greater than the thickness of the second nitride film.

12. The semiconductor memory device according to claim 5, wherein The thickness of the first nitride film is less than the thickness of the second nitride film.

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