SiC-based vdmosfet device resistant to single event gate damage
By splitting the gate oxide layer and introducing Schottky contacts and a P+ protected zone in SiC-based VDMOSFET devices, the gate damage problem caused by single-event effects was solved, and the device's single-event resistance was improved.
Patent Information
- Application Number
- CN202211356503.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-01
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2042-11-01
AI Technical Summary
Traditional SiC-based VDMOSFET devices are susceptible to gate damage caused by single-event effects under space irradiation. Especially when the source-drain voltage is less than 50% of the rated voltage, single-event incident can lead to current surge, temperature runaway, and single-event burnout.
The gate oxide layer is split into two parts, a Schottky contact is introduced and a P+ protection zone is added. The strong electric field is suppressed by the transverse electric field between the P+ protection zone and the P-type base region, providing an additional hole discharge path. Excess holes are quickly extracted using the Schottky contact.
It effectively reduces damage to the gate oxide layer after single-particle incident, lowers the risk of device failure, and maintains the normal operating state of the device.
Smart Images
Figure CN115799334B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a SiC-based VDMOSFET device resistant to single-particle gate damage. BACKGROUND
[0002] Silicon carbide is more suitable for high-voltage, high-power, radiation-resistant fields due to its greater band gap, stronger breakdown field and higher thermal conductivity. Compared with traditional MOSFETs, the most significant feature of VDMOSFET (vertical double-diffused MOSFET) is that the drain and source are respectively made on the two sides of the chip, thereby forming a vertical conduction channel, and the requirement for high power is met through the structure of multiple cells in parallel. Therefore, the device is often used in the field of aerospace power supply manufacturing, but the single-particle effect caused by space radiation is one of the key factors affecting the normal operation of the device.
[0003] Single-particle effect refers to the problem of local strong electric field, large current and high temperature caused by the incidence of a single particle to a device, which affects the normal working state of the device and even causes the device to fail. Among them, single-particle burnout effect is a representative irreversible single-particle effect. When the device is in a blocking state with a source-drain voltage less than 50% of the rated voltage, the incidence of a single particle will cause the device to have a single-particle burnout phenomenon of rising current and out-of-control temperature. SUMMARY
[0004] In order to solve the above problems existing in the prior art, the application provides a SiC-based VDMOSFET device resistant to single-particle gate damage. The technical problem to be solved by the application is solved through the following technical scheme:
[0005] The application provides a SiC-based VDMOSFET device resistant to single-particle gate damage, which comprises a substrate, a drain below the substrate, and an N-drift region above the substrate, wherein,
[0006] The upper surface of the N-drift region is ion implanted to form a first P+ ohmic contact region and a second P+ ohmic contact region on both sides, respectively, the N-drift region inside the first P+ ohmic contact region is ion implanted to form a first P-type base region, and the N-drift region inside the second P+ ohmic contact region is ion implanted to form a second P-type base region; the upper surface of the first P-type base region is ion implanted to form a first N+ source region, and the upper surface of the second P-type base region is ion implanted to form a second N+ source region;
[0007] The upper surface of the first P+ ohmic contact region is provided with a first source electrode extending from the upper surface of the first P+ ohmic contact region to the upper surface of the first N+ source region; the upper surface of the second P+ ohmic contact region is provided with a second source electrode extending from the upper surface of the second P+ ohmic contact region to the upper surface of the second N+ source region; a P+ protection region is formed in the upper surface of the N- drift region by ion implantation, and the upper surface of the P+ protection region is provided with a P+ protection region electrode; the two sides of the P+ protection region electrode are respectively provided with a third source electrode and a fourth source electrode, and the lower surfaces of the third source electrode and the fourth source electrode form Schottky contact with the upper surface of the N- drift region.
[0008] A first gate dielectric layer and a first gate electrode are stacked between the first source electrode and the third source electrode, and the lower surface of the first gate dielectric layer is in contact with the first N- drift region, the first P-type base region and the first N+ source region at the same time; a second gate dielectric layer and a second gate electrode are stacked between the second source electrode and the fourth source electrode, and the lower surface of the second gate dielectric layer is in contact with the first N- drift region, the second P-type base region and the second N+ source region at the same time.
[0009] In an embodiment of the present application, the inner surface of the first P+ ohmic contact region is in contact with the outer surface of the first P-type base region, and the inner surface of the second P+ ohmic contact region is in contact with the outer surface of the second P-type base region.
[0010] In an embodiment of the present application, the inner surface of the first P+ ohmic contact region is in contact with the outer surface of the first N+ source region, and the inner surface of the second P+ ohmic contact region is in contact with the outer surface of the second N+ source region.
[0011] In an embodiment of the present application, the first source electrode forms ohmic contact with the interfaces of the first P+ ohmic contact region and the first N+ source region respectively, and the second source electrode forms ohmic contact with the interfaces of the second P+ ohmic contact region and the second N+ source region respectively.
[0012] In an embodiment of the present application, the P+ protection region has the same width as the P+ protection region electrode, and the two sides of the P+ protection region electrode are in contact with the third source electrode and the fourth source electrode respectively.
[0013] In an embodiment of the present application, the P+ protection region has the same implantation depth and doping concentration as the first P+ ohmic contact region and the second P+ ohmic contact region.
[0014] In an embodiment of the present application, the material of the P+ protection region electrode is Ni.
[0015] In one embodiment of the present invention, the two sides of the first gate dielectric layer are respectively spaced apart from the first source and the third source; the two sides of the second gate dielectric layer are respectively spaced apart from the second source and the fourth source.
[0016] In one embodiment of the present invention, the substrate material is N-type SiC, phosphorus-doped, with a doping concentration of 5*10⁻⁶. 18 -1*10 19 cm -3 .
[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0018] In traditional VDMOSFETs, the gate oxide layer covers the entire JFET region, which is damaged by the accumulation of holes caused by single-particle incident. The SiC-based VDMOSFET device of this invention splits the gate oxide layer, removes the central gate oxide in the neck region (the region between two p-type base regions), introduces a Schottky contact, and adds a P+ protection zone. This has the following advantages: (1) Since the implantation depth and doping concentration of the P+ protection zone are consistent with those of the P+ ohmic contact region, it is formed simultaneously with the P+ ohmic contact region, without the need for additional photolithography and ion implantation processes, and does not increase the process complexity; (2) After single-particle incident, the incident track will generate a large number of electron-hole pairs, and a large number of holes will accumulate at the interface between the gate oxide and the drift region under the action of voltage bias. Therefore, the Schottky contact is introduced so that holes can be discharged not only through the first and second sources, but also through the third and fourth sources, providing an additional discharge path for excess holes. Accumulated holes can be quickly extracted, thereby effectively reducing the strong additional gate oxide electric field caused by the accumulation of excess holes; (3) The P+ protection zone is close to the P-type base region. When the blocking voltage is high, the depletion region is connected to form a transverse electric field, which can effectively suppress the reverse leakage current of the Schottky junction and the strong electric field in the gate oxide on both sides.
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of a SiC-based VDMOSFET device resistant to single-particle gate damage provided in an embodiment of the present invention;
[0021] Figure 2 This is a top view schematic diagram of a SiC-based VDMOSFET device resistant to single-particle gate damage provided in an embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram illustrating the working principle of a SiC-based VDMOSFET device resistant to single-particle gate damage provided in an embodiment of the present invention.
[0023] Explanation of reference numerals in the attached figures:
[0024] 1-Substrate; 2-Drain; 3-N-Drift region; 4-First P+ Ohmic contact region; 5-Second P+ Ohmic contact region; 6-First P-type base region; 7-Second P-type base region; 8-First N+ source region; 9-Second N+ source region; 10-First source; 11-Second source; 12-P+ protection zone; 13-P+ protection zone electrode; 14-Third source; 15-Fourth source; 16-First gate dielectric layer; 17-First gate; 18-Second gate dielectric layer; 19-Second gate. Detailed Implementation
[0025] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a VDMOSFET device resistant to single-particle gate damage according to the present invention, in conjunction with the accompanying drawings and specific embodiments.
[0026] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0027] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.
[0028] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a SiC-based VDMOSFET device resistant to single-event gate damage provided by an embodiment of the present invention. Figure 2 This is a top view schematic diagram of a SiC-based VDMOSFET device resistant to single-event gate damage provided by an embodiment of the present invention. The SiC-based VDMOSFET device includes a substrate 1, a drain 2 located below the substrate 1, and an N-drift region 3 located above the substrate 1. Preferably, the substrate 1 is made of N-type SiC, phosphorus-doped, with a doping concentration of 5*10⁻⁶. 18 -1*1019 cm -3 The drain electrode 2 is made of Ni, and the drain metal forms an ohmic contact with the bottom of the substrate 1. The N-drift region 3 is made of N-type SiC, phosphorus-doped, with a thickness of 10-30 μm and a doping concentration of 3*10⁻⁶. 15 -1*10 16 cm -3 .
[0029] The upper surface of the N-drift region 3 is ion-implanted to form a first P+ ohmic contact region 4 and a second P+ ohmic contact region 5 on both sides. The surface of the N-drift region 3 inside the first P+ ohmic contact region 4 is ion-implanted to form a first P-type base region 6. The surface of the N-drift region 3 inside the second P+ ohmic contact region 5 is ion-implanted to form a second P-type base region 7. The upper surface of the first P-type base region 6 is ion-implanted to form a first N+ source region 8. The upper surface of the second P-type base region 7 is ion-implanted to form a second N+ source region 9.
[0030] In this embodiment, the inner surface of the first P+ ohmic contact region 4 is in contact with the outer surface of the first P-type base region 6, and the inner surface of the second P+ ohmic contact region 5 is in contact with the outer surface of the second P-type base region 7. Further, the inner surface of the first P+ ohmic contact region 4 is in contact with the outer surface of the first N+ source region 8, and the inner surface of the second P+ ohmic contact region 5 is in contact with the outer surface of the second N+ source region 9.
[0031] The first P-type base region 6 is L-shaped, and the first N+ source region 8 is located within the area enclosed by the first P+ ohmic contact region 4 and the first P-type base region 6. The upper surfaces of the first P-type base region 6, the first N+ source region 8, and the first P+ ohmic contact region 4 are all flush. Symmetrically, the second P-type base region 7 is L-shaped, and the second N+ source region 9 is located within the area enclosed by the second P+ ohmic contact region 5 and the second P-type base region 7. The upper surfaces of the second P-type base region 7, the second N+ source region 9, and the second P+ ohmic contact region 5 are all flush.
[0032] Furthermore, a first source 10 is disposed on the upper surface of the first P+ ohmic contact region 4, and the first source 10 extends from the upper surface of the first P+ ohmic contact region 4 to the upper surface of the first N+ source region 8; a second source 11 is disposed on the upper surface of the second P+ ohmic contact region 5, and the second source 11 extends from the upper surface of the second P+ ohmic contact region 5 to the upper surface of the second N+ source region 9; a P+ protection zone 12 is formed in the middle of the upper surface of the N-drift region 3 by ion implantation, and a P+ protection zone electrode 13 is disposed on the upper surface of the P+ protection zone 12; a third source 14 and a fourth source 15 are disposed on both sides of the P+ protection zone electrode 13, and the lower surfaces of the third source 14 and the fourth source 15 form Schottky contacts with the upper surface of the N-drift region 3, respectively.
[0033] The first source electrode 10 forms ohmic contacts with the interfaces of the first P+ ohmic contact region 4 and the first N+ source region 8, respectively; the second source electrode 11 forms ohmic contacts with the interfaces of the second P+ ohmic contact region 5 and the second N+ source region 9, respectively. In this embodiment, the first source electrode 10 covers the entire upper surface of the first P+ ohmic contact region 4 and a portion of the upper surface of the first N+ source region 8, and correspondingly, the second source electrode 11 covers the entire upper surface of the second P+ ohmic contact region 5 and a portion of the upper surface of the second N+ source region 9.
[0034] Furthermore, the P+ protection zone 12 and the P+ protection zone electrode 13 have the same width, and the two sides of the P+ protection zone electrode 13 are in contact with the third source electrode 14 and the fourth source electrode 15, respectively. In other words, the two side boundaries of the P+ protection zone electrode 13 are perpendicularly aligned with the two side boundaries of the P+ protection zone 12; the right side boundary of the third source electrode 14 is perpendicularly aligned with the left side boundary of the P+ protection zone 12; and the left side boundary of the fourth source electrode 15 is perpendicularly aligned with the right side boundary of the P+ protection zone 12.
[0035] Preferably, in this embodiment, the implantation depth and doping concentration of the P+ protection zone 12 are the same as those of the first P+ ohmic contact region 4 and the second P+ ohmic contact region 5. During fabrication, the P+ protection zone 12 is formed simultaneously with the first P+ ohmic contact region 4 and the second P+ ohmic contact region 5, eliminating the need for additional photolithography and ion implantation processes, thus avoiding increased process complexity. In this embodiment, the material of the P+ protection zone electrode 13 is Ni.
[0036] Furthermore, a first gate dielectric layer 16 and a first gate 17 are stacked between the first source 10 and the third source 14. The lower surface of the first gate dielectric layer 16 simultaneously contacts the first N-drift region 3, the first P-type base region 6, and the first N+ source region 8. A second gate dielectric layer 18 and a second gate 19 are stacked between the second source 11 and the fourth source 13. The lower surface of the second gate dielectric layer 18 simultaneously contacts the first N-drift region 3, the second P-type base region 7, and the second N+ source region 9. In other words, the first gate dielectric layer 16 covers the entire upper surface of the first P-type base region 6 and a portion of the first N-drift region 3 and the first N+ source region 8; the second gate dielectric layer 18 covers the entire upper surface of the second P-type base region 7 and a portion of the first N-drift region 3 and the second N+ source region 9.
[0037] Furthermore, the two sides of the first gate dielectric layer 16 are spaced apart from the first source 10 and the third source 14, respectively; the two sides of the second gate dielectric layer 18 are spaced apart from the second source 11 and the fourth source 13, respectively.
[0038] Preferably, the first source 10 and the second source 11 are made of Ti / Al / Ni multilayer metal, and the third source 14 and the fourth source 15 are made of Ni or Ti metal. The first gate dielectric layer 16 and the second gate dielectric layer 18 are both made of SiO2 with a thickness of 30-100 nm. The first gate 17 and the second gate 19 are polysilicon gates.
[0039] like Figure 2 As shown, in actual use, the first source 10, the second source 11, the third source 14 and the fourth source 15 are connected together and connected to the source voltage, and the first gate 17 and the second gate 19 are connected together and connected to the gate voltage.
[0040] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the working principle of a SiC-based VDMOSFET device resistant to single-event gate damage provided by an embodiment of the present invention. The working principle of the SiC-based VDMOSFET device according to an embodiment of the present invention will be described in detail below.
[0041] The SiC-based VDMOSFET device in this embodiment of the invention operates on the same forward principle as a conventional VDMOSFET device. For example... Figure 3 As shown (the conductive path on the right is similar to that on the left; the following example uses the conductive path on the left), when the applied gate voltage is greater than the threshold voltage, the surface of the first P-type base region 6 inverts, forming a conductive channel, thereby connecting the source and drain, and the device operates normally. Single-event effects generally occur in the blocking state. The advantage of the SiC-based VDMOSFET device in this embodiment of the invention is its excellent resistance to single-event gate damage.
[0042] For traditional structures: when a single particle is incident on a reverse blocking device (drain connected to a positive voltage, gate and source grounded), a large number of electron-hole pairs are generated. Under the influence of the drain voltage, a large number of holes move towards the bottom of the gate oxide layer. If the excess holes cannot be extracted in time, a strong electric field will be added to the gate oxide layer, thereby causing gate damage.
[0043] For the SiC-based VDMOSFET device of this embodiment: when a single particle is incident on the reverse-blocking device (drain connected to positive voltage, gate, source, and P+ protection electrode grounded), a large number of electron-hole pairs are generated. Under the influence of the drain voltage, a large number of holes move towards the bottom of the first gate dielectric layer 16, causing hole accumulation at the interface between the first gate dielectric layer 16 and the N-drift region 3. Therefore, Schottky electrodes (third source 14 and fourth source 15) and the P+ protection zone 12 are introduced. The presence of the Schottky electrodes provides an additional discharge path for excess holes, allowing for rapid extraction of accumulated holes. Simultaneously, the lateral electric field between the closely spaced P+ protection zone 12 and the P-type base region (first P-type base region 6 and second P-type base region 7) can suppress the reverse leakage current of the Schottky junction and the strong electric field in the gate oxide on both sides.
[0044] In summary, the VDMOSFET device of this invention splits the gate dielectric layer into two parts, removes the central gate oxide of the neck region (the region between the two p-type base regions), introduces a Schottky contact, and adds a P+ protection zone. It has the following advantages: (1) Since the implantation depth and doping concentration of the P+ protection zone are consistent with those of the P+ ohmic contact region, it is formed at the same time as the P+ ohmic contact region. No additional photolithography and ion implantation processes are required, and the process complexity will not be increased; (2) After a single particle is incident, the incident track will generate a large number of electron-hole pairs. A large number of holes will accumulate at the interface between the gate oxide and the drift region under the action of voltage bias. Therefore, the Schottky contact is introduced so that holes can be discharged not only through the first and second sources, but also through the third and fourth sources, providing an additional discharge path for excess holes. Accumulated holes can be quickly extracted, thereby effectively reducing the strong additional gate oxide electric field caused by the accumulation of excess holes; (3) The P+ protection zone is close to the P-type base region. When the blocking voltage is high, the depletion region is connected to form a transverse electric field, which can effectively suppress the reverse leakage current of the Schottky junction and the strong electric field in the gate oxide on both sides.
[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A SiC-based VDMOSFET device resistant to single-event gate damage, characterized in that, It includes a substrate (1), a drain (2) located below the substrate (1), and an N-drift region (3) located above the substrate (1), wherein, The upper surface of the N-drift region (3) is ion implanted to form a first P+ ohmic contact region (4) and a second P+ ohmic contact region (5) on both sides. The N-drift region (3) inside the first P+ ohmic contact region (4) is ion implanted to form a first P-type base region (6). The N-drift region (3) inside the second P+ ohmic contact region (5) is ion implanted to form a second P-type base region (7). The upper surface of the first P-type base region (6) is ion implanted to form a first N+ source region (8). The upper surface of the second P-type base region (7) is ion implanted to form a second N+ source region (9). A first source electrode (10) is disposed on the upper surface of the first P+ ohmic contact region (4), and the first source electrode (10) extends from the upper surface of the first P+ ohmic contact region (4) to the upper surface of the first N+ source region (8); a second source electrode (11) is disposed on the upper surface of the second P+ ohmic contact region (5), and the second source electrode (11) extends from the upper surface of the second P+ ohmic contact region (5) to the upper surface of the second N+ source region (9); a P+ protection zone (12) is formed in the middle of the upper surface of the N-drift region (3) by ion implantation, and a P+ protection zone electrode (13) is disposed on the upper surface of the P+ protection zone (12); a third source electrode (14) and a fourth source electrode (15) are disposed on both sides of the P+ protection zone electrode (13), and the lower surfaces of the third source electrode (14) and the fourth source electrode (15) respectively form Schottky contacts with the upper surface of the N-drift region (3); A first gate dielectric layer (16) and a first gate (17) are stacked between the first source (10) and the third source (14). The lower surface of the first gate dielectric layer (16) is in contact with the first N-drift region (3), the first P-type base region (6), and the first N+ source region (8). A second gate dielectric layer (18) and a second gate (19) are stacked between the second source (11) and the fourth source (13). The lower surface of the second gate dielectric layer (18) is in contact with the first N-drift region (3), the second P-type base region (7), and the second N+ source region (9). The inner surface of the first P+ ohmic contact region (4) is in contact with the outer surface of the first P-type base region (6), and the inner surface of the second P+ ohmic contact region (5) is in contact with the outer surface of the second P-type base region (7). The inner surface of the first P+ ohmic contact region (4) is in contact with the outer surface of the first N+ source region (8), and the inner surface of the second P+ ohmic contact region (5) is in contact with the outer surface of the second N+ source region (9). The P+ protection zone (12) and the P+ protection zone electrode (13) have the same width, and the two sides of the P+ protection zone electrode (13) are in contact with the third source electrode (14) and the fourth source electrode (15) respectively. The implantation depth and doping concentration of the P+ protection zone (12) are the same as those of the first P+ ohmic contact region (4) and the second P+ ohmic contact region (5); The two sides of the first gate dielectric layer (16) are spaced apart from the first source (10) and the third source (14), respectively; the two sides of the second gate dielectric layer (18) are spaced apart from the second source (11) and the fourth source (13), respectively.
2. The SiC-based VDMOSFET device resistant to single-event gate damage according to claim 1, characterized in that, The first source electrode (10) forms an ohmic contact with the interface of the first P+ ohmic contact region (4) and the first N+ source region (8); the second source electrode (11) forms an ohmic contact with the interface of the second P+ ohmic contact region (5) and the second N+ source region (9).
3. The SiC-based VDMOSFET device resistant to single-event gate damage according to claim 1, characterized in that, The material of the P+ protected area electrode (13) is Ni.
4. The SiC-based VDMOSFET device resistant to single-event gate damage according to any one of claims 1 to 3, characterized in that, The substrate (1) is made of N-type SiC, phosphorus-doped, with a doping concentration of 5*10⁻⁶. 18 -1*10 19 cm -3 .
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