A dedicated timing processor for LTE communication and LTE communication method

Abstract

The application relates to a special timing processor for LTE communication and an LTE communication method. The special timing processor (TPU) comprises six cores and a common data memory and is based on a specific instruction set. The six cores are used for automatic gain, automatic power, transmission and reception of a current frame, and control of transmission and reception of a next frame in sequence, and the priority is in sequence from high to low. The specific instruction set comprises instructions of general output, trigger output, update operation, SPI operation and register operation, and the operation parameters of the first four kinds of operations comprise interval time. Each core is provided with an internal timer. When the TPU is started, the processing units of the cores send access request signals for the instruction memory to an instruction arbitrator, the instruction to be executed is taken out from the instruction memory according to the current PC pointer, the internal timer is used to determine that the instruction is executed when the interval time expires, and the instruction execution result can be written into the data memory or the data required for executing the instruction is taken out from the data memory. The transmission process of the uplink and downlink baseband data can be accurately and efficiently controlled in time.

Description

TECHNICAL FIELD

[0001] The present application relates to a wireless communication method and a processor, and more particularly to a processor for LTE (Long Term Evolution) communication and a LTE communication method. BACKGROUND

[0002] With the development of technology, the fourth generation mobile communication technology such as LTE technology is widely used. LTE technology is a high-speed wireless communication standard for mobile phones and data terminals in telecommunications, which is a transition from HSDPA (High-Speed Downlink Packet Access) to 4G version, commonly known as 3.9G. The standard is based on the old GSM / EDGE and UMTS / HSPA network technology, and uses modulation technology to improve network capacity and speed. The standard of LTE was first proposed by 3GPP (3rd Generation Partnership Project) in Release 8 version in the fourth quarter of 2008, and was slightly improved in Release 9 version.

[0003] LTE technology mainly uses digital baseband to process data, and radio frequency front end is responsible for data transmission and reception to realize wireless network transmission of data. However, LTE technology including subsequent 4G more advanced mobile communication technology proposes more stringent air interface protocol specification. At present, the industry generally controls the data transmission and reception process by using protocol stack software. This soft control method using general-purpose processor and configuring software has the problems of large hardware overhead, low efficiency, and insufficient accuracy of air interface timing control, which is difficult to meet the application requirements of modern mobile communication scenarios relying on LTE technology and more advanced mobile communication technology. SUMMARY

[0004] The present application is provided to solve the problems existing in the prior art.

[0005] A timing control device for LTE communication is needed, which can significantly reduce hardware overhead and power consumption compared with general-purpose processors, and realize more accurate timing control of the transmission process of uplink and downlink baseband data, and the accuracy can meet the higher requirements of LTE technology including subsequent 4G more advanced mobile communication technology for timing control.

[0006] According to a first aspect of the present application, a dedicated timing processor for LTE communication is provided. The dedicated timing processor comprises six cores and is based on a specific instruction set. The six cores are used for automatic gain control, automatic power control, current frame transmission control, current frame reception control, next frame transmission control and next frame reception control in sequence and have decreasing priority in sequence. The specific instruction set comprises at least general output instruction, trigger output instruction, update operation instruction, SPI operation instruction and register operation instruction, wherein the operation parameters of the general output instruction, the trigger output instruction, the update operation instruction and the SPI operation instruction all contain an interval time for executing the instruction. Each core comprises an independent processing unit, an instruction arbitrator and an instruction memory, in each core, the instruction memory is used to store instructions, the processing unit is used to send an access request signal to the instruction memory to the instruction arbitrator and receive access permission information, and the instruction to be executed is fetched from the instruction memory according to the current PC (program counter) pointer. Each processing unit is provided with an internal timer, and is further configured to, in an enabled state of the dedicated timing processor, determine the expiration of the interval time of the instruction to be executed according to the timing of the internal timer, so that the instruction can be executed.

[0007] According to a second aspect of the present application, an LTE communication method is provided, which utilizes the dedicated timing processor described above to control the transmission and reception timing of the entire transmission and reception process of uplink and downlink data from baseband to radio frequency front end. Specifically, the operation timing of peripheral interface including GPIO and SPI can be controlled by using the dedicated timing processor.

[0008] By using the dedicated timing processor for LTE communication and the LTE communication method according to various embodiments of the present application, the baseband-radio interface, GPIO and SPI and other peripherals can be controlled by using the dedicated timing processor based on the specific instruction set, the precise and efficient timing control of the entire transmission and reception process of uplink and downlink baseband data of more advanced wireless communication technologies such as but not limited to LTE communication (e.g. fourth generation and above) can be achieved, the precise and efficient time control of each operation can be achieved, the hardware overhead and power consumption are reduced, and the precise time control of data transmission and reception is also achieved, and the precision can reach the clock cycle level. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter extensions can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein, and are not intended to limit the disclosure to the embodiments depicted. The same reference numerals in different drawings can identify the same or similar concepts. Such embodiments are illustrative rather than restrictive, and the disclosure is not limited to the embodiments depicted.

[0010] Figure 1 A schematic diagram showing the transceiving process of data from baseband to radio frequency front end for LTE technology according to embodiments of the present application;

[0011] Figure 2 A configuration diagram of a dedicated timing processor (TPU) for LTE communication according to embodiments of the present application;

[0012] Figure 3 A configuration diagram of a core of a dedicated timing processor (TPU) according to embodiments of the present application;

[0013] Figure 4 A state machine diagram showing the control of the instruction prefetch module and the instruction execution module by a control module in each core according to embodiments of the present application;

[0014] Figure 5 A schematic configuration diagram of an instruction prefetch module in each core according to embodiments of the present application; and

[0015] Figure 6 A schematic configuration diagram of an instruction execution module in each core according to embodiments of the present application. DETAILED DESCRIPTION

[0016] In order to make the skilled in the art better understand the technical solutions of the present application, the present application is described in detail below in combination with the drawings and specific embodiments. The embodiments of the present application are further described in detail below in combination with the drawings and specific embodiments, but not as a limitation of the present application. The order in which each step is described herein as an example should not be considered as a limitation, and those skilled in the art should know that the order can be adjusted, as long as it does not destroy the logic between them and leads to the failure of the whole process.

[0017] Figure 1 A schematic diagram showing the transceiving process of data from baseband to radio frequency front end for LTE technology according to embodiments of the present application. As Figure 1As shown, the special timing processor (TPU) according to various embodiments of the present application can precisely control the transmission and reception timing of data in this process. Four parts are involved in the whole transmission process, the radio frequency front end 14, the radio frequency interface 13, the direct memory access 12 and the digital baseband 11, that is, the transmission and reception process from the digital baseband 11 to the radio frequency front end 14. The four parts are schematically divided into four parts by four wireframes in Figure 1 Each part contains the main components and related processing modules. Taking the radio frequency front end 14 as an example, it contains the radio frequency front end as the main component, and also includes the reception control processing module and the transmission control processing module associated therewith.

[0018] The following will briefly describe the transmission and reception process of data from the baseband to the radio frequency front end according to the LTE technology in combination with the hardware wiring diagram in Figure 1 In order to make the diagram simple and clear, the abbreviation TFT is used to represent the downlink kernel processing, the abbreviation LETU is used to represent the uplink kernel processing, the abbreviation LPF is used to represent the low-pass filter data processing, the abbreviation FIFO is used to represent the first-in-first-out memory, the abbreviation TX is used to represent the transmission, the abbreviation RX is used to represent the reception, and the abbreviation DMA is used to represent the direct memory access.

[0019] In the radio frequency front end 14, the radio frequency front end is mainly used to up-mix the transmission data with the carrier and transmit it through the power amplifier; at the same time, the received data is down-mixed through the low-noise amplifier to remove the carrier. The reception control processing and the transmission control processing, as the direct interface of the radio frequency front end, control the start and end of data transmission / reception, and at the same time, simply process the data into data that can be directly used by the radio frequency front end.

[0020] In the radio frequency interface 13 or at the interface with the peripheral modules, all FIFOs are used for cross-clock domain processing of data. The reception path selector is configured to be sent to different modules according to the category of the received data. If downlink service data is received, the reception path selector sends the data to the downlink kernel for downlink data pre-demodulation. If it is downlink measurement data, the reception path selector sends it to the low-pass filter for down-sampling processing. The reception path selector can also directly receive the data without processing. The transmission path selector is configured to be sent to different modules according to the category of the transmission data. If it is uplink service data, the transmission path selector sends it to the uplink kernel processing module for modulation. The transmission path selector can also directly send out the data without processing.

[0021] The data transceiving process from baseband to RF front-end and the hardware layout of the above-mentioned LTE technology are known except for the TPU-related content, which will not be described herein. The application of the TPU to the data transceiving process from baseband to RF front-end and the hardware layout of the LTE technology can provide a new LTE communication method, i.e., the use of the TPU according to various embodiments of the present application to control the transceiving timing of uplink and downlink data at the baseband-RF interface.

[0022] In some embodiments, the LTE communication method can include but is not limited to the use of the TPU according to various embodiments of the present application to control the operation timing of peripheral interfaces including GPIO and SPI.

[0023] The TPU according to various embodiments of the present application can support the transceiving control of two-way received data and one-way transmitted data. The following will describe the TPU in detail in connection with the hardware layout of Figure 1 The TPU is laid out in four parts, i.e., the RF front-end part 14, the RF interface part 13, the direct memory access part 12 and the digital baseband part 11, but the layout mode is not limited thereto, as long as it acts between the baseband and the RF front-end (including the baseband and the RF front-end themselves) to control the transceiving and operation timing.

[0024] As shown in Figure 1 , the TPU can act on the RF front-end by performing general output operations and SPI operations to control the operation timing of peripheral interfaces including GPIO and SPI.

[0025] Further, the TPU can control the reception control processing module and / or the transmission control processing module by performing trigger operations to determine the start and end time points of two-way received data and one-way transmitted data. When the data is sent to the designated module through the reception path selector and / or the transmission path selector, the TPU can also configure the data transmission start and end addresses, transfer types and start enable of the DMA through register operations, thereby controlling the DMA to complete the data transfer between the FIFO and the bus, and finally the digital baseband obtains the received data from the bus to continue the subsequent processing or sends the processed data to the bus to wait for the DMA transfer. The TPU can also act on the digital baseband by performing interrupt operations, etc.

[0026] Figure 2 A configuration diagram of a special timing processor (TPU) for LTE communication according to an embodiment of the present application is shown. As shown in Figure 2 , the special timing processor for LTE communication includes six cores and is based on a specific instruction set. Note that the various cores of the TPU are collectively represented by reference numeral 100 in this document, and the scope of a single core 100 is exemplified by a dashed box. Figure 2 ​

[0027] The six cores are used for automatic gain control, automatic power control, current frame transmission control, current frame receiving control, next frame transmission control and next frame receiving control in sequence and have decreasing priority in sequence.

[0028] The specific instruction set comprises at least general output instruction, trigger output instruction, update operation instruction, SPI operation instruction and register operation instruction, wherein the operation parameters of the general output instruction, the trigger output instruction, the update operation instruction and the SPI operation instruction all contain interval time for executing the instructions.

[0029] As shown in Figure 2 Each core 100 comprises an independent processing unit 101, an instruction arbiter 102 and an instruction memory 103, and it is noted that in this document the processing unit of each different core is uniformly represented by reference numeral 101, the instruction arbiter of each different core is uniformly represented by reference numeral 102, and the instruction memory of each different core is uniformly represented by reference numeral 103.

[0030] In each core 100, the instruction memory 103 is used for storing instructions, the processing unit 101 is used for sending an access request signal of the instruction memory 103 to the instruction arbiter 102 and receiving access permission information, and the instruction to be executed is fetched from the instruction memory 103 according to a current PC (program counter) pointer.

[0031] Each processing unit 101 is provided with an internal timer (not shown in the figure) for measuring the time interval of executing an instruction. Figure 2The internal timer is configured to determine the time interval of the instruction to be executed. As an example, the time interval of the general output instruction, the trigger output instruction, the update operation instruction and the SPI operation instruction are all contained in the operation parameters of the instructions. The TPU can directly control the air interface timing through a hardware signal without relying on the bus. In combination with the internal timing of the time interval of the instruction by the internal timer, the precision of the execution timing of the instruction with the time interval can be easily controlled to one clock cycle (e.g. 30.72Mhz), thereby meeting the strict air interface timing requirements of 4G. The TPU is based on a specific instruction set containing the general output instruction, the trigger output instruction, the update operation instruction and the SPI operation instruction with the time interval, and adopts a 6-core design (6-core single-thread design) for automatic gain control, automatic power control, current frame transmission control, current frame reception control, next frame transmission control and next frame reception control with decreasing priority. The design structure is simple, the hardware overhead is small, and the power consumption is low, while meeting the air interface protocol specification of LTE. The 6-core design with decreasing priority provides a stable fault tolerance, which can prevent the TPU from hanging when the execution results of different cores 100 conflict, so that the execution results of different cores 100 do not conflict under normal circumstances. The use of a specific instruction set-based dedicated timing processor to control the baseband-radio frequency interface, GPIO and SPI peripherals and the like can complete accurate and efficient timing control of the entire transmission process of the uplink and downlink baseband data of more advanced wireless communication technologies (such as the fourth generation and above) such as but not limited to LTE communication. Each operation can be accurately and efficiently time-controlled, reducing hardware overhead and power consumption, while achieving accurate time control of data transmission, with a precision of clock cycle level (e.g. 30.72Mhz).

[0032] Each "module" and component in the present disclosure can be formed as part of an SOC or as an ASIC independent of and electrically connected to each other, in order to balance hardware manufacturing cost and processing speed.

[0033] In some embodiments, each processing unit 101, such as Figure 3As shown, each core 100 can include a control module 101a, an instruction pre-fetch module 101b and an instruction execution module 101c, the control module 101a can control (e.g. control enable) the instruction pre-fetch module 101b and instruction execution module 101c through a state machine, so that: the instruction pre-fetch module 101b sends the access request signal to the instruction arbiter 102, and accordingly, if the instruction arbiter 102 arbitrates that it can have access to the instruction memory 103, it obtains access permission information from the instruction arbiter 102, takes out the instruction to be executed from the instruction memory 103 according to the current PC (program counter) pointer, decodes the instruction after decoding, and sends the decoded instruction to the instruction execution module 101c, and the instruction execution module 101c receives the instruction and sends it to the corresponding execution unit for execution. For example, the instruction execution module 101c can output the corresponding results according to the execution of the execution unit, such as but not limited to register operation, general output, SPI operation, trigger output, interrupt, etc. In some embodiments, each core 100 has a separate instruction memory 103 inside, and the storage capacity is 128*32 bits.

[0034] As shown in Figure 2 and Figure 3 The bus 105 can be included in the TPU, and the bus 105 can be responsible for reading and writing, and the processing unit 101 of each core 100 is responsible for reading out, but the bus 105 and the processing unit 101 of the core 100 can request access to each instruction memory 103, and the corresponding instruction arbiter 102 can be further configured to: also receive the access request signal of the instruction memory 103 from the bus 105; decide whether to give the access permission to the bus 105 or the processing unit 101 of each core 100.

[0035] In order to ensure that the execution results of different cores 100 do not conflict on the basis of fault tolerance of the 6-core design with decreasing priority, an output arbiter 104 connected with the 6 cores 100 is further provided in the TPU, which is configured to: arbitrate the instructions that can be executed by the 6 cores 100 to decide the instruction execution operation to be output, such as but not limited to general output operation, SPI operation, trigger output operation, register operation and interrupt operation, etc.

[0036] In some embodiments, a shared data memory 107 and a data access arbiter 106 are further included in the TPU. In the case that the storage capacity of each instruction memory 103 is 128*32 bits, the storage capacity of the shared data memory 107 is 1024*32 bits accordingly. The data access arbiter 106 is connected with the 6 cores 100 and the bus 105, and is configured to receive a data access request for the shared data memory 107 from each core 100 (especially each processing unit 101) or the bus 105, and to decide the data access right to be given to one of the cores 100 or the bus 105.

[0037] In some embodiments, the instruction arbiter 103, the output arbiter 104 and the data access arbiter 106 are all configured with fixed priority, that is, the priority of the access to be given to one of the parties in case of arbitration is fixed. In this way, the hardware configuration can be simplified and the processing speed can be accelerated.

[0038] The TPU further includes a main timer 108 configured to provide a working clock with a frequency of 30.72Mhz, and to control the overall activation of the TPU. The TPU can be used to complete the control of the radio frequency chip and the link control of the baseband data, and the main timer 108 and the internal timer are used to ensure that the execution of each instruction is effective at the set time point, which will be described in detail below. Figure 6

[0039] The activation time of each core 100 of the TPU can be independently controlled. Any one of three activation modes can be used. The first activation mode is to control the activation by using the register stack 109 (based on the register configuration, see Figure 3 ). The second activation mode is to periodically activate by using the timing of the main timer 108. The third activation mode is to non-periodically interrupt the activation by using the main timer 108 to generate an interrupt number.

[0040] Figure 4 A state machine for controlling the instruction prefetch module 101b and the instruction execution module 101c by the control module 101a in each core according to the embodiments of the present application is shown. As Figure 4 shown, the state machine includes an idle state 401, an instruction fetching state 402 and an execution state 403.

[0041] ​Idle state 401 indicates that the TPU is in a disabled state, in which the reference clock can be stopped, a global reset can be performed, and related register initialization configuration can be performed. When the TPU is in idle state 401, the TPU is configured to perform the following steps in sequence to complete startup: global reset, then enable the master timer 108; write instructions to be executed to the instruction memory 105 via the bus 105; perform related register configuration (e.g., via the register stack 109), including selecting a clock reference, configuring a start time and a start interrupt number, a starting address of a PC pointer, and a count mode of an internal timer; and start the TPU. The interrupt number can be generated by the master timer 108, e.g., eight interrupt numbers can be generated, 0-7.

[0042] When the TPU is in idle state 401, if the TPU is started, the state machine jumps to fetch state 402. Specifically, the state machine jumps to fetch state 402 when any one of the following three optional start modes is true: register enable start, periodic interrupt timer start, and non-periodic interrupt start.

[0043] Fetch state 402 indicates an instruction pre-fetch state. For example, the process can include the state machine jumping to fetch state 402. An access request signal to the instruction memory 103 can be generated, and access to the instruction memory 103 (e.g., via arbitration approval of the instruction arbiter 102) can be obtained. Then, the PC pointer is updated, and the instruction arbiter 102 generates a request completion signal. Then, the instruction can be fetched from the instruction memory 103, decoded, and output.

[0044] When the TPU is in fetch state 402, if the instruction arbiter 102 completes arbitration of the access request signal, the state machine jumps to execution state 403, the PC pointer is updated, the instruction to be executed is fetched from the instruction memory 103, decoded, and output. Specifically, after the instruction arbiter request is completed, the state machine jumps to execution state 403.

[0045] Execution state 403 indicates an instruction execution state.

[0046] When the TPU is in execution state 403, if the instruction execution condition is met, the instruction is executed and the state machine jumps to fetch state 402, or if a non-enabled instruction is executed or all instructions are executed, the state machine jumps to idle state 401. For instructions with an interval time, the instruction is executed after the internal timer counts to the interval time, and the state jump is completed. For instructions without an interval time, the instruction can be executed after one clock cycle, and the state jump is completed.

[0047] Specifically, when either of the two conditions of executing the disable instruction and the instruction in the instruction memory 103 being executed completely is met, the state jumps to the idle state 401.

[0048] The instruction execution condition can include any of the following: in the case of the instruction having an interval time, determining the expiration of the interval time of the instruction according to the timing of the internal timer; in the case of the instruction being a conditional wait instruction, the condition being met; the instruction being an immediate execution instruction. That is, when any of the three conditions of the internal timer counting reaching the instruction interval time, or the conditional wait being completed, or the instruction itself being an immediate execution instruction is met, the state jumps to the instruction fetch state 403.

[0049] As described above, by using the state machine design architecture, immediate number addressing can be used, and compared with the pipeline design and the complex addressing mode of the conventional general-purpose processor, the TPU has the advantages of simple structure, low power consumption, high efficiency, and small overhead.

[0050] After the internal timer of the TPU is started, it starts counting from 0, and the execution time of each instruction in each core 100 is determined by the respective internal timer. After the count value of the internal timer of the TPU reaches the time interval value defined in the instruction operand, the current instruction is executed, the internal timer is cleared, the PC pointer is sequentially incremented by one, and the next instruction is executed. The JUMP instruction can be used to jump the PC pointer to any position in the instruction memory 103 to execute the instruction. The instruction without the interval time parameter will be executed immediately (i.e., the so-called immediate execution instruction), and the instruction with the interval time parameter will wait until the count value of the internal timer (for example, the internal timer provided in the instruction execution module 101c) reaches the interval time, and then the instruction will be executed and the execution result will be output.

[0051] Figure 5 A schematic configuration diagram of an instruction prefetch module in each core according to an embodiment of the present application is shown. As shown, the instruction prefetch module 101b specifically includes an instruction fetch arbitration request generation module 101b3, an instruction pointer generation module 101b1, a first decoder 101b4, an instruction output register 101b5, and a pointer output register 101b2. Figure 5

[0052] The instruction fetch arbitration request generation module 101b3 is configured to generate an instruction fetch arbitration request and send it to the instruction arbitrator 102 when the current state of the state machine is the instruction fetch state, and receive an instruction fetch arbitration request completion signal after the instruction arbitrator 102 responds to the request.

[0053] The first decoder 101b4 is configured to obtain the instruction fetched (read out) from the instruction memory 103, and decode the instruction into a 14-bit instruction identifier (such as​Figure 5 instruction operation type identifier [13:0]) and 28-bit instruction operation parameters (e.g. Figure 5 instruction operation parameters [27:0]) in the instruction, and transmits the instruction operation parameters to the instruction execution module 101c via the instruction output register 101b5 for execution of the instruction.

[0054] The first decoder 101b4 decodes the instruction into a 14-bit instruction identifier, based on which an instruction operation enable signal can be directly generated to feed the clock gate of the processing unit corresponding to the operation in the total of 14 processing units, so as to enable the corresponding processing unit (which will be described in detail below). Figure 6

[0055] The instruction pointer generation module 101b1 is configured to initialize the starting address of the PC pointer according to the state of the state machine and the register configuration value, to determine whether the PC pointer needs to be jumped according to the execution result of the current instruction, to jump to the corresponding position if needed, to sequentially add 1 to the PC pointer (i.e. the next instruction pointer) if no jump is needed, and to generate the current PC pointer, and to output the current PC pointer via the pointer output register 101b2. As shown in Figure 5 the instruction pointer update control can send an update enable signal to control the instruction pointer to be updated to the next PC pointer. The first decoder 101b4 can also transmit the pointer jump information contained in the conditional jump instruction to the instruction pointer generation module 101b1 to perform the pointer jump. That is, if the current execution instruction is a jump instruction or a conditional jump instruction, the instruction pointer jumps to the jump position specified in the instruction, otherwise the instruction pointer is sequentially added by 1.

[0056] Figure 6 A schematic configuration diagram of the instruction execution module 101c in each core according to an embodiment of the present application is shown. It should be noted that the internal timer 108c is built in the processing unit 101, Figure 6 which is set in the instruction execution module 101c, but it is understood that the actual implementation is not limited thereto, and the internal timer 108 can also be set in other modules of the processing unit 101, and the timer count can be obtained by the instruction execution module 101c. However, preferably, the internal timer 108 is set in the instruction execution module 101c, so that the timing control of the instruction execution module 101c is more convenient and the processing speed is faster.

[0057] As shown in Figure 6 the instruction execution module 101c specifically includes the execution units 101ca-101cn of each instruction in the specific instruction set, the output arbitration request generation module 101co, the clock gate 101ct, the second decoder 101c4, and the internal timer 108c.​

[0058] In some embodiments, the specific instruction set can include, in addition to the general output instruction, the trigger output instruction, the update operation instruction, the SPI operation instruction and the register operation instruction, the no-operation instruction, the disable operation instruction, the interrupt operation instruction, the jump instruction, the conditional wait instruction, the data low bit assignment instruction, the data high bit assignment instruction, the conditional jump instruction and the conditional setting instruction, wherein at least the operation parameters of the no-operation instruction, the disable operation instruction, the interrupt operation instruction and the jump instruction contain the interval time.

[0059] The event type, operation code and operation parameter of the 14 instructions are shown in Table 1 below.

[0060] Table 1 Explanation of event type, operation code and operation parameter of 14 instructions of specific instruction set

[0061]

[0062]

[0063] The instructions in the table will be specifically explained below in combination with Table 1.

[0064] 1) No-operation instruction.

[0065] 2 bits [27:26] in 28-bit operation parameter ([27:0]) are used to configure the working mode, 00 in [27:26] means no-operation, no operation is performed when the instruction is executed, and 01 means internal timer working mode setting, which is used to set the internal timer working mode (self-clearing or not clearing, which can also be configured through a register) after the instruction is executed.

[0066] 2 bits [25:24] in 28-bit operation parameter are used to configure mode selection. When [25:24] is 0, it means self-clearing mode, the interval time represents the interval between the execution time of the current instruction and the previous instruction; when [25:24] is 1, it means non-clearing mode, the interval time represents the interval between the execution time of the current instruction and the TUP start time; when [25:24] is 2, it means internal timer clearing, the count value is cleared after the instruction is executed.

[0067] 2) Disable instruction.

[0068] After executing the command, the timing processor state machine jumps to the idle state and waits for the next start-up.

[0069] 3) General output instruction

[0070]

[27] of the 28-bit operation parameter is used to configure the mode selection. When

[27] is 0, it means that the general purpose output (GPO) operation is in single-root setting mode, and one GPO output level can be set at a time. A maximum of 128 general purpose outputs are supported, which are divided into 8 groups, each group having 16 general purpose outputs. When

[27] is 1, it means that the GPO operation is in multi-root setting mode, and a maximum of 8 GPO levels can be set at the same time. At this time, a maximum of 64 general purpose outputs are supported, which are divided into 8 groups, each group having 8 general purpose outputs.

[0071] [26:24] of the 28-bit operation parameter is used to configure the group selection, and [26:24] represents the GPO group number that is specified to be set at this time. The group numbers of the single-root and multi-root setting modes correspond to each other as follows: single-root setting mode group number = [multi-root setting mode group number / 2]. For example, when the 0th group and the 1st group of the multi-root setting mode are combined, they correspond to the low 8 bits and the high 8 bits of the 0th group of GPO in the single-root setting mode, respectively.

[0072] [23:20] of the 28-bit operation parameter is used to configure the bit selection within the group. When it is in the single-root setting mode, it represents the specific bit within the group. When it is in the multi-root setting mode, at this time, the 8 GPOs within the group are set at the same time, and the GPOs that do not need to be set can be shielded through register setting.

[0073] [19:18] of the 28-bit operation parameter is used to configure the update mode. When [19:18] is 0, it means immediate update, that is, the GPO level is updated after the execution of the command; when [19:18] is 1, it means waiting for update, that is, the GPO level is updated after the execution of the update operation command, which can be used for simultaneous assignment of multiple outputs.

[0074] 4) Trigger output instruction

[0075] A pulse signal is used to trigger the output of a beat, and a maximum of 256 trigger outputs are supported. They are divided into 16 groups, each group having 16 trigger outputs. One bit of trigger output can be set at a time, and there are two update modes. The trigger output is mainly used to control the transmission and reception of radio frequency baseband data. Other definitions refer to the definitions of the general purpose output (GPO) instruction.

[0076] 5) Update operation instruction. After the execution of this instruction, the signals in the general purpose output and trigger output that are in the waiting update state will be immediately updated.

[0077] 6) Interrupt operation instruction. This instruction is used to trigger an interrupt to the processing unit at a certain time. Any one of the 32 sequencer interrupts can be selected. [27:23] of the 28-bit operation parameter can be used for interrupt selection.

[0078] 7) SPI operation instruction. Timing sends out the data in SPI or reference internal memory to configure the external RF module. The internal memory shared by both is 256*32 bits. When sending, select a section in the memory to send. Each bit in the 28-bit operation parameter can be configured as follows for the SPI operation instruction.

[0079] [27:20] is used to configure the start address of the sent data, 0 represents the first 32-bit data in the internal memory, and so on, a total of 256.

[0080] [19:16] is used to configure the number of sent data, 0 represents no data transmission, 1 represents one, and so on, a maximum of 15 data can be sent at the same time, if more data needs to be transmitted, use multiple SPI instructions.

[0081] 8) Jump operation instruction.

[0082] After executing this command, the sequencer jumps to the set address (jump address in the instruction) to fetch the instruction.

[0083] [27:20] in the 28-bit operation parameter is used for the jump address, where 0 represents the first instruction in the instruction RAM, 1 represents the second instruction, 63 represents the sixty-fourth instruction, and so on.

[0084] 9) Conditional waiting instruction.

[0085] When the selected condition is 0, the TPU is always in a waiting state, and the time interval timer stops counting. When the selected condition is 1, the TPU continues to read the next event. The parameters and condition selection are as follows: 0 represents condition 0, corresponding to tp_gpo

[64] ; 1 represents condition 1, corresponding to tp_gpo

[65] ; and so on, 15 represents condition 15, corresponding to tp_gpo

[79] . As an example, the instruction set supports 16 conditions.

[0086] 10) Register operation instruction.

[0087] The precondition for executing this instruction is that the RFIF_TP_CTRL.TP_REG_EN register is configured as 1, otherwise this instruction cannot be executed.

[0088] After executing this instruction, the registers of the sequencer or other modules can be read and written through the bus.

[0089] Write operation: Read the register address from the specified address (store data address [9:0]) in the sequencer data memory that requires a write operation. Read the data that requires writing from the specified address + 1. If the value of the operation number [27:20] is greater than 1, then multiple write operations need to be performed. Read the memory address that requires a write operation for the second time from the specified address + 2, read the data that requires writing for the second time from the specified address + 3, and so on.

[0090] Read operation: The meaning is referred to the write operation. Read the register address from the specified address in the sequencer data memory that requires a read operation, and then write the data read from the register into the specified address + 1 in the sequencer data memory, and so on for multiple read operations.

[0091] Interrupt enable and condition enable:

[0092] Used to indicate whether an interrupt operation or a condition waiting operation is triggered after the completion of the register read / write operation. [15:11] in the 28-bit operation parameter is used to configure the bit selection, i.e., to determine which interrupt. When multiple sequencers simultaneously execute the register read / write operation instruction, the REG instruction is executed according to the priority order of the sequencer numbers 0-6.

[0093] The same sequencer can use at most 2 instructions in succession to complete the register read / write operation.

[0094] 11) Data low bit assignment operation

[0095] Write operation is performed on the low 16 bits of the data memory shared by the timing processor. Among the parameters, the storage data address: 0 represents the address of the first data of the data memory, 1 represents the address of the second data of the data memory, and so on, 1023 represents the address of the 1024th data of the data memory.

[0096] 12) Data high bit assignment operation

[0097] Write operation is performed on the high 16 bits of the data memory shared by the timing processor. Among the parameters, the storage data address: 0 represents the address of the first data of the data memory, 1 represents the address of the second data of the data memory, and so on, 1023 represents the address of the 1024th data of the data memory.

[0098] 13) Condition jump instruction

[0099] [27:20] in the 28-bit operation parameter is used to configure the jump address, indicating the address in the sequencer instruction RAM to jump to after the execution of this instruction if the condition is met. 0 represents the first address, 1 represents the second address, and so on.

[0100] [9:0] of the 28-bit operation parameter is used to configure the storage condition address, indicating the address in the shared data RAM. The data stored in this address is regarded as the condition, and any bit in the 32-bit data is indicated by the bit selection [16:12]. 0 indicates the first address, 1 indicates the second address, 1023 indicates the 1024th address in the data RAM, and so on.

[0101]

[17] of the 28-bit operation parameter is used to configure the condition negation. When it is 0, it indicates no negation. That is, when the condition bit is 0, the instruction jump is not performed, and the next instruction is executed according to the instruction queue order; when the condition bit is not 0, it is regarded as the condition being met, and the next instruction is executed at the specified address of the instruction memory. When it is 1, it indicates negation. The reference meaning is just the opposite of when it is 0.

[0102] 14) Condition setting instruction

[0103] After executing this instruction, the corresponding operation (setting, clearing, left shifting, right shifting, addition and subtraction) will be performed on the specified condition bit, which is mainly used to set the condition bit used in the conditional jump operation.

[0104] [27:24] of the 28-bit operation parameter is used to configure the mode selection. 0 indicates that the bit selection is needed, and the specified condition bit is set to 1; 1 indicates that the bit selection is needed, and the specified condition bit is cleared to 0; 2 indicates that the 32-bit data in the specified address of the data RAM is right shifted as a whole, and the highest bit is filled with 0; 3 indicates that the left shift is performed as a whole, and the lowest bit is filled with 0; 4 indicates that the subtraction of 1 is performed as a whole; and 5 indicates that the addition of 1 is performed as a whole.

[0105] Corresponding to the 14 instructions, Figure 6 correspondingly equipped with a no-operation unit 101ca, a no-enable operation unit 101cb, a general output unit 101cc, a trigger output unit 101cd, an update operation unit 101ce, an interrupt operation unit 101cf, an SPI operation unit 101cg, a jump operation unit 101ch, a condition waiting unit 101ci, a register operation unit 101cj, a data low bit assignment unit 101ck, a data high bit assignment unit 101cl, a conditional jump unit 101cm, and a condition setting unit 101cn as the execution unit of each instruction.

[0106] The execution unit of each instruction is correspondingly provided with the gated clock, and the instruction identification of each instruction causes the sending of the instruction operation enable signal to the corresponding gated clock to enable the execution unit of the corresponding instruction. In order to make the illustration clearer and simpler, Figure 6 corresponding to the no-operation instruction and the corresponding no-operation unit 101ca, and only the timing control thereof is shown, which is also applicable to the execution units of other instructions, and will not be described here.

[0107] The second decoder 101c4 is configured to receive the instruction operation parameters and to perform the final decoding, and to enable only the execution unit of the corresponding instruction, such as the NOP unit 101ca, to execute the instruction according to the final decoding result (decoded operation parameters). Which execution unit is enabled depends on the output of the instruction operation enable signal, not the second decoder 101c4.

[0108] The internal timer 108c is configured to perform timing, and if the instruction to be executed has an interval time (such as a NOP instruction) and the interval time of the instruction expires according to the timing of the internal timer 108c, the execution unit of the instruction, i.e. the NOP unit 101ca, is enabled to execute the instruction. For example, the NOP unit 101ca is enabled by turning on the gated clock 101ct with the instruction operation enable signal. Refer back to Figure 5 If the instruction operation type identifier [13:0] is 0, i.e. instruction operation type 0, NOP instruction, the instruction operation enable signal (i.e. this bit) can make the control signal of the gated clock 101ct of the NOP unit 101ca valid, thereby enabling the gated clock 101ct and the NOP unit 101ca. The working clock of the internal timer 108c is also provided by the main timer 108, and information such as register configuration information and count mode control is obtained.

[0109] The output arbitration request generation module 101co is configured to generate an output arbitration request signal, and if the output arbitration is completed, also to receive an output arbitration completion signal.

[0110] Returning Figure 1 The present application also provides an LTE communication method using the special timing processor according to various embodiments of the present application to control the transceiving timing of uplink and downlink data at the baseband radio frequency interface.

[0111] In some embodiments, the LTE communication method further includes using the special timing processor according to various embodiments of the present application to control the operation timing of peripheral interfaces including GPIO and SPI.

[0112] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used in addition to those described specifically herein, by one of ordinary skill in the art upon reviewing the above description. Still further, in the specific embodiments described above, various features can be grouped together or divided up for the purpose of simplifying the present disclosure. This should not be interpreted as a requirement in any of the claims to more features than are needed to support the recited claim. Rather, inventive subject matter can be less than all of the features of a particular disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, by way of examples or embodiments, wherein each claim can stand on its own as a separate embodiment, and the scope of the application should be determined with reference to the entire description, and not by relying solely on the abstract or summary of the embodiments.

Claims

1. A dedicated timing processor for LTE communications, wherein, The special timing processor includes 6 cores and is based on a specific instruction set, The 6 cores are used for automatic gain control, automatic power control, current frame sending control, current frame receiving control, next frame sending control and next frame receiving control in sequence and have priority in sequence from high to low; The specific instruction set at least includes general output instruction, trigger output instruction, update operation instruction, SPI operation instruction and register operation instruction, wherein operation parameters of the general output instruction, the trigger output instruction, the update operation instruction and the SPI operation instruction all contain interval time for executing the instruction; Each core includes an independent processing unit, an instruction arbiter and an instruction memory, in each core, the instruction memory is used for storing instructions, the processing unit is used for sending an access request signal of the instruction memory to the instruction arbiter and receiving access permission information, and an instruction to be executed is fetched from the instruction memory according to a current program counter (PC) pointer, Each processing unit is provided with an internal timer, and is further configured to: in an enabled state of the special timing processor, control air interface timing through a hardware signal without relying on a bus, determine expiration of interval time of the instruction to be executed according to timing of the internal timer, enable execution of the instruction, and control precision of execution timing of the instruction with interval time to one clock cycle.

2. The special-purpose timing processor of claim 1, wherein, Each processing unit includes a control module, an instruction prefetch module and an instruction execution module, the control module controls the instruction prefetch module and the instruction execution module through a state machine, so that: the instruction prefetch module sends the access request signal to the instruction arbiter, obtains access permission information from the instruction arbiter, fetches an instruction to be executed from the instruction memory according to a current PC pointer, sends the instruction to the instruction execution module after decoding, and the instruction execution module receives the instruction and sends it to a corresponding execution unit for execution.

3. The special-purpose timing processor of claim 2, wherein, Further comprising an output arbiter connected with the 6 cores, configured to arbitrate instructions executable by the 6 cores to determine an instruction execution operation to be output.

4. The special purpose timing processor of claim 3, wherein, Each instruction arbiter is further configured to: also receive an access request signal of the instruction memory from the bus; and determine whether to give access permission to the bus or the processing unit of each core.

5. The special purpose timing processor of claim 3, wherein, Further comprising a shared data memory and a data access arbiter, the data access arbiter is connected with the 6 cores and the bus, and is configured to: receive a data access request of the shared data memory from each core or the bus; and determine data access permission to be given to one of the cores or the bus.

6. The special purpose timing processor of any of claims 3-5, wherein, The instruction arbiter, the output arbiter and the data access arbiter all adopt a fixed priority configuration.

7. The special purpose processing unit of claim 2, wherein, Further comprising a master timer configured to provide a working clock with a frequency of 30.72Mhz and used for controlling overall enablement of the special timing processor.

8. The special purpose timing processor of claim 7, wherein, The state machine includes an idle state, an instruction fetching state and an execution state, If the special timing processor is started when currently in the idle state, the state machine jumps to the instruction fetching state, When the state machine is in the fetch state, if the instruction arbitrator completes arbitration on the access request signal, the state machine jumps to the execute state, the PC pointer is updated, the instruction to be executed is fetched from the instruction memory, decoded and outputted; When the state machine is in the execute state, if the instruction execution condition is met, the instruction is executed and the state machine jumps to the fetch state, if the instruction is not enabled or the instruction is executed completely, the state machine jumps to the idle state.

9. The special purpose timing processor of claim 8, wherein, The instruction execution condition includes any one of the following: in the case that the instruction has an interval time, the interval time of the instruction is determined to be expired according to the timing of the internal timer; in the case that the instruction is conditional, the condition is true; the instruction is an immediate execution instruction.

10. The special purpose timing processor of claim 8, wherein, When the state machine is in the idle state, the special timing processor is configured to sequentially execute the following steps to complete the start-up: Global reset, and then enable the main timer; Write the instruction to be executed into the instruction memory through the bus; Perform the related register configuration, including selecting the clock reference, configuring the start-up time and start-up interrupt number, the start address of the PC pointer, and the internal timer counting mode; Start the special timing processor.

11. The special purpose timing processor of claim 10, wherein, The start-up of the special timing processor includes three optional start-up modes of register enabled start-up, non-periodic timing start-up and periodic interrupt timing start-up.

12. The special purpose processing unit of claim 2, wherein, The instruction pre-fetch module specifically includes a fetch instruction arbitration request generation module, an instruction pointer generation module, a first decoder, an instruction output register and a pointer output register, The fetch instruction arbitration request generation module is configured to generate a fetch instruction arbitration request and send it to the instruction arbitrator in the fetch state, and receive a fetch instruction arbitration request completion signal after the instruction arbitrator responds to the request; The first decoder is configured to obtain the instruction fetched from the instruction memory, decode the instruction into a 14-bit instruction identifier and a 28-bit operation parameter, and transmit the instruction to the instruction execution module through the instruction output register; The instruction pointer generation module is configured to initialize the start address of the PC pointer according to the state of the state machine and the register configuration value, and determine whether the PC pointer needs to jump according to the current instruction execution result, jump to the corresponding position if needed, and sequentially add 1 to the PC pointer if no jump is needed, thereby generating the current PC pointer; The current PC pointer is outputted through the pointer output register.

13. The application-specific temporal processor of claim 2, wherein, The instruction execution module specifically includes an execution unit of each instruction in the specific instruction set, an output arbitration request generation module, a gated clock, a second decoder and the internal timer, The execution unit of each instruction is correspondingly provided with the gated clock, and the instruction identifier of each instruction is configured to send an instruction operation enable signal to the corresponding gated clock to enable the execution unit of the corresponding instruction; The second decoder is configured to receive the operation parameter and perform final decoding; According to the final decoding result, only the enabled execution unit of the corresponding instruction executes the instruction. The internal timer is configured to time, if the instruction to be executed has an interval time and the interval time of the instruction expires according to the timing of the internal timer, enable the execution unit of the instruction to execute the instruction; The output arbitration request generation module is configured to generate an output arbitration request signal, and receive an output arbitration completion signal in response to completion of the output arbitration.

14. The special purpose processing unit of any of claims 1-5, wherein, The specific instruction set further comprises a no-operation instruction, a disable-operation instruction, an interrupt-operation instruction, a jump instruction, a conditional-wait instruction, a data-low-bit assignment instruction, a data-high-bit assignment instruction, a conditional-jump instruction and a conditional-set instruction, wherein at least the operation parameters of the no-operation instruction, the disable-operation instruction, the interrupt-operation instruction and the jump instruction contain an interval time.

15. A method of LTE communication, the method comprising: The uplink and downlink data transceiving timing of the transceiving process of the baseband to the radio frequency front end is controlled by using the special timing processor according to any one of claims 1-14.

16. The LTE communication method of claim 15, wherein, Further comprising: The operation timing of the peripheral interface including GPIO and SPI is controlled by using the special timing processor according to any one of claims 1-14.

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