A processor processing method, device, storage medium and electronic equipment

Abstract

The embodiment of the present disclosure provides a processor processing method and device, a storage medium and an electronic device, and relates to the technical field of computers. A peripheral interface of a processor is used for connecting peripherals. The method comprises the following steps: receiving an interrupt request and a priority request of the peripheral, adjusting the priority of the peripheral according to the priority request and a priority adjustment range corresponding to the peripheral; processing the interrupt request using a processor core according to the adjusted priority; and / or, in response to a determined key process, accessing an instruction memory space of the key process, determining a target instruction of the key process, detecting a memory space required by the target instruction, and adjusting the memory space of the key instruction according to the memory space required by the target instruction and an unused special space. In this way, the real-time adjustment of the priority and / or the real-time adjustment of the memory space of the key process improve the service quality performance of the processor and the balance of the overall performance of the processor.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a processor processing method, apparatus, storage medium, and electronic device. Background Technology

[0002] The two most important aspects of implementing processor (CPU) Quality of Service (QoS) are interrupt priority management and memory resource allocation. In related technologies, interrupt priority management involves the CPU assigning priorities to different peripheral interfaces, ensuring that tasks on higher-priority peripheral interfaces receive CPU resources first. Memory resource allocation involves the CPU using the memory controller or bus arbitration mechanisms to ensure that critical tasks receive sufficient memory bandwidth.

[0003] like Figure 1 As shown, a CPU can contain multiple processor cores, an interrupt controller, peripheral interfaces, a memory controller, etc. Multiple cores execute instructions, and peripheral interfaces (such as...) Figure 1 Interfaces 0, 1, ..., N-1 in the interface are connected to external peripheral devices (such as... Figure 1 The system uses peripherals (peripheral 0, peripheral 1, ..., peripheral N-1) to generate interrupt signals that connect to the interrupt controller. The interrupt controller sends these signals to the Core based on the peripherals' priority. High-priority interrupts are sent to the Core first. Upon receiving an interrupt signal, the Core pauses its current task and executes the corresponding interrupt handler. After the interrupt handler finishes, it returns to the previously paused task. The memory controller controls the Core's access to external DDR (Double Data Rate Synchronous Dynamic Random Access Memory), enabling DDR data access and writing for instructions. It also allocates specific DDR space for high-priority processes based on configuration, ensuring that only the corresponding processes access the designated DDR space.

[0004] The above-mentioned implementation scheme for CPU QoS function has the following problems:

[0005] 1. There are flaws in the priority management of peripherals; the priority of their interfaces is fixed. Figure 1The interrupt controller in the system has an interrupt vector table, which specifies the priority of interrupt numbers. For example, the priority order is: interrupt number 0 > interrupt number 1 > interrupt number 1... interrupt number N-1. When using the system, the user assigns interrupts from interface 0 to interface N-1 to interrupt numbers 0 to N-1 according to the usual priority of the peripherals. For example, if the user considers external device 0 corresponding to interface 0 to have the highest priority, then the interrupt number for interface 0 is set to interrupt number 0; if the user considers external device 5 corresponding to interface 5 to have the second highest priority, then the interrupt number for interface 5 is set to interrupt number 1; if the user considers external device 10 corresponding to interface 10 to have the next highest priority, then the interrupt number for interface 10 is set to interrupt number 2; and so on.

[0006] Even if users configure interrupt priorities for N peripherals according to their own preferences, the priority order of peripherals cannot be modified once the hardware connection is fixed, posing a significant potential risk. For example, a peripheral set to high priority may not be handling an actually important process, or it may be executing an actually important process for most of the time but its importance is not high during a specific period. Similarly, a peripheral set to low priority may not be handling an actually unimportant process, or it may be executing an actually unimportant process for most of the time but its importance is high during a specific period. This makes it impossible for traditional solutions to accurately and dynamically identify the importance of external device processes, thus failing to achieve reasonable interrupt priority allocation. This results in a significant potential risk that important processes running on low-priority peripherals may not be prioritized by the CPU or may even remain unprocessed (e.g., a peripheral set to high priority by default continuously generates interrupts). In extreme cases, this could lead to irreparable losses of critical business operations.

[0007] 2. Memory resource allocation is largely arbitrary, failing to accurately allocate memory resources based on the actual memory requirements of critical processes. Traditional solutions, in order to ensure the real-time processing of critical processes, often allocate a relatively large amount of memory space, even though the actual usage space may not be that large. For example, if 200MB of space is allocated to a critical process, but the process only uses 20MB, other regular processes cannot use the remaining 180MB (200MB - 20MB), resulting in a significant waste of memory and severely impacting the normal operation of regular processes. Summary of the Invention

[0008] This disclosure provides a processor processing method, apparatus, storage medium, and electronic device to at least solve the above-mentioned technical problems existing in the prior art.

[0009] The technical solution of this disclosure embodiment is implemented as follows:

[0010] In a first aspect, embodiments of this disclosure provide a processing method for a processor, the processor including multiple processor cores and multiple peripheral interfaces, the peripheral interfaces being used to connect peripherals, the method including:

[0011] The processor receives interrupt requests and priority requests from peripherals, adjusts the priority of the peripherals according to the priority request and the priority adjustment range corresponding to the peripherals, and triggers the processor core to process the interrupt request according to the adjusted priority.

[0012] And / or,

[0013] In response to a identified critical process, the instruction memory space of the critical process is accessed to determine the target instruction of the critical process, which is an instruction involving memory operations; the memory space required by the target instruction is detected; and the memory space of the critical process is adjusted based on the memory space required by the target instruction and unused dedicated space.

[0014] In a second aspect, embodiments of this disclosure provide a processing apparatus applied to a processor, the processor including multiple processor cores and multiple peripheral interfaces, the peripheral interfaces being used to connect peripherals, the apparatus comprising:

[0015] The first processing module is used to receive interrupt requests and priority requests from peripheral devices, adjust the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device, and trigger the processor core to process the interrupt request according to the adjusted priority.

[0016] And / or,

[0017] The second processing module is configured to, in response to a determined critical process, access the instruction memory space of the critical process, determine the target instruction of the critical process, wherein the target instruction is an instruction involving memory operations; detect the memory space required by the target instruction; and adjust the memory space of the critical process based on the memory space required by the target instruction and unused dedicated space.

[0018] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the processing methods described above.

[0019] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the processing methods described herein.

[0020] The embodiments disclosed herein have the following beneficial effects:

[0021] This disclosure provides a processor processing method, apparatus, storage medium, and electronic device. The processor includes multiple processor cores and multiple peripheral interfaces for connecting peripherals. The method includes: receiving interrupt requests and priority requests from peripherals; adjusting the priority of the peripherals according to the priority requests and the priority adjustment range corresponding to the peripherals; triggering processor cores to process the interrupt requests according to the adjusted priorities; and / or, in response to a determined critical process, accessing the instruction memory space of the critical process, determining the target instruction of the critical process, wherein the target instruction is an instruction involving memory operations; detecting the memory space required by the target instruction; and adjusting the memory space of the critical process according to the memory space required by the target instruction and unused dedicated space. Thus, by segmenting priorities and adjusting priorities in real time based on these segments, the timely processing of critical processes on all peripheral interfaces is guaranteed to the greatest extent, greatly improving processor quality of service (QoS) performance and system security. By accurately predicting and adjusting the memory space required by critical processes, the drawbacks of blindly allocating excessively large dedicated spaces for critical processes in traditional solutions are avoided. This ensures the normal execution of critical processes while minimizing the impact on regular processes. Consequently, the processor's quality-of-service performance and overall performance balance are improved.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating the implementation architecture of a traditional CPU QoS performance.

[0024] Figure 2 A schematic flowchart illustrating a processor processing method provided in an embodiment of this disclosure;

[0025] Figure 3 A diagram illustrating an implementation architecture for CPU QoS performance provided in this disclosure embodiment;

[0026] Figure 4 This is a schematic diagram of the structure of a dynamic interrupt controller provided in an embodiment of the present disclosure;

[0027] Figure 5 A schematic diagram of the structure of a key process memory control module provided in an embodiment of this disclosure;

[0028] Figure 6 This is a schematic diagram of the structure of a processing device provided in an embodiment of the present disclosure;

[0029] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0030] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0034] Figure 2 A flowchart illustrating a processor processing method provided in an embodiment of this disclosure is shown below. Figure 2 As shown, the method is applied to a processor, which includes multiple processor cores and multiple peripheral interfaces. The peripheral interfaces are used to connect peripherals. The method includes:

[0035] Step 201: Receive the interrupt request and priority request from the peripheral device; adjust the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device; trigger the processor core to process the interrupt request according to the adjusted priority.

[0036] And / or,

[0037] Step 202: In response to the identified critical process, access the instruction memory space of the critical process, determine the target instruction of the critical process, the target instruction being an instruction involving memory operations; detect the memory space required by the target instruction; adjust the memory space of the critical process based on the unused dedicated space and the memory space required by the target instruction.

[0038] In some embodiments, the processor may be a multi-core processor, a multi-core heterogeneous processor, etc., which may have multiple processor cores and multiple peripheral interfaces. Each peripheral interface can connect to one peripheral. Each peripheral can trigger one or more interrupt requests. Upon receiving an interrupt request, the processor will pause its current task and execute the interrupt handler corresponding to the interrupt request.

[0039] Priority specifically refers to the priority of peripheral processes, which determines the order in which interrupt requests are processed, i.e., the execution order of peripheral processes. The higher the priority, the earlier the peripheral's interrupt request is processed, and the higher the priority of the process execution. Interrupt requests from higher-priority peripherals can be processed first in the dynamic interrupt controller, ensuring timely response to important peripheral requests.

[0040] Each peripheral can trigger a priority request to request an adjustment (such as an increase) in priority, which can make the peripheral process execute as quickly as possible.

[0041] Peripheral interfaces can be of various types, such as PCIe, USB, Ethernet, UART, IIC, SPI, etc.; each type of peripheral interface can be one or more. For example, Figure 3 As shown, this disclosure provides a schematic diagram of a processor structure; the processor has multiple cores and N peripheral interfaces; each peripheral interface (such as...) Figure 3 Interfaces 0, 1, ..., N-1 in the interface are connected to external peripherals (such as... Figure 3 Peripherals 0, 1, ..., N-1 (in the diagram).

[0042] Each interface type can have one or more interfaces, such as 8 PCIe x16 ports, 10 USB ports, 4 Ethernet ports, 6 UART ports, 12 IIC ports, and 3 SPI ports. PCIe interfaces connect to peripherals such as solid-state drives, graphics cards, and sound cards; USB interfaces connect to peripherals such as mice, keyboards, and USB flash drives; Ethernet interfaces connect to peripherals such as Ethernet devices; IIC / UART interfaces are used to interact with external management chips; and SPI interfaces are used to connect to Flash devices for system booting, etc. The above examples of interface types and connected peripherals are just one illustration; other types may be included in actual applications, which are not listed here.

[0043] In this embodiment of the disclosure, the processing order of peripheral interrupts is optimized by dynamically adjusting the priority; and / or, the memory space required by the instructions of critical processes is dynamically adjusted, thereby optimizing the processor service quality performance, improving the processor service quality performance, and thus improving the overall performance balance of the processor chip.

[0044] In some embodiments, adjusting the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device includes:

[0045] Determine whether the priority request is a priority promotion request or a priority maintenance request;

[0046] If the priority request is a priority upgrade request, determine the priority adjustment range of the peripheral according to the first priority segment to which the peripheral belongs, and determine the upgrade level corresponding to the priority upgrade request; adjust the priority of the peripheral from the first priority segment to the second priority segment according to the upgrade level and the priority adjustment range of the peripheral.

[0047] If the priority request is a priority maintenance request, the priority of the peripheral device remains unchanged.

[0048] Here, the processor may have a controller for dynamically adjusting peripheral priorities, for example, Figure 3 The dynamic interrupt controller shown.

[0049] During operation, peripherals can send interrupt requests (denoted as irq_req) to the dynamic interrupt controller. If a peripheral wishes to increase its processing priority to gain faster access to processor core resources and improve processing efficiency, it can send a priority increase request. This request is used to raise the priority level and can be denoted as irq_up_req[1:0], where [1:0] represents a two-bit binary signal indicating priority ranges such as 0, 1, 2, 3, etc., or other identifiers representing the requested priority range. If the peripheral does not want to increase its processing priority, it lowers the priority level by setting irq_up_req=0, thus establishing a priority maintenance request. Therefore, by determining whether the priority request is a priority increase request or a priority maintenance request, it can be determined whether the peripheral needs to increase its priority.

[0050] If the priority request is a priority promotion request, the range of promotion that the peripheral can be taken into account is determined based on its current priority segment (i.e., the first priority segment). Then, considering the required promotion level (e.g., level 1, level 2, etc., representing different degrees of priority increase), the peripheral is promoted from its current priority segment to a higher second priority segment. If the priority request is a priority maintenance request, no changes are made, and the peripheral's current priority remains unchanged. This helps stabilize peripherals that do not require immediate priority promotion, avoiding unnecessary resource contention and system fluctuations.

[0051] In one example, such as Figure 3 As shown, there are N peripherals (peripheral 0 to peripheral N-1). The priorities of the N peripherals are divided into X priority segments. Assuming X is 4, then there are 4 priority segments (the value of X can be set by the user or extracted, such as 3, 5, etc.), which are denoted as segment A, segment B, segment C, and segment D respectively. The default priority order is segment A > segment B > segment C > segment D.

[0052] If irq_up_req is 1, the priority of the peripheral is raised by 1 level. For example, if the peripheral's priority is in segment D, the priority is adjusted to segment C.

[0053] If irq_up_req is 2, the priority of the peripheral will be increased by 2 levels. For example, if the priority of the peripheral is in segment D, the priority will be adjusted to segment B.

[0054] If irq_up_req is 3, the priority of the peripheral will be increased by 3 levels. For example, if the priority of the peripheral is in segment D, the priority will be adjusted to segment A.

[0055] Of course, if X is other values, such as 5, then irq_up_req can also be 4 or other values. The above is just one example, and there are no restrictions on the values ​​of X and irq_up_req.

[0056] In some embodiments, the method further includes:

[0057] Determine the number of peripherals connected to the processor;

[0058] The peripherals are segmented according to their number to obtain multiple priority segments;

[0059] Set the priority adjustment range for each priority segment to obtain a priority adjustment range table;

[0060] Each priority segment includes at least one peripheral device, and the peripheral devices in different priority segments have different priorities.

[0061] Accordingly, the priority adjustment range of the peripheral is determined based on the first priority segment to which the peripheral belongs, including:

[0062] The priority adjustment range of the peripheral is determined by querying the priority adjustment range table according to the first priority segment to which the peripheral belongs.

[0063] Here, priority segments can be pre-divided for each peripheral. For example, if there are N peripherals (peripheral 0 to peripheral N-1), the priority of the N peripherals can be divided into X priority segments. Assuming X is 4, then there are 4 priority segments, which are denoted as segment A, segment B, segment C, and segment D respectively.

[0064] Peripherals in different priority segments have different priorities, indicating that peripherals within each priority segment have different priorities based on their importance, urgency, etc. For example, real-time input devices may be assigned to a high-priority segment, while less urgent peripherals may be assigned to a low-priority segment. Based on the above examples, a priority relationship can be set as: Segment A > Segment B > Segment C > Segment D.

[0065] The value of X can be set by the user or other values, such as 3 or 5. The setting can be combined with the number of peripherals. X should be less than or equal to the total number of peripherals.

[0066] For each priority segment, a priority adjustment range is set. This range defines the range to which the priority of the internal and external devices in that priority segment can be adjusted, such as whether it can be adjusted from segment A to segment D, or whether it can be adjusted from segment D to segment B, etc.

[0067] By establishing a priority adjustment range table, the system can make quick decisions when processing requests, thereby optimizing the response time and resource utilization efficiency of peripherals.

[0068] In some embodiments, setting the priority adjustment range for each priority segment includes:

[0069] The priority adjustment range for each priority segment is determined based on the principle that high-priority segments are adjusted to lower-priority segments within a first limit, while low-priority segments are adjusted to higher-priority segments without limit.

[0070] Here, we will explain the setting method with an example. Assume that there are 4 priority segments: A, B, C, and D; A > B > C > D; and the division is based on 50%. The high priority segment includes segments A and B, and the low priority segment includes segments C and D.

[0071] The principle for setting the priority adjustment range is as follows: peripherals originally in the high-priority segment can be adjusted to the low-priority segment to a limited extent; peripherals originally in the low-priority segment can be adjusted to the high-priority segment indefinitely. In this way, this setting principle ensures that critical processes of originally low-priority peripherals can be processed by the processor core as soon as possible, and also ensures that processes of originally high-priority peripherals are not adjusted to the lowest priority.

[0072] It should be noted that even if the priority is adjusted, the number of peripherals in each priority segment remains unchanged.

[0073] Based on the above examples, the priority adjustment range within segment A can be the priority interval within the original segments B and C; the priority adjustment range within segment B can be the priority interval within the original segments A and C; the priority adjustment range within segment C can be the priority interval within the original segments A, B, and D; and the priority adjustment range within segment D can be the priority interval within the original segments A, B, and C.

[0074] Accordingly, the created external priority adjustment range table can be shown in Table 1 below:

[0075] Table 1

[0076]

[0077] Here, A_period, B_period, C_period, and D_period represent priority intervals, or priority segments. The default priority refers to the original priority segment of the peripheral, denoted as the first priority segment; the dynamic priority adjustment interval represents the range of priority adjustments that the peripheral in the corresponding priority segment can be made to, and the adjusted priority segment is denoted as the second priority segment.

[0078] Within each priority range, peripherals can also have different priorities. For example, suppose that... Figure 3 The N peripherals are divided into 4 segments, and each segment has N / 4 peripherals. The priority is assigned by number, such as 1, 2, 3...N, for a total of N numbers. The smaller the number, the higher the priority.

[0079] The priority ranges for the N / 4 peripherals within segment A are 1, 2...N / 4;

[0080] The priority intervals for the N / 4 peripherals within segment B are (N / 4)+1, (N / 4)+2, ..., N / 2.

[0081] The priority intervals for the N / 4 peripherals within segment C are (N / 2)+1, (N / 2)+2, ..., 3×N / 4.

[0082] The priority intervals for the N / 4 peripherals within segment D are (3×N / 4)+1, (3×N / 4)+2, ..., N.

[0083] Here, the priority adjustment range refers to the range within which a peripheral device's priority can be increased or decreased during priority management. The priority adjustment range is obtained by querying the priority adjustment range table based on the peripheral device's original priority segment (i.e., the first priority segment). For example, the adjustment range for priority segment A might be -2, while the adjustment range for priority segment B might be ±1. This allows for more flexible adjustment of its priority.

[0084] Based on Table 1 above, here is an example. As shown in Table 1, only peripherals in segment D can be upgraded without restriction, that is, they can generate irq_up_req=0 / 1 / 2 / 3; peripherals in segment C can only generate irq_up_req=0 / 1 / 2; peripherals in segment B can only generate irq_up_req=0 / 1; peripherals in segment A can only generate irq_up_req=0, that is, priority adjustment in segment A is a passive adjustment.

[0085] If multiple priority adjustment requests from peripherals are received within the same time period, a comprehensive judgment will be made. For example, if two priority increase requests with irq_up_req=1 are received in segment D and one irq_up_req=1 request is received in segment C, then a priority in segment B will be downgraded to segment D, the priority of the request in segment C that initiates irq_up_req=1 will be set to segment B, and at the same time, a priority in segment C will be downgraded to segment D, and the two priorities in segment D that initiate irq_up_req=1 will be set to segment C.

[0086] In some embodiments, the method further includes:

[0087] The frequency of interrupt requests initiated by each peripheral device and the average interrupt processing time are detected, and the target peripheral devices with priority adjustment needs are determined based on the detection results.

[0088] The priority of the target peripheral is adjusted, and the processor core is triggered to process the interrupt request according to the adjusted priority.

[0089] Among them, the target peripherals with priority adjustment requirements determined based on the test results include:

[0090] If the frequency of interrupt requests initiated by high-priority peripherals is lower than the first frequency threshold and the average interrupt processing time is higher than the first time threshold, then the high-priority peripherals are determined to be the target peripherals, and the priority adjustment target of the target peripherals is to lower them.

[0091] If the frequency of interrupt requests initiated by a low-priority peripheral is higher than the second frequency threshold and the average interrupt processing time is lower than the second time threshold, then the low-priority peripheral is determined to be the target peripheral, and the priority adjustment target of the target peripheral is to increase it.

[0092] The high-priority segment has at least one number, the low-priority segment has at least one number, and the peripheral corresponding to the high-priority segment has a higher priority than the peripheral corresponding to the low-priority segment.

[0093] Here, when no peripheral device initiates a priority adjustment request, the need for priority adjustment can be proactively judged, and proactively adjusted and restored, thereby improving the overall efficiency of the processor in handling interrupts from various peripheral devices and the utilization rate of interrupt resources.

[0094] The above detection can be performed periodically, for example, with a period of T, monitoring the frequency of high-priority peripherals initiating interrupt requests (such as peripherals in segments A and B mentioned above) within the time period T (denoted as req_freq_high), and the average interrupt processing time (denoted as T_high).

[0095] Furthermore, during the monitoring time period T, the frequency of interrupt requests initiated by low-priority peripherals (such as interrupt requests initiated by peripherals in segments C and D mentioned above) is denoted as req_freq_low, as well as the average interrupt processing time (denoted as T_high_low).

[0096] The judgment is based on frequency and average processing time, and the judgment principles are as follows:

[0097] High priority interrupt requests with low frequency and long interrupt processing times can be downgraded by one range.

[0098] Low priority interrupt requests with high frequency and short interrupt processing time can be increased by one range.

[0099] Specifically, regarding the judgment principle, the dynamic interrupt controller can determine whether a high-priority peripheral meets condition 1. If it does, the priority of that peripheral can be lowered by one interval. It can also determine whether a low-priority peripheral meets condition 2. If it does, the priority of that peripheral can be raised by one interval.

[0100] Condition 1: For high-priority segments (such as segments A and B), when the frequency of peripheral interrupt requests (i.e., req_freq_high) decreases and req_freq_high < the first frequency threshold (denoted as req_freq_high_threhlod), and when the average processing time of the peripheral interrupt (i.e., the execution time of the corresponding interrupt handler function) increases, such as T_high > the first time threshold (T_high_threhold), then the priority can be downgraded by one level.

[0101] For example, if the peripheral device's priority belongs to segment A, then its priority is lowered to segment B; if the peripheral device's priority belongs to segment B, then its priority is lowered to segment C.

[0102] The aforementioned thresholds, namely req_freq_high_threhlod and T_high_threhold, can use default values ​​or be configured by the user.

[0103] Condition 2: For low priority segments (such as segments C and D), when the frequency of peripheral interrupt requests (i.e., req_freq_low) increases, and req_freq_low > the second frequency threshold (denoted as req_freq_low_threhlod), and the average processing time of the interrupts of the peripheral (i.e., the execution time of the corresponding interrupt handler function) decreases, if T_low < the second time threshold (T_low_threhold), then the priority can be increased by one level.

[0104] For example, if the peripheral device priority belongs to segment C, then the interrupt priority is increased to segment A; if the peripheral device priority belongs to segment D, then the priority is decreased to segment B.

[0105] The aforementioned thresholds, namely req_freq_low_threhlod and T_low_threhold, can use default values ​​or be configured by the user.

[0106] In some embodiments, if the number of target peripherals is multiple, the method further includes:

[0107] Determine a first number of first target peripherals and a second number of second target peripherals, wherein the first target peripherals are peripherals with a high priority segment in the first priority segment, and the second target peripherals are peripherals with a low priority segment in the first priority segment;

[0108] If the first number is greater than the second number, then it is determined that only the priority of the second number of peripherals will be adjusted;

[0109] If the first quantity is less than the second quantity, determine to adjust the priorities of only the first quantity of peripherals;

[0110] Among them, the first quantity of peripherals or the second quantity of peripherals to be adjusted are screened based on the frequency of interrupt requests initiated by the peripherals and the average interrupt processing duration.

[0111] Here, if within the monitoring period T, the interrupts of multiple peripherals meet the above conditions, the multiple eligible peripherals perform a comprehensive active priority adjustment. For example, if there are 3 peripherals meeting the above conditions in segment A, 2 peripherals meeting the above conditions in segment C, and 1 peripheral meeting the above conditions in segment D, then lower the priorities of the 3 peripherals in segment A to segment B, transfer out 4 peripherals from segment B, where the priority of 1 peripheral is set to segment A, 2 peripherals are set to segment C, 1 peripheral is set to segment D, transfer out 2 peripherals from segment C and set them to segment A, and transfer out 1 peripheral from segment D and set it to segment B.

[0112] The principle of its active comprehensive priority adjustment can be:

[0113] Count the number of peripherals meeting condition 1 (i.e., the first target peripherals) (denoted as high_num) and the number of peripherals meeting condition 2 (i.e., the second target peripherals) (denoted as low_num);

[0114] If high_num > low_num, the number of peripherals whose priorities are actually adjusted = low_num, that is, no adjustment is made to the high_num - low_num high - priority peripherals.

[0115] If high_num < low_num, the number of peripherals whose priorities are actually adjusted = high_num, that is, no adjustment is made to the low_num - high_num low - priority peripherals.

[0116] For example, within the T time period, there are 7 high - priority peripherals meeting condition 1 and 5 low - priority peripherals meeting condition 2, then only adjust 5 low - priority peripherals to the high - priority segment. Among them, the 5 peripherals with increased priority should be the 5 with higher interrupt request frequency and shorter processing time on the basis of meeting condition 2. And the 5 peripherals with decreased priority should be the 5 with lower interrupt request frequency and longer processing time on the basis of meeting condition 1.

[0117] For example, within the T time period, there are 7 high - priority peripherals meeting condition 1 and 10 low - priority peripherals meeting condition 2, then only adjust 7 low - priority peripherals to the high - priority segment. Similarly, the 7 peripherals with decreased priority should be the 5 with lower interrupt request frequency and longer processing time on the basis of meeting condition 1.

[0118] In some embodiments, the method further includes:

[0119] The execution progress of the peripheral device whose priority has been adjusted is detected. If the peripheral device whose priority has been adjusted has finished executing, the peripheral device whose priority has been adjusted is restored to the first priority.

[0120] Here, the priority adjustment is subject to a time limit. After the processor core completes the processing of the corresponding peripheral, the priority of the peripheral needs to be restored to the priority range before the adjustment.

[0121] Figure 3 This is a schematic diagram of the structure of a processor that implements QoS performance, provided in an embodiment of this disclosure; as shown below. Figure 3 As shown, the processor includes: multiple processor cores, multiple interfaces (such as interface 0, interface 1, ..., interface N), a dynamic interrupt controller, a memory controller, and a critical process memory control module. The memory controller can control DDR, and each interface connects to one peripheral device.

[0122] The dynamic interrupt controller is used to dynamically adjust the priority of each peripheral device, make predictive adjustments, and promptly restore the adjusted status. Through the dynamic interrupt controller, it is ensured that critical peripheral processes (interrupt handlers) or critical peripheral processes within a specific time period can be processed promptly by the processor core, maximizing the timely processing of critical processes on all peripheral interfaces, improving the real-time performance of the processor core in processing critical peripheral processes, and enhancing the overall security of the CPU system.

[0123] like Figure 4 As shown, the dynamic interrupt controller may include: an interrupt comprehensive control module, an interrupt reordering module, and a priority active adjustment module. The interrupt comprehensive control module is used to segment the interrupt priorities of each peripheral device, obtaining multiple priority segments, and setting the priority adjustment range for each segment. The interrupt reordering module is used to receive interrupt request signals (denoted as irq_req) from each peripheral device, and to receive interrupt priority request signals (irq_up_req) from each peripheral device; and adjusts the priorities based on the interrupt request signals and interrupt priority request signals.

[0124] Here, in addition to transmitting the interrupt request signal irq_req to the dynamic interrupt controller, if the peripheral wants to increase the processing priority, it can transmit the interrupt priority request signal irq_up_req[1:0] to set the interrupt priority high, where [1:0] indicates that this is a binary signal. If the peripheral does not want to increase the processing priority, it sets irq_up_req=0 low. If irq_up_req is non-zero, the interrupt reordering module receives irq_req and irq_up_req, and determines the specific priority range of the current peripheral after the priority adjustment based on the dynamic adjustment range.

[0125] The priority proactive adjustment module is used to proactively determine the need for priority adjustment when the peripheral device does not initiate an interrupt priority elevation request, and then proactively adjust and restore the priority. This improves the overall efficiency of CPU interrupt handling and the utilization of interrupt resources.

[0126] In this embodiment of the disclosure, the interrupt priority of multiple peripheral processes of the processor CPU is dynamically managed and controlled by a dynamic interrupt controller. The interrupt priority of all peripherals is adjusted in segments, which greatly improves the flexibility of the processor interrupt handling and ensures that the processes of critical peripherals in the original default low-priority peripherals are processed in real time after the priority is adjusted, thus avoiding the drawbacks of blindly setting priorities.

[0127] In some embodiments, in response to a determined critical process, the instruction memory space of the critical process is accessed to determine the target instruction of the critical process, including:

[0128] In response to a identified critical process, a space estimation instruction is created for the critical process, the space estimation instruction indicating the offset address of the instruction in the critical process in memory;

[0129] The space estimation instruction is executed to obtain the instructions of the critical process and to obtain the target instruction from the obtained instructions, wherein the target instruction is an instruction that requires memory space to perform operations.

[0130] Here, critical processes can be set by the user. Each process has its own instruction and data storage space during runtime. After identifying critical processes, space estimation instructions can be created for them. These instructions can then be used to access the memory regions associated with the critical process in order to read its instructions. Furthermore, specific target instructions (i.e., instructions that require memory space to perform operations) can be identified from the process's instruction set to analyze each target instruction and the memory space required by the process during execution.

[0131] In one example, the processor may have a module that performs memory control over critical processes, such as... Figure 3The critical process memory control module enables precise allocation and dynamic adjustment of the memory space required by critical processes. This ensures the normal execution of critical processes while greatly reducing their impact on other regular processes in the processor, thus improving the actual utilization of memory.

[0132] like Figure 5 As shown, the critical process memory control module may include:

[0133] The estimation instruction creation module is used to create space estimated instructions for identified critical processes in response to those processes. The space estimated instructions can adopt the architecture shown in Table 2 below:

[0134] Table 2

[0135]

[0136] Among them, the [31:16] field represents offset_addr, which is the memory offset address of the instruction of the critical process. The [15:12] field represents rs1, which stores the number of the current critical process in a general-purpose register. The [11:7] field represents rs2, which stores the execution status of the current space estimation instruction. When the instruction is completed, this field is set to 1. When the value of this field is read by the software, this field is automatically reset to 0. The [6:0] field represents opcode, which is the opcode of the space estimation instruction and is a unique identifier used by the CPU instruction parsing unit to identify the instruction.

[0137] In some embodiments, the number of target instructions may be at least one, and the memory space required to detect the target instructions includes:

[0138] Determine the instruction type of each target instruction, and determine the memory space required for each target instruction based on its instruction type.

[0139] Here, based on the above example, the critical process memory control module may also include: a critical process instruction traversal module, used to execute space estimation instructions. This module accesses the instruction memory space of the critical process at the memory address (memory address = base address + offset_addr, where offset_addr is the offset address in memory) according to the space estimation instructions.

[0140] The base address is different in each system and can be set by the user. The target instruction (denoted as an S-type instruction) in the critical process is determined based on the value of the opcode field of the instruction in the instruction memory space. The possible values ​​of the opcode are binary 0100011, 0100011, and 0100011. The target instruction can adopt the architecture shown in Table 3 below:

[0141] Table 3

[0142]

[0143] In Table 3, rs1 represents the base address register (memory address = rs1 + sign-extended immediate value). rs2 represents the data source register to be stored. The immediate value is divided into two parts (imm[11:5] and imm[4:0]), which need to be concatenated and sign-extended in hardware.

[0144] The func3 field represents the specific instruction type. For example, func3=000 means storing 1 byte (8 bits); func3=001 means storing 2 bytes (16 bits); and func3=010 means storing a word (4 bytes, 32 bits).

[0145] By iterating through the target instructions (denoted as S-type instructions), space estimation is performed based on the value of the func3 field. When func3 = 000, the memory space required by the critical process (denoted as space_estimate) increases by 1 (in bytes); when func3 = 001, space_estimate increases by 2 (in bytes); and when func3 = 010, space_estimate increases by 4 (in bytes). The final estimated total memory space required by the critical process (space_estimate) is then obtained.

[0146] It should be noted that when encountering branch instructions during traversal, the opcode field value is 1100011. Traversal needs to be performed on each branch, ultimately resulting in multiple space_estimates, such as space_estimate_0, space_estimate_1, ..., space_estimate_N-1. The final estimated memory space value can be taken as the average.

[0147] space_estimate_average= (space_estimate_0+space_estimate_1+……space_estimate_N-1) / N.

[0148] The memory controller can allocate dedicated space to the current critical process based on the space_estimate_average.

[0149] In some embodiments, adjusting the memory space of the critical process based on unused dedicated space and the memory space required by the critical process includes:

[0150] The memory space of the critical process is adjusted based on the memory space required by the target instruction and the unused dedicated space, including:

[0151] Compare the memory space required by the unexecuted target instructions with the unused dedicated space;

[0152] If the memory space required by the unexecuted target instruction is less than the unused dedicated space, then the target size of memory space is released from the unused dedicated space, and the remaining dedicated space is used as the memory space for the critical process.

[0153] If the memory space required by the unexecuted target instruction is greater than the unused dedicated space, then add memory space of the target size to the unused dedicated space, and use the added dedicated space as the memory space of the critical process.

[0154] In some embodiments, the method further includes:

[0155] The freed memory space of the target size is allocated to regular processes in the processor.

[0156] Here, the dedicated space can be memory space allocated based on prior estimates, such as the dedicated space allocated based on space_estimate or space_estimate_average obtained from the aforementioned key process instruction traversal module.

[0157] Based on the above examples, the critical process memory control module may further include a margin dynamic control module, used to adjust the estimation results of the critical process instruction traversal module. Considering that the critical process instruction traversal module obtains an estimated value, that is, a relatively accurate estimate, such as estimating that a critical process requires 500MB of memory space, but the actual space required when the process is actually running may be 400MB or 600MB, blindly dividing the memory, such as allocating an excessively large space of 800MB, may lead to resource waste. Therefore, this disclosure provides a method to accurately converge the estimated memory space. Here, there will still be a margin between the estimated value of the critical process instruction traversal module and the actual space required by the critical process; the margin dynamic control module is specifically used to dynamically control this margin.

[0158] Determine whether the critical process meets the following conditions 3 and 4;

[0159] Condition 3: The estimated memory space required by the unexecuted S-type (i.e., target instruction) is less than the unused private space minus the target size of the memory space (denoted as space_dynamic).

[0160] If condition 3 is met, the memory controller will be notified in a timely manner to allocate space of size space_dynamic from the unused dedicated space for use by regular processes.

[0161] Condition 4: Estimated memory space required without executing S-type > unused private space + space_dynamic;

[0162] If the conditions are met, the memory controller should be notified promptly to allocate space of size space_dynamic for use by critical processes.

[0163] The value of space_dynamic can be set by the user or a default value, such as 50M, can be used.

[0164] For example, if the estimated memory space required for S-type execution is 200MB, and the unused dedicated space is 300MB, then condition 3 is met. In this case, the memory controller will allocate 50MB of space from the dedicated space for use by regular processes.

[0165] If the estimated memory space required for S-type execution is 300MB, and the unused dedicated space is 200MB, then condition 4 is met. In this case, the memory controller will allocate an additional 50MB of space for the critical process.

[0166] The above adjustments can be performed once or multiple times. For example, after updating or re-estimating the required memory space for S-type not being performed, the space can be judged and adjusted again based on the estimated value.

[0167] In this way, the memory space required by critical processes can be predicted to the greatest extent possible. The memory space required by critical processes can be accurately allocated and dynamically adjusted through the critical process memory control module. This ensures the normal execution of critical processes while greatly reducing the impact of critical processes on regular processes, improving the actual utilization of memory, and enhancing CPU QoS performance and overall performance.

[0168] It should be noted that either step 201 or step 202 can be executed, or they can be executed simultaneously or sequentially. There are no restrictions on the execution order or sequence.

[0169] Figure 6 This is a schematic diagram of the structure of a processing device provided in an embodiment of this disclosure; as shown below. Figure 6 As shown, the device is applied to a processor, which includes multiple processor cores and multiple peripheral interfaces. The peripheral interfaces are used to connect peripherals. The device includes:

[0170] The first processing module is used to receive interrupt requests and priority requests from peripheral devices, adjust the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device, and trigger the processor core to process the interrupt request according to the adjusted priority.

[0171] And / or,

[0172] The second processing module is configured to, in response to a determined critical process, access the instruction memory space of the critical process, determine the target instruction of the critical process, wherein the target instruction is an instruction involving memory operations; detect the memory space required by the target instruction; and adjust the memory space of the critical process based on the memory space required by the target instruction and unused dedicated space.

[0173] In some embodiments, the first processing module is used to determine whether the priority request is a priority promotion request or a priority maintenance request;

[0174] If the priority request is a priority upgrade request, determine the priority adjustment range of the peripheral according to the first priority segment to which the peripheral belongs, and determine the upgrade level corresponding to the priority upgrade request; adjust the priority of the peripheral from the first priority segment to the second priority segment according to the upgrade level and the priority adjustment range of the peripheral.

[0175] If the priority request is a priority maintenance request, the priority of the peripheral device remains unchanged.

[0176] In some embodiments, the first processing module is further configured to determine the number of peripherals connected to the processor;

[0177] Based on the number of peripherals, multiple peripherals are segmented to obtain multiple priority segments;

[0178] Set the priority adjustment range for each priority segment to obtain a priority adjustment range table;

[0179] Each priority segment includes at least one peripheral device, and the peripheral devices in different priority segments have different priorities.

[0180] Accordingly, the priority adjustment range of the peripheral is determined based on the first priority segment to which the peripheral belongs, including:

[0181] The priority adjustment range of the peripheral is determined by querying the priority adjustment range table according to the first priority segment to which the peripheral belongs.

[0182] In some embodiments, the first processing module is used to determine the priority adjustment range of each priority segment based on the principle that high priority segments are adjusted to lower priority segments to a first limit and low priority segments are adjusted to higher priority segments to an unlimited extent.

[0183] In some embodiments, the first processing module is further configured to detect the frequency of interrupt requests initiated by each of the peripheral devices and the average interrupt processing time, and determine the target peripheral devices with priority adjustment requirements based on the detection results;

[0184] The priority of the target peripheral is adjusted, and the processor core is triggered to process the interrupt request according to the adjusted priority.

[0185] In some embodiments, the first processing module is configured to determine that the high-priority peripheral is a target peripheral if the frequency of interrupt requests initiated by the high-priority peripheral is lower than a first frequency threshold and the average interrupt processing time is higher than a first time threshold, and the priority adjustment target of the target peripheral is to lower it.

[0186] If the frequency of interrupt requests initiated by a low-priority peripheral is higher than the second frequency threshold and the average interrupt processing time is lower than the second time threshold, then the low-priority peripheral is determined to be the target peripheral, and the priority adjustment target of the target peripheral is to increase it.

[0187] The high-priority segment has at least one number, the low-priority segment has at least one number, and the peripheral corresponding to the high-priority segment has a higher priority than the peripheral corresponding to the low-priority segment.

[0188] In some embodiments, the first processing module is configured to determine a first number of first target peripherals and a second number of second target peripherals if there are multiple target peripherals, wherein the first target peripheral is a peripheral with a high priority segment in the first priority segment, and the second target peripheral is a peripheral with a low priority segment in the first priority segment.

[0189] If the first number is greater than the second number, then it is determined that only the priority of the second number of peripherals will be adjusted;

[0190] If the first number is less than the second number, then it is determined that only the priority of the first number of peripherals will be adjusted;

[0191] The first or second number of peripherals to be adjusted are selected based on the frequency of interrupt requests initiated by the peripherals and the average interrupt processing time.

[0192] In some embodiments, the first processing module is further configured to detect the process execution progress of the peripheral device whose priority has been adjusted, and if the process of the peripheral device whose priority has been adjusted has been completed, restore the peripheral device whose priority has been adjusted to the first priority.

[0193] In some embodiments, the second processing module is configured to, in response to a determined critical process, create a space estimation instruction for the critical process, the space estimation instruction being used to indicate the offset address of the instruction of the critical process in memory;

[0194] The space estimation instruction is executed to obtain the instructions of the critical process and to obtain the target instruction from the obtained instructions, wherein the target instruction is an instruction that requires memory space to perform operations.

[0195] In some embodiments, the number of target instructions is at least one, and the second processing module is configured to determine the instruction type of each target instruction and determine the memory space required by the target instruction based on the instruction type of each target instruction.

[0196] In some embodiments, the second processing module is configured to compare the memory space required by the unexecuted target instruction with the unused dedicated space;

[0197] If the memory space required by the unexecuted target instruction is less than the first dedicated space, then the target size of memory space is released in the unused dedicated space, and the remaining dedicated space is used as the memory space for the critical process.

[0198] If the memory space required by the unexecuted target instruction is greater than the second dedicated space, then add memory space of the target size to the unused dedicated space, and use the added dedicated space as the memory space of the critical process;

[0199] Wherein, the first dedicated space is the unused dedicated space minus the target size of the memory space;

[0200] The second dedicated space is the space obtained by adding the target size of memory space to the unused dedicated space.

[0201] In some embodiments, the second processing module is further configured to allocate the freed target-size memory space to regular processes in the processor.

[0202] It is understood that, when implementing the corresponding processing method, the processing apparatus provided in the above embodiments can allocate the processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0203] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a processing method.

[0204] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and when executed by a processor, the processor will execute the processing method provided in this application.

[0205] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0206] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0207] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0208] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0209] Figure 7This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 7 As shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform:

[0210] The processor receives interrupt requests and priority requests from peripherals, adjusts the priority of the peripherals according to the priority request and the priority adjustment range corresponding to the peripherals, and triggers the processor core to process the interrupt request according to the adjusted priority.

[0211] And / or,

[0212] In response to a identified critical process, the instruction memory space of the critical process is accessed to determine the target instruction of the critical process, which is an instruction involving memory operations; the memory space required by the target instruction is detected; and the memory space of the critical process is adjusted based on the memory space required by the target instruction and unused dedicated space.

[0213] The electronic devices and corresponding processing methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0214] In practical applications, the electronic device 70 may further include at least one network interface 703. The various components of the electronic device 70 are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 All buses are labeled as bus system 704. The number of processors 701 and the number of memories 702 can be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

[0215] The memory 702 in this embodiment is used to store various types of data to support the operation of the electronic device 70.

[0216] The methods disclosed in the above embodiments of this disclosure can be applied to processor 701, or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in the form of software. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 702. Processor 701 reads the information in memory 702 and combines its hardware to complete the steps of the aforementioned processing method.

[0217] In some embodiments, the electronic device 70 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0218] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0219] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0220] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0221] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0222] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0223] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A processing method for a processor, characterized in that, The processor includes multiple processor cores and multiple peripheral interfaces, the peripheral interfaces being used to connect peripherals, and the method includes: The processor receives interrupt requests and priority requests from peripheral devices, adjusts the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device, and triggers the processor core to process the interrupt request according to the adjusted priority. The priority adjustment range represents the range of priorities that can be increased or decreased in priority management of the peripheral device. And / or, In response to a identified critical process, the instruction memory space of the critical process is accessed to determine the target instruction of the critical process, wherein the target instruction is an instruction involving memory operations; the memory space required by the target instruction is detected; and the memory space of the critical process is adjusted based on the memory space required by the target instruction and unused dedicated space. The memory space of the critical process is adjusted based on the memory space required by the target instruction and the unused dedicated space, including: Compare the memory space required by the unexecuted target instructions with the unused dedicated space; If the memory space required by the unexecuted target instruction is less than the first dedicated space, then the target size of memory space is released in the unused dedicated space, and the remaining dedicated space is used as the memory space for the critical process. If the memory space required by the unexecuted target instruction is greater than the second dedicated space, then add memory space of the target size to the unused dedicated space, and use the added dedicated space as the memory space of the critical process; Wherein, the first dedicated space is the unused dedicated space minus the target size of the memory space; The second dedicated space is the unused dedicated space plus the target size of the memory space.

2. The method according to claim 1, characterized in that, Based on the priority request and the priority adjustment range corresponding to the peripheral, the priority of the peripheral is adjusted, including: Determine whether the priority request is a priority promotion request or a priority maintenance request; If the priority request is a priority upgrade request, determine the priority adjustment range of the peripheral according to the first priority segment to which the peripheral belongs, and determine the upgrade level corresponding to the priority upgrade request; adjust the priority of the peripheral from the first priority segment to the second priority segment according to the upgrade level and the priority adjustment range of the peripheral. If the priority request is a priority maintenance request, the priority of the peripheral device remains unchanged.

3. The method according to claim 2, characterized in that, The method further includes: Determine the number of peripherals connected to the processor; Based on the number of peripherals, multiple peripherals are segmented to obtain multiple priority segments; Set the priority adjustment range for each priority segment to obtain a priority adjustment range table; Each priority segment includes at least one peripheral device, and the peripheral devices in different priority segments have different priorities. Accordingly, the priority adjustment range of the peripheral is determined based on the first priority segment to which the peripheral belongs, including: The priority adjustment range of the peripheral is determined by querying the priority adjustment range table according to the first priority segment to which the peripheral belongs.

4. The method according to claim 3, characterized in that, Setting the priority adjustment range for each priority segment includes: The priority adjustment range for each priority segment is determined based on the principle that high-priority segments are adjusted to lower-priority segments within a first limit, while low-priority segments are adjusted to higher-priority segments without limit.

5. The method according to claim 1, characterized in that, The method further includes: The frequency of interrupt requests initiated by each peripheral device and the average interrupt processing time are detected, and the target peripheral devices with priority adjustment needs are determined based on the detection results. The priority of the target peripheral is adjusted, and the processor core is triggered to process the interrupt request according to the adjusted priority.

6. The method according to claim 5, characterized in that, Based on the test results, target peripherals with priority adjustment requirements were identified, including: If the frequency of interrupt requests initiated by high-priority peripherals is lower than the first frequency threshold and the average interrupt processing time is higher than the first time threshold, then the high-priority peripherals are determined to be the target peripherals, and the priority adjustment target of the target peripherals is to reduce their priority. If the frequency of interrupt requests initiated by a low-priority peripheral is higher than the second frequency threshold and the average interrupt processing time is lower than the second time threshold, then the low-priority peripheral is determined to be the target peripheral, and the priority adjustment target of the target peripheral is to increase it. The high-priority segment has at least one number, the low-priority segment has at least one number, and the peripheral corresponding to the high-priority segment has a higher priority than the peripheral corresponding to the low-priority segment.

7. The method according to claim 5, characterized in that, If there are multiple target peripherals, the method further includes: Determine the first number of the first target peripheral and the second number of the second target peripheral, wherein the first target peripheral is a peripheral with a high priority segment in the first priority segment, and the second target peripheral is a peripheral with a low priority segment in the first priority segment; If the first number is greater than the second number, then it is determined that only the priority of the second number of peripherals will be adjusted; If the first number is less than the second number, then it is determined that only the priority of the first number of peripherals will be adjusted; The first or second number of peripherals to be adjusted are selected based on the frequency of interrupt requests initiated by the peripherals and the average interrupt processing time.

8. The method according to claim 1 or 5, characterized in that, The method further includes: The execution progress of the peripheral device whose priority has been adjusted is detected. If the peripheral device whose priority has been adjusted has finished executing, the peripheral device whose priority has been adjusted is restored to the first priority.

9. The method according to claim 1, characterized in that, In response to a identified critical process, the instruction memory space of the critical process is accessed to determine the target instruction of the critical process, including: In response to a identified critical process, a space estimation instruction is created for the critical process, the space estimation instruction indicating the offset address of the instruction in the critical process in memory; The space estimation instruction is executed to obtain the instructions of the critical process and to obtain the target instruction from the obtained instructions, wherein the target instruction is an instruction that requires memory space to perform operations.

10. The method according to claim 1, characterized in that, The number of target instructions is at least one, and the memory space required to detect the target instructions includes: Determine the instruction type of each target instruction, and determine the memory space required for each target instruction based on its instruction type.

11. The method according to claim 1, characterized in that, The method further includes: The freed memory space of the target size is allocated to regular processes in the processor.

12. A processing apparatus, characterized in that, The device is applied to a processor, the processor including multiple processor cores and multiple peripheral interfaces, the peripheral interfaces being used to connect peripherals, and the device comprising: The first processing module is used to receive interrupt requests and priority requests from peripheral devices, adjust the priority of the peripheral device according to the priority request and the priority adjustment range corresponding to the peripheral device, and trigger the processor core to process the interrupt request according to the adjusted priority; the priority adjustment range represents the range of priorities that can be increased or decreased in priority management of the peripheral device. And / or, The second processing module is configured to, in response to a determined critical process, access the instruction memory space of the critical process, determine the target instruction of the critical process, wherein the target instruction is an instruction involving memory operations; detect the memory space required by the target instruction; and adjust the memory space of the critical process based on the memory space required by the target instruction and unused dedicated space. The memory space of the critical process is adjusted based on the memory space required by the target instruction and the unused dedicated space, including: Compare the memory space required by the unexecuted target instructions with the unused dedicated space; If the memory space required by the unexecuted target instruction is less than the first dedicated space, then the target size of memory space is released in the unused dedicated space, and the remaining dedicated space is used as the memory space for the critical process. If the memory space required by the unexecuted target instruction is greater than the second dedicated space, then add memory space of the target size to the unused dedicated space, and use the added dedicated space as the memory space of the critical process; Wherein, the first dedicated space is the unused dedicated space minus the target size of the memory space; The second dedicated space is the unused dedicated space plus the target size of the memory space.

13. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 11.

Images