Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of core structures on the substrate, the core structures including a first core layer, a second core layer, and a third core layer, the first core layer and the second core layer being parallel to a first direction and having overlapping central axes in the first direction, the third core layer being parallel to a second direction, a first end of the second core layer being connected to one end of the first core layer and one end of the third core layer at the same time, and a second end being in contact with an adjacent third core layer; forming a word line structure on the substrate, the pattern of the word line structure being the pattern formed by the first core layer through self-aligned double patterning technology; forming a connection layer on the substrate, the connection layer corresponding to and being connected to the word line structure one by one, and the pattern of the connection layer being the pattern formed by the third core layer through self-aligned double patterning technology. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the development of flash memory, NOR (Not-OR) flash memory and NAND (Not-AND) flash memory are two types of flash memories that are widely used.

[0003] Among them, the NAND (Not-AND) flash memory adopts a non-linear macro cell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. The NAND (Not-AND) flash memory has the advantages of large capacity and fast rewrite speed, and is suitable for storing a large amount of data. Therefore, it has been increasingly widely used in the industry, such as in embedded products including digital cameras, MP3 player memory cards, and small-sized USB flash drives.

[0004] However, there are still some problems in the existing process for manufacturing NAND (Not-AND) flash type devices that need to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the process for manufacturing NAND (Not-AND) flash type devices.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of core structures on the substrate, the plurality of core structures being arranged at equal intervals, each core structure including a first core layer, a second core layer, and a third core layer, the first core layer and the second core layer being parallel to a first direction, and the central axes of the first core layer and the second core layer in the first direction coinciding, the third core layer being parallel to a second direction, the second core layer including a first end and a second end, the first end being simultaneously connected to one end of the first core layer and one end of the third core layer, the second end being in contact with an adjacent third core layer, the first direction and the second direction being parallel to the surface of the substrate, and the first direction and the second direction being perpendicular, the plurality of first core layers being arranged in parallel in the second direction, the plurality of second core layers being arranged in parallel in the second direction, the plurality of third core layers being arranged in parallel in the first direction, the second core layer being used to repair the edge critical effect when forming the first core layer and the third core layer; forming a word line structure on the substrate, the pattern of the word line structure being the pattern formed by the first core layer through self-aligned double patterning technology; forming a connection layer on the substrate, the connection layer corresponding to and being connected to the word line structure one by one, the pattern of the connection layer being the pattern formed by the third core layer through self-aligned double patterning technology.

[0007] Optionally, the core structure further includes: a plurality of fourth core layers. In the extending direction of any one of the first core layer and the second core layer, the plurality of fourth core layers are arranged at intervals in a first direction, and any one of the fourth core layers is located between adjacent third core layers. The fourth core layer can repair the edge critical effect when forming the first core layer and the third core layer.

[0008] Optionally, the method for forming the core structure includes: forming a core material layer on a substrate; forming a first mask layer on the core material layer, and the first mask layer exposes a part of the surface of the core material layer; etching the core material layer using the first mask layer as a mask until the surface of the substrate is exposed, thereby forming the core structure.

[0009] Optionally, the material of the first mask layer includes photoresist; the process for forming the first mask layer includes coating, exposure, and development processes.

[0010] Optionally, the word line structure and the connection layer are formed simultaneously.

[0011] Optionally, after forming the core structure, it further includes: removing the second core layer and the fourth core layer.

[0012] Optionally, the method for forming the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer and a second sidewall on the sidewall of the third core layer; after forming the first sidewall and the second sidewall, removing the first core layer and the third core layer; after removing the first core layer and the third core layer, forming a plurality of second mask layers on the second sidewall, and the plurality of second mask layers are parallel to a second direction and arranged in the first direction; etching the substrate using the first sidewall as a mask to form an initial word line structure; etching the substrate using the second mask layer and the second sidewall as a mask to form an initial connection layer; forming a first isolation layer in the initial word line structure, and the first isolation layer penetrates the initial word line structure in the first direction to make the initial word line structure form discrete word line structures; forming a second isolation layer in the initial connection layer, and the second isolation layer penetrates the initial connection layer in the second direction to make the initial connection layer form discrete connection layers, and one connection layer is connected to one word line structure.

[0013] Optionally, the material of the core structure includes silicon oxide or silicon nitride; the process for removing the core structure includes a wet etching process.

[0014] Optionally, the method for forming the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer, a second sidewall on the sidewall of the second core layer, a third sidewall on the sidewall of the third core layer, and a fourth sidewall on the sidewall of the fourth core layer; after forming the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall, removing the first core layer, the second core layer, the third core layer, and the fourth core layer; after removing the first core layer, the second core layer, the third core layer, and the fourth core layer, removing the second sidewall and the fourth sidewall; after removing the second sidewall and the fourth sidewall, forming a plurality of second mask layers on the third sidewall, the plurality of second mask layers being parallel to the second direction and arranged along the first direction; etching the substrate using the first sidewall as a mask to form an initial word line structure; etching the substrate using the second mask layer and the third sidewall as a mask to form an initial connection layer; forming a first isolation layer within the initial word line structure, the first isolation layer penetrating the initial word line structure along the first direction to form discrete word line structures; forming a second isolation layer within the initial connection layer, the second isolation layer penetrating the initial connection layer along the second direction to form discrete connection layers, and one connection layer being connected to one word line structure.

[0015] Optionally, the method for forming the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer, a second sidewall on the sidewall of the second core layer, a third sidewall on the sidewall of the third core layer, and a fourth sidewall on the sidewall of the fourth core layer; after forming the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall, removing the first core layer, the second core layer, the third core layer, and the fourth core layer; after removing the first core layer, the second core layer, the third core layer, and the fourth core layer, forming a plurality of second mask layers on the third sidewall, the plurality of second mask layers being parallel to the second direction and arranged along the first direction; etching the substrate using the first sidewall as a mask to form an initial word line structure; etching the substrate using the second mask layer and the third sidewall as a mask to form an initial connection layer; forming a first isolation layer within the initial word line structure, the first isolation layer penetrating the initial word line structure along the first direction to form discrete word line structures; forming a second isolation layer within the initial connection layer, the second isolation layer penetrating the initial connection layer along the second direction to form discrete connection layers, and one connection layer being connected to one word line structure.

[0016] Optionally, when etching the substrate using the first sidewall as a mask, it further includes: etching the substrate using the second sidewall and the fourth sidewall as a mask to form a pseudo word line structure; removing the pseudo word line structure.

[0017] Optionally, the material of the core structure includes amorphous silicon, silicon oxide, or silicon nitride.

[0018] Optionally, the material of the word line structure includes polysilicon or metal, and the metal includes tungsten; the material of the connection layer includes polysilicon or metal, and the metal includes tungsten.

[0019] Optionally, it further includes: forming a word line material layer on the substrate; the core structure is located on the word line material layer.

[0020] Optionally, before forming the word line material layer on the substrate, it further includes: forming a device layer on the substrate, where there are a plurality of floating gate structures arranged in parallel in the device layer, and the floating gate structures are parallel to the second direction; the word line material layer is located on the device layer.

[0021] Optionally, the floating gate structure includes a floating gate oxide layer and a floating gate layer located on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, and the metal includes tungsten.

[0022] Optionally, the device layer includes: a first dielectric layer, floating gate structures located in the first dielectric layer, and a word line oxide layer located on the first dielectric layer and on the floating gate structures.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the forming method of the present invention, by forming a plurality of core structures on the substrate, the first core layer and the second core layer are parallel to the first direction, and the central axes of the first core layer and the second core layer coincide in the first direction, the third core layer is parallel to the second direction, the second core layer includes a first end and a second end, the first end is simultaneously connected to one end of the first core layer and one end of the third core layer, and the second end is in contact with an adjacent third core layer. A second core layer is added between adjacent third core layers, so that the pattern density of the mask pattern forming the core structure increases between adjacent third core layers, and the pattern density of the mask pattern forming the first core layer increases on both sides in the second direction. The increased pattern of the second core layer increases the exposure degree of the area adjacent to the mask pattern forming the first core layer, so that the mask pattern of the first core layer can be accurately formed, reducing the situation where the first core layer is disconnected from the third core layer due to the influence of the optical proximity effect. Thus, the second core layer can repair the edge critical effect when forming the first core layer and the third core layer, and further improve the yield of the subsequent formed word line structure and connection layer.

[0025] Furthermore, a second core layer is added between adjacent third core layers. Meanwhile, in the extending direction of any of the first core layers and the second core layer, a number of fourth core layers are also added, so that the pattern density of the mask pattern forming the core structure is further increased between adjacent third core layers. The patterns of the added second core layer and the fourth core layer increase the exposure degree in the area adjacent to the mask pattern of the first core layer, so that the mask pattern of the first core layer can be accurately formed, reducing the situation where the first core layer is disconnected from the third core layer due to the influence of the optical proximity effect. Thus, the patterns of the added second core layer and the fourth core layer can repair the edge critical effect when forming the first core layer and the third core layer, thereby improving the yield of the subsequent formation of the word line structure and the connection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 and Figure 2 are schematic cross-sectional structure diagrams of the semiconductor structure formation process in an embodiment;

[0027] Figures 3 to 9 are schematic cross-sectional structure diagrams of the semiconductor structure formation process in an embodiment of the present invention;

[0028] Figures 10 to 12 are schematic cross-sectional structure diagrams of the semiconductor structure formation process in another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] As described in the background art, there are still some problems to be improved in the existing process of manufacturing NAND (negative AND) flash memory devices. The following is an analysis and description in combination with specific embodiments.

[0030] Figure 1 and Figure 2 are schematic cross-sectional structure diagrams of the semiconductor structure formation process in an embodiment.

[0031] Please refer to Figure 1 and Figure 2 , Figure 1 is Figure 2 the top view of Figure 2 is Figure 1Schematic cross-sectional structure diagram of the first core layer 107 along the section line AA1, including: a substrate 100; a floating gate structure located on the substrate 100, the floating gate structure including a floating gate oxide layer 101 and a floating gate layer 102 located on the floating gate oxide layer 101; source-drain doping regions 103 in the substrate 100 on both sides of the floating gate structure; a first dielectric layer 104 located on the substrate 100, the floating gate structure being located within the first dielectric layer 104; a word line oxide layer 105 located on the first dielectric layer 104 and on the floating gate structure; a second dielectric layer 106 located on the word line oxide layer 105; a core structure located on the second dielectric layer 106, the core structure including a first core layer 107 and a second core layer 108 that are perpendicular to each other and connected to each other, the first core layer 107 extending parallel to a first direction X, the second core layer 108 extending parallel to a second direction Y, the first direction X and the second direction Y being perpendicular, a plurality of the first core layers 107 being parallel to each other, and a plurality of the second core layers 108 being parallel to each other.

[0032] The first core layer 107 is used to form a first pattern layer on the second dielectric layer 106 by subsequent self-aligned double patterning technology (SADP), and the first pattern layer is used as a mask layer for etching the second dielectric layer 106 and forming a word line structure within the second dielectric layer 106. The second core layer 108 is used to form a second pattern layer on the second dielectric layer 106 by subsequent self-aligned double patterning technology (SADP), and the second pattern layer is used as a mask layer for etching the second dielectric layer 106 and forming a connection layer within the second dielectric layer 106. The method for forming the core structure includes: forming a core material layer on the second dielectric layer 106; forming a first mask layer on the core material layer, the first mask layer exposing a part of the surface of the core material layer; etching the core material layer using the first mask layer as a mask until the surface of the second dielectric layer 106 is exposed to form the core structure. The material of the first mask layer includes photoresist, and the process for forming the first mask layer includes coating, exposure, and development processes.

[0033] Due to design requirements, a plurality of the first core layers 107 are arranged parallel to the second direction Y, and a plurality of the second core layers 108 are arranged parallel to the first direction X. Therefore, at the position between the end position where the first core layer 107 is connected to the second core layer 108 and the edge of the substrate (such as Figure 1The shown area A) has no designed pattern, which makes the pattern density on both sides of the first core layer 107 uneven along the second direction Y. Therefore, during the process of exposing and forming the first mask layer, due to the influence of the optical proximity effect, the pattern at the end position where the first core layer 107 is connected to the second core layer 108 is difficult to be accurately exposed due to insufficient exposure. After subsequent development, the pattern of part of the first core layer 107 is disconnected from the pattern of the second core layer 108, resulting in a situation where the formed first core layer 107 and the second core layer 108 are not connected (as shown in area B in Figure 1 ), thus affecting the connection performance of the subsequent formed word line structure and the connection layer.

[0034] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure. By forming a plurality of core structures on a substrate, the first core layer and the second core layer are parallel to the first direction, and the central axes of the first core layer and the second core layer coincide in the first direction. The third core layer is parallel to the second direction. The second core layer includes a first end and a second end. The first end is simultaneously connected to one end of the first core layer and one end of the third core layer, and the second end is in contact with the adjacent third core layer. By adding a second core layer between adjacent third core layers, the pattern density of the mask pattern for forming the core structure between adjacent third core layers is increased, and the pattern density on both sides of the mask pattern for forming the first core layer in the second direction is increased. The added pattern for forming the second core layer increases the exposure degree of the area adjacent to the mask pattern for forming the first core layer, so that the mask pattern of the first core layer can be accurately formed, reducing the disconnection between the first core layer and the third core layer affected by the optical proximity effect, and thus improving the yield of the subsequent formed word line structure and connection layer.

[0035] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0036] Figures 3 to 9 It is a schematic structural diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0037] Please refer to Figure 3 , provide a substrate 200; form a device layer on the substrate 200, and there are a plurality of floating gate structures arranged in parallel along the first direction X in the device layer, and the floating gate structures are parallel to the second direction Y (as shown in Figure 4 ).

[0038] The device layer includes: a first dielectric layer 204, floating gate structures located in the first dielectric layer 204, and a word line oxide layer 205 located on the first dielectric layer 204 and on the floating gate structures.

[0039] The floating gate structure includes a floating gate oxide layer 201 and a floating gate layer 202 located on the floating gate oxide layer 201; the material of the floating gate oxide layer 201 includes silicon oxide, the material of the floating gate layer 202 includes polysilicon or metal, and the metal includes tungsten.

[0040] In this embodiment, the material of the substrate 200 is silicon.

[0041] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] The material of the first dielectric layer 204 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first dielectric layer 204 includes silicon oxide.

[0043] Please continue to refer to Figure 3 , a word line material layer 206 is formed on the device layer.

[0044] The word line material layer 206 is used to form a word line structure and a connection layer subsequently.

[0045] The material of the word line material layer 206 includes polysilicon or metal, and the metal includes tungsten. The process of forming the word line material layer 206 includes a physical vapor deposition process or a chemical vapor deposition process.

[0046] Please refer to Figure 4 and Figure 5 , Figure 4 is Figure 5 a top view of Figure 5 is Figure 4Schematic cross-sectional structure diagram of the first core layer 207 along the direction of section line BB1. A number of core structures are formed on the word line material layer 206, and the number of the core structures are arranged at equal intervals. The core structure includes a first core layer 207, a second core layer 209, and a third core layer 208. The first core layer 207 and the second core layer 209 are parallel to the first direction X, and the central axes of the first core layer 207 and the second core layer 209 coincide in the first direction X. The third core layer 208 is parallel to the second direction Y. The second core layer 209 includes a first end and a second end. The first end is simultaneously connected to one end of the first core layer 207 and one end of the third core layer 208, and the second end is in contact with the adjacent third core layer 208. The first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X and the second direction Y are perpendicular. A number of the first core layers 207 are arranged in parallel in the second direction Y, a number of the second core layers 209 are arranged in parallel in the second direction Y, and a number of the third core layers 208 are arranged in parallel in the first direction X.

[0047] The forming method of the core structure includes: forming a core material layer (not shown) on the word line material layer 206; forming a first mask layer (not shown) on the core material layer, and the first mask layer exposes part of the surface of the core material layer; etching the core material layer using the first mask layer as a mask until the surface of the word line material layer 206 is exposed to form the core structure.

[0048] The material of the first mask layer includes photoresist; the process of forming the first mask layer includes coating, exposure, and development processes.

[0049] Since the graphic size of the core structure is small, when the first mask layer pattern of the core structure is formed by exposure, the pattern of the first mask layer is easily affected by the optical proximity effect.

[0050] A second core layer 209 is added between adjacent third core layers 208, so that the graphic density of the mask pattern for forming the core structure increases between adjacent third core layers 208, and the graphic density of the mask pattern for forming the first core layer 207 increases on both sides in the second direction Y. The added pattern of the second core layer 209 increases the exposure degree of the area adjacent to the mask pattern for forming the first core layer 207, so that the mask pattern of the first core layer 207 can be accurately formed, reducing the situation that the first core layer 207 is disconnected from the third core layer 209 due to the influence of the optical proximity effect. Thus, the second core layer 209 can repair the edge critical effect when the first core layer 207 and the third core layer 209 are formed, and further improves the yield of the subsequent formed word line structure and connection layer.

[0051] In this embodiment, the core structure further includes: a plurality of fourth core layers 210. In the extending direction of any one of the first core layer 207 and the second core layer 209, the plurality of fourth core layers 210 are arranged at intervals along the first direction X, and any one of the fourth core layers 210 is located between adjacent third core layers 208.

[0052] A second core layer 209 is added between adjacent third core layers 208. At the same time, in the extending direction of any one of the first core layer 207 and the second core layer 209, a plurality of fourth core layers 210 are also added, so that the pattern density of the mask pattern forming the core structure between adjacent third core layers 208 is further increased. The pattern of the added second core layer 209 and the pattern of the fourth core layer 210 increase the exposure degree of the area adjacent to the mask pattern of the first core layer 207. Thus, the pattern of the added second core layer 209 and the pattern of the fourth core layer 210 can repair the edge critical effect when forming the first core layer 207 and the third core layer 209, so that the mask pattern of the first core layer 207 can be accurately formed, reducing the situation that the first core layer 207 is disconnected from the third core layer 209 due to the influence of optical proximity effect, and further improving the yield of the subsequent formation of the word line structure and the connection layer.

[0053] The material of the core structure includes amorphous silicon, silicon oxide or silicon nitride.

[0054] In this embodiment, the material of the core structure includes silicon oxide.

[0055] Next, a word line structure is formed on the substrate. The pattern of the word line structure is the pattern formed by the first core layer 207 through self-aligned double patterning technology; a connection layer is formed on the substrate. The connection layer corresponds to the word line structure one by one and is connected to each other. The pattern of the connection layer is the pattern formed by the third core layer 208 through self-aligned double patterning technology. For the formation process of the word line structure and the connection layer, please refer to Figures 6 to 9 .

[0056] Please refer to Figure 6 , and remove the second core layer 209 and the fourth core layer 210.

[0057] Remove the second core layer 209 and the fourth core layer 210 to avoid the situation that the patterns of the second core layer 209 and the fourth core layer 210 are subsequently transferred to the word line material layer 206 together with the first core layer 207 and the third core layer 208 to form a pseudo word line structure and need to be removed later. First, remove the second core layer 209 and the fourth core layer 210, so that the subsequently formed word line structure and connection layer will not be affected by the removal process.

[0058] The process of removing the second core layer 209 and the fourth core layer 210 includes a wet etching process.

[0059] The method of removing the second core layer 209 and the fourth core layer 210 includes: forming a patterned mask layer (not shown) on the core structure, the patterned mask layer exposing the second core layer 209 and the fourth core layer 210; removing the exposed second core layer 209 and the fourth core layer 210.

[0060] The material of the word line material layer 206 is different from that of the core structure, so that the core structure can be removed completely while causing less damage to the word line material layer 206.

[0061] Please refer to Figure 7 , forming a first sidewall 211 on the sidewall of the first core layer 207 and a second sidewall 212 on the sidewall of the third core layer 208; after forming the first sidewall 211 and the second sidewall 212, removing the first core layer 207 and the third core layer 208.

[0062] The method of forming the first sidewall 211 and the second sidewall 212 includes: forming a sidewall material layer (not shown) on the sidewall surface and the top surface of the first core layer 207 and on the sidewall surface and the top surface of the third core layer 208; back-etching the sidewall material layer until the top surfaces of the first core layer 207 and the third core layer 208 are exposed, forming the first sidewall 211 on the sidewall of the first core layer 207 and forming the second sidewall 212 on the sidewall of the third core layer 208.

[0063] The materials of the first sidewall 211 and the second sidewall 212 include a dielectric material, and the materials of the first sidewall 211 and the second sidewall 212 are different from the materials of the first core layer 207 and the third core layer 208. Thus, when back-etching the sidewall material layer, the back-etching process can stop at the surfaces of the first core layer 207 and the third core layer 208.

[0064] The materials of the first sidewall 211 and the second sidewall 212 include silicon, silicon oxide or silicon nitride.

[0065] In this embodiment, the materials of the first sidewall 211 and the second sidewall 212 include silicon nitride.

[0066] In this embodiment, the process of removing the first core layer 207 and the third core layer 208 includes a wet etching process.

[0067] Please refer to Figure 8 , forming a plurality of second mask layers 213 on the second sidewall 212, the plurality of second mask layers 213 being parallel to the second direction Y and arranged along the first direction X.

[0068] The width of the second mask layer 213 in the first direction X is greater than the width of the second sidewall 212, so that the second mask layer 213 can completely cover the second sidewall 212, and a connection layer with a larger size is formed subsequently, which is convenient for connection in subsequent processes.

[0069] In this embodiment, the material of the second mask layer 213 includes photoresist; the process of forming the second mask layer 213 includes coating, exposure and development processes.

[0070] Please refer to Figure 9 , using the first sidewall 211 as a mask to etch the word line material layer 206 to form an initial word line structure (not shown); using the second mask layer 213 and the second sidewall 212 as masks to etch the word line material layer 206 to form an initial connection layer (not shown); forming a first isolation layer 216 in the initial word line structure, the first isolation layer 216 penetrates the initial word line structure along the first direction X, so that the initial word line structure forms discrete word line structures 214; forming a second isolation layer 217 in the initial connection layer, the second isolation layer 217 penetrates the initial connection layer along the second direction Y, so that the initial connection layer forms discrete connection layers 215, and one of the connection layers 215 is connected to one of the word line structures 214.

[0071] The word line structures 214 and the connection layers 215 are formed simultaneously.

[0072] The first isolation layer 216 is used for electrically isolating the connected word line structures, so that the initial word line structure forms discrete word line structures 214; the second isolation layer 217 is used for electrically isolating the connected connection layers, so that the initial connection layer forms mutually discrete connection layers 215.

[0073] One of the connection layers 215 is connected to one of the word line structures 214, so that subsequently, it is possible to achieve the effect of being connected to the word line structure 214 by being connected to the connection layer 215. At the same time, the area of the connection layer 215 is relatively large, making the process window for forming the subsequent connection lines larger.

[0074] The material of the word line material layer 206 includes polysilicon or metal, so that the material of the word line structure 214 formed by the word line material layer 206 includes polysilicon or metal, and the metal includes tungsten; the material of the connection layer 215 formed by the word line material layer 206 includes polysilicon or metal, and the metal includes tungsten.

[0075] Figures 10 to 12 It is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure in another embodiment of the present invention.

[0076] Please refer to Figure 10 , Figure 10Schematic diagram based on Figure 4 A first sidewall 311 is formed on the sidewall of the first core layer 207, a second sidewall 313 is formed on the sidewall of the second core layer 209, a third sidewall 314 is formed on the sidewall of the third core layer 208, and a fourth sidewall 315 is formed on the sidewall of the fourth core layer 210.

[0077] The forming method of the first sidewall 311, the second sidewall 313, the third sidewall 314, and the fourth sidewall 315 includes: forming a sidewall material layer (not shown) on the sidewall surface and the top surface of the first core layer 207, the sidewall surface and the top surface of the second core layer 209, the sidewall surface and the top surface of the third core layer 208, and the sidewall surface and the top surface of the fourth core layer 210; etching back the sidewall material layer until the top surfaces of the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 210 are exposed, forming the first sidewall 311 on the sidewall of the first core layer 207, forming the second sidewall 313 on the sidewall of the second core layer 209, forming the third sidewall 314 on the sidewall of the third core layer 208, and forming the fourth sidewall 315 on the sidewall of the fourth core layer 210.

[0078] The materials of the first sidewall 311, the second sidewall 313, the third sidewall 314, and the fourth sidewall 315 include dielectric materials, and the materials of the first sidewall 311, the second sidewall 313, the third sidewall 314, and the fourth sidewall 315 are different from the materials of the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 210. Thus, when etching back the sidewall material layer, the etching back process can stop on the surfaces of the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 210.

[0079] The materials of the first sidewall 311, the second sidewall 313, the third sidewall 314, and the fourth sidewall 315 include silicon, silicon oxide, or silicon nitride.

[0080] In this embodiment, the materials of the first sidewall 311, the second sidewall 313, the third sidewall 314, and the fourth sidewall 315 include silicon nitride.

[0081] Please refer to Figure 11 , remove the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 209; after removing the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 210, remove the second sidewall 313 and the fourth sidewall 315.

[0082] In this embodiment, the process of removing the first core layer 207, the second core layer 209, the third core layer 208, and the fourth core layer 210 includes a wet etching process. The process of removing the second sidewall 313 and the fourth sidewall 315 includes a dry etching process or a wet etching process.

[0083] The method of removing the second sidewall 313 and the fourth sidewall 315 includes: forming a patterned mask layer (not shown) on the substrate, and the patterned mask layer exposes the second sidewall 313 and the fourth sidewall 315; removing the exposed second sidewall 313 and the fourth sidewall 315.

[0084] The material of the word line material layer 206 is different from that of the second sidewall 313 and the fourth sidewall 315, so that the second sidewall 313 and the fourth sidewall 315 can be removed cleanly while causing less damage to the word line material layer 206.

[0085] Removing the second sidewall 313 and the fourth sidewall 315 to avoid the situation where the patterns of the second sidewall 313 and the fourth sidewall 315 are simultaneously transferred to the word line material layer 206 to form a pseudo word line structure along with the first sidewall 311 and the third sidewall 314 in the subsequent process, and then the situation where it still needs to be removed. Removing the second sidewall 313 and the fourth sidewall 315 first, so that the subsequent formed word line structure and connection layer will not be affected by the removal process.

[0086] Please refer to Figure 12 , after removing the second sidewall 313 and the fourth sidewall 315, a plurality of second mask layers 316 are formed on the third sidewall 314, and the plurality of second mask layers 316 are parallel to the second direction Y and arranged along the first direction X.

[0087] The width of the second mask layer 316 in the first direction X is greater than the width of the third sidewall 314, so that the second mask layer 316 can completely cover the third sidewall 314 and the gap left by removing the second sidewall 313 and the fourth sidewall 315, and a connection layer with a larger size is formed subsequently, which is convenient for connection in the subsequent process.

[0088] In this embodiment, the material of the second mask layer 316 includes photoresist; the process of forming the second mask layer 316 includes coating, exposure, and development processes.

[0089] Next, using the first sidewall 311 as a mask, etch the word line material layer 206 to form an initial word line structure; using the second mask layer 316 and the third sidewall 314 as masks, etch the word line material layer 206 to form an initial connection layer (not shown); form a first isolation layer within the initial word line structure, the first isolation layer penetrating the initial word line structure along the first direction X, so that the initial word line structure forms discrete word line structures; form a second isolation layer within the initial connection layer, the second isolation layer penetrating the initial connection layer along the second direction Y, so that the initial connection layer forms discrete connection layers, and one of the connection layers is connected to one of the word line structures. For the specific formation process of the word line structures and connection layers, please refer to Figure 9 , which will not be elaborated here.

[0090] In another embodiment, on the basis of Figure 4 , the method for forming the word line structures and connection layers includes: forming a first sidewall on the sidewall of the first core layer, a second sidewall on the sidewall of the second core layer, a third sidewall on the sidewall of the third core layer, and a fourth sidewall on the sidewall of the fourth core layer; after forming the first sidewall, second sidewall, third sidewall, and fourth sidewall, remove the first core layer, second core layer, third core layer, and fourth core layer; after removing the first core layer, second core layer, third core layer, and fourth core layer, form a second mask layer on the third sidewall; using the first sidewall as a mask, etch the substrate to form an initial word line structure; using the second mask layer and the third sidewall as masks, etch the substrate to form an initial connection layer; form a first isolation layer within the initial word line structure, the first isolation layer penetrating the initial word line structure along the first direction, so that the initial word line structure forms discrete word line structures; form a second isolation layer within the initial connection layer, the second isolation layer penetrating the initial connection layer along the second direction, so that the initial connection layer forms discrete connection layers, and one of the connection layers is connected to one of the word line structures.

[0091] In another embodiment, when etching the substrate using the first sidewall as a mask, it further includes: etching the substrate using the second sidewall and the fourth sidewall as masks to form pseudo word line structures; removing the pseudo word line structures.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a plurality of core structures on the substrate, the plurality of core structures being arranged at equal intervals. The core structure includes a first core layer, a second core layer, and a third core layer. The first core layer and the second core layer are parallel to a first direction, and the central axes of the first core layer and the second core layer in the first direction coincide. The third core layer is parallel to a second direction. The second core layer includes a first end and a second end. The first end is simultaneously connected to one end of the first core layer and one end of the third core layer. The second end is in contact with an adjacent third core layer. The first direction and the second direction are parallel to the substrate surface, and the first direction and the second direction are perpendicular. A plurality of the first core layers are arranged in parallel in the second direction. A plurality of the second core layers are arranged in parallel in the second direction. A plurality of the third core layers are arranged in parallel in the first direction. The second core layer is used to repair the edge critical effect when forming the first core layer and the third core layer; Forming a word line structure on the substrate, the pattern of the word line structure being the pattern formed by the first core layer through self-aligned double patterning technology; Forming a connection layer on the substrate, the connection layer corresponding to and being connected to the word line structure one by one, the pattern of the connection layer being the pattern formed by the third core layer through self-aligned double patterning technology.

2. The method for forming a semiconductor structure according to claim 1, wherein The core structure further includes: a plurality of fourth core layers. In the extending direction of any one of the first core layer and the second core layer, a plurality of the fourth core layers are arranged at intervals in the first direction, and any one of the fourth core layers is located between adjacent third core layers. The fourth core layer can repair the edge critical effect when forming the first core layer and the third core layer.

3. The method for forming a semiconductor structure according to claim 2, wherein The forming method of the core structure includes: forming a core material layer on the substrate; forming a first mask layer on the core material layer, the first mask layer exposing a part of the surface of the core material layer; etching the core material layer using the first mask layer as a mask until the substrate surface is exposed to form the core structure.

4. The method for forming a semiconductor structure according to claim 3, wherein The material of the first mask layer includes photoresist; the process of forming the first mask layer includes coating, exposure, and development processes.

5. The method for forming a semiconductor structure according to claim 2, wherein, The word line structure and the connection layer are formed simultaneously.

6. The method for forming a semiconductor structure according to claim 5, wherein, After forming the core structure, it further includes: removing the second core layer and the fourth core layer.

7. The method for forming a semiconductor structure according to claim 6, wherein The forming method of the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer and a second sidewall on the sidewall of the third core layer; after forming the first sidewall and the second sidewall, removing the first core layer and the third core layer; after removing the first core layer and the third core layer, forming a plurality of second mask layers on the second sidewall, and the plurality of second mask layers are parallel to the second direction and arranged along the first direction; etching the substrate with the first sidewall as a mask to form an initial word line structure; etching the substrate with the second mask layer and the second sidewall as masks to form an initial connection layer; forming a first isolation layer in the initial word line structure, and the first isolation layer penetrates the initial word line structure along the first direction to make the initial word line structure form discrete word line structures; forming a second isolation layer in the initial connection layer, and the second isolation layer penetrates the initial connection layer along the second direction to make the initial connection layer form discrete connection layers, and one connection layer is connected to one word line structure.

8. The method for forming a semiconductor structure according to claim 7, wherein The material of the core structure includes silicon oxide or silicon nitride; the process of removing the core structure includes a wet etching process.

9. The method for forming a semiconductor structure according to claim 5, wherein, The forming method of the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer, a second sidewall on the sidewall of the second core layer, a third sidewall on the sidewall of the third core layer, and a fourth sidewall on the sidewall of the fourth core layer; after forming the first sidewall, the second sidewall, the third sidewall and the fourth sidewall, removing the first core layer, the second core layer, the third core layer and the fourth core layer; after removing the first core layer, the second core layer, the third core layer and the fourth core layer, removing the second sidewall and the fourth sidewall; after removing the second sidewall and the fourth sidewall, forming a plurality of second mask layers on the third sidewall, and the plurality of second mask layers are parallel to the second direction and arranged along the first direction; etching the substrate with the first sidewall as a mask to form an initial word line structure; etching the substrate with the second mask layer and the third sidewall as masks to form an initial connection layer; forming a first isolation layer in the initial word line structure, and the first isolation layer penetrates the initial word line structure along the first direction to make the initial word line structure form discrete word line structures; forming a second isolation layer in the initial connection layer, and the second isolation layer penetrates the initial connection layer along the second direction to make the initial connection layer form discrete connection layers, and one connection layer is connected to one word line structure.

10. The method for forming a semiconductor structure as described in claim 5, wherein, The forming method of the word line structure and the connection layer includes: forming a first sidewall on the sidewall of the first core layer, a second sidewall on the sidewall of the second core layer, a third sidewall on the sidewall of the third core layer, and a fourth sidewall on the sidewall of the fourth core layer; after forming the first sidewall, the second sidewall, the third sidewall and the fourth sidewall, removing the first core layer, the second core layer, the third core layer and the fourth core layer; after removing the first core layer, the second core layer, the third core layer and the fourth core layer, forming a plurality of second mask layers on the third sidewall, and the plurality of second mask layers are parallel to the second direction and arranged along the first direction; using the first sidewall as a mask to etch the substrate to form an initial word line structure; using the second mask layer and the third sidewall as masks to etch the substrate to form an initial connection layer; forming a first isolation layer in the initial word line structure, and the first isolation layer penetrates the initial word line structure along the first direction to make the initial word line structure form discrete word line structures; forming a second isolation layer in the initial connection layer, and the second isolation layer penetrates the initial connection layer along the second direction to make the initial connection layer form discrete connection layers, and one connection layer is connected to one word line structure.

11. The method for forming a semiconductor structure according to claim 9, wherein When using the first sidewall as a mask to etch the substrate, it further includes: using the second sidewall and the fourth sidewall as masks to etch the substrate to form a pseudo word line structure; removing the pseudo word line structure.

12. The method for forming a semiconductor structure according to claim 1, wherein The material of the core structure includes amorphous silicon, silicon oxide or silicon nitride.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the word line structure includes polysilicon or metal, and the metal includes tungsten; the material of the connection layer includes polysilicon or metal, and the metal includes tungsten.

14. The method for forming a semiconductor structure according to claim 1, wherein, It further includes: forming a word line material layer on the substrate; The core structure is located on the word line material layer.

15. The method for forming a semiconductor structure according to claim 14, wherein, Before forming the word line material layer on the substrate, it further includes: forming a device layer on the substrate, and the device layer has a plurality of parallel floating gate structures, and the floating gate structures are parallel to the second direction; the word line material layer is located on the device layer.

16. The method for forming a semiconductor structure according to claim 15, wherein, The floating gate structure includes a floating gate oxide layer and a floating gate layer on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, and the metal includes tungsten.

17. The method for forming a semiconductor structure according to claim 15, wherein The device layer includes: a first dielectric layer, floating gate structures in the first dielectric layer, and a word line oxide layer on the first dielectric layer and on the floating gate structures.

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