A quantum well structure and a manufacturing method thereof

Abstract

The present application provides a quantum well structure and a manufacturing method thereof, including a substrate, on which a first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate are sequentially stacked, a bottom gate located on the substrate and in contact with the first barrier layer, an aluminum layer located on the first side sidewalls of the first quantum well layer and the second quantum well layer, and further including a first electrode located on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode located on the third side sidewall of the second quantum well layer, where the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively. A superfluid phase under Bose-Einstein condensation is generated through the coupling between the quantum well layers. Since an aluminum layer is provided on the sidewalls of the quantum well, the coupling of the superfluid phase with the superconducting lead is realized, ensuring a clear coupling interface, and creating a high-quality quantum well structure with a clear interface for studying the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology.

Description

Technical Field

[0001] The present invention relates to the field of quantum wells and their manufacturing, and particularly to a quantum well structure and a manufacturing method thereof. Background Art

[0002] Currently, an intrinsic double quantum well is a key semiconductor structure for generating superfluid (counter flow) / Bose-Einstein condensate (BEC). At the same time, the closely coupled and spaced double well structures have foreseeable extremely high coupling mobilities and fractional quantum Hall effects. The superconducting-semiconductor double quantum well heterostructure made into superconducting-double well-superconducting (S-DQW-S or S-BEC / counterflow-S) has superconducting-semiconductor / superfluid hybrid characteristics, and ballistic transport and mesoscopic transport effects that have never appeared can be observed. However, due to the lack of a high-quality material system, the quality of the superconducting-quantum well contact interface is crucial. There is still a difficulty in strong uniform long-range coupling, so that the grown double well structure cannot be used to study the fractional quantum Hall effect. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a quantum well structure and a manufacturing method thereof, aiming to create a quantum well structure with high quality and clear interfaces.

[0004] To achieve the above purpose, this application has the following technical solutions:

[0005] A quantum well structure, comprising:

[0006] A substrate;

[0007] A first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate stacked in sequence on the substrate;

[0008] A bottom gate located on the substrate and in contact with the first barrier layer;

[0009] An aluminum layer located on the first side sidewalls of the first quantum well layer and the second quantum well layer;

[0010] A first electrode located on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode located on the third side sidewall of the second quantum well layer, where the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively.

[0011] Optionally, a buffer layer is provided between the substrate and the first barrier layer. The buffer layer is doped, the buffer layer is in contact with the bottom gate, and the bottom gate is located in other regions outside the projection area of the first barrier layer on the substrate.

[0012] Optionally, the material of the substrate is silicon;

[0013] When the material of the first quantum well layer is silicon, the silicon element content in the buffer layer gradually decreases from bottom to top, and the germanium content gradually increases; when the material of the first quantum well layer is germanium, a germanium material layer is further included between the substrate and the buffer layer, and the silicon element in the buffer layer gradually increases from bottom to top, and the germanium content gradually decreases.

[0014] Optionally, the material of the second quantum well layer is silicon or germanium;

[0015] When the materials of the second quantum well layer and the first quantum well layer are the same, an isolation layer is provided between the first quantum well layer and the second quantum well layer; when the materials of the second quantum well layer and the first quantum well layer are different, an isolation layer is provided between the first quantum well layer and the second quantum well layer, or the first quantum well layer and the second quantum well layer are in direct contact.

[0016] Optionally, the aluminum layer also covers the fourth sidewalls of the first quantum well layer and the second quantum well layer, and the first sidewall and the fourth sidewall are opposite sidewalls.

[0017] Optionally, the aluminum layer also covers the first sidewalls of the first barrier layer and the second barrier layer, the fourth sidewalls of the first barrier layer and the second barrier layer, and a part of the upper surface of the second barrier layer. There is a dielectric layer between the aluminum layer and the top gate, and the dielectric layer covers a part of the upper surface of the second barrier layer.

[0018] Optionally, the second sidewalls of the first quantum well layer and the second quantum well layer are doped with a first doping type, and the third sidewalls of the second quantum well layer are doped with a second doping type.

[0019] The embodiment of the present application also provides a manufacturing method of a quantum well structure, including:

[0020] Providing a substrate;

[0021] Forming a first barrier layer, a first quantum well layer, a second quantum well layer, and a second barrier layer stacked in sequence on the substrate;

[0022] Forming an aluminum layer on the first sidewalls of the first quantum well layer and the second quantum well layer, forming a first electrode on the second sidewalls of the first quantum well layer and the second quantum well layer, forming a second electrode on the third sidewalls of the second quantum well layer, forming a top gate on the second barrier layer, and forming a bottom gate on the substrate and in contact with the first barrier layer. The second sidewall and the third sidewall are adjacent to the first sidewall respectively.

[0023] Optionally, the method further includes:

[0024] Before forming the first barrier layer on the substrate, a buffer layer is formed on the substrate. The buffer layer is doped and is used for bottom gate contact. The bottom gate is located in an area other than the projection area of the first barrier layer on the substrate.

[0025] Optionally, the material of the substrate is silicon;

[0026] When the material of the first quantum well layer is silicon, the silicon element content in the buffer layer gradually decreases from bottom to top, and the germanium content gradually increases; when the material of the first quantum well layer is germanium, a germanium material layer is further included between the substrate and the buffer layer, and the silicon element in the buffer layer gradually increases from bottom to top, and the germanium content gradually decreases.

[0027] Optionally, the material of the second quantum well layer is silicon or germanium;

[0028] When the materials of the second quantum well layer and the first quantum well layer are the same, an isolation layer is provided between the first quantum well layer and the second quantum well layer; when the materials of the second quantum well layer and the first quantum well layer are different, an isolation layer is provided between the first quantum well layer and the second quantum well layer, or the first quantum well layer and the second quantum well layer are in direct contact.

[0029] Optionally, the aluminum layer also covers the fourth sidewalls of the first quantum well layer and the second quantum well layer, and the first sidewall and the fourth sidewall are opposite sidewalls.

[0030] Optionally, the aluminum layer also covers the first sidewalls of the first barrier layer and the second barrier layer, the fourth sidewalls of the first barrier layer and the second barrier layer, and a partial upper surface of the second barrier layer. Before forming the top gate on the second barrier layer, a dielectric layer is formed on the second barrier layer, and the dielectric layer covers a partial upper surface of the second barrier layer.

[0031] Optionally, the second sidewalls of the first quantum well layer and the second quantum well layer are doped with a first doping type, and the third sidewall of the second quantum well layer is doped with a second doping type.

[0032] An embodiment of the present application provides a quantum well structure and a manufacturing method thereof. First, it includes a substrate, on which a first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate are sequentially stacked. It includes a bottom gate located on the substrate and on the side of the first barrier layer facing the substrate. It includes an aluminum layer located on the first side sidewalls of the first quantum well layer and the second quantum well layer, and also includes a first electrode located on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode located on the third side sidewall of the second quantum well layer. The second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively. A superfluid phase in Bose-Einstein condensation is generated through the coupling between the quantum well layers. Since an aluminum layer is provided on the first side sidewalls of the first quantum well layer and the second quantum well layer, the formation process of the aluminum layer is simple and it is easy to form a high-quality film layer, realizing the coupling of the superfluid phase with a superconducting lead and ensuring a clear coupling interface, creating a high-quality quantum well structure with a clear interface that can be used to study the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1A Schematic diagram of a quantum well structure provided by an embodiment of the present application;

[0035] Figure 1B is Figure 1A Cross-sectional view of a quantum well structure provided in the aa direction;

[0036] Figure 1C is Figure 1A Cross-sectional view of a quantum well structure provided in the bb direction;

[0037] Figure 2A 、 Figure 2B 、 Figure 2C Schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0038] Figure 3A 、 Figure 3B 、 Figure 3C Schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0039] Figure 4A 、 Figure 4B 、 Figure 4C Schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0040] Figure 5A 、 Figure 5B 、 Figure 5C is a schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0041] Figure 6 is a schematic flow chart of a manufacturing method of a quantum well structure provided by an embodiment of the present application;

[0042] Figure 7A 、 Figure 7B 、 Figure 7C is a schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0043] Figure 8A 、 Figure 8B 、 Figure 8C is a schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0044] Figure 9A 、 Figure 9B 、 Figure 9C is a schematic diagram of another quantum well structure provided by an embodiment of the present application;

[0045] Figure 10A 、 Figure 10B 、 Figure 10C is a schematic diagram of another quantum well structure provided by an embodiment of the present application. Detailed Embodiments

[0046] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed embodiments of the present application in conjunction with the accompanying drawings.

[0047] In the following description, many specific details are set forth to fully understand the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0048] Secondly, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the sake of clarity, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0049] At present, the S-DQW-S made of a superconducting-semiconductor double quantum well heterostructure has superconducting-semiconductor / superfluid hybrid characteristics, and ballistic transport and mesoscopic transport effects that have never appeared can be observed. However, due to the lack of a high-quality material system, the quality of the superconducting-quantum well contact interface is crucial. There is still a difficulty in strong uniform long-range coupling, so that the grown double-well structure cannot be used to study the fractional quantum Hall effect.

[0050] Based on the above technical problems, the embodiments of the present application provide a quantum well structure and a manufacturing method thereof, including a substrate, on which a first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate are sequentially stacked, a bottom gate located on the substrate and in contact with the first barrier layer, an aluminum layer located on the first side sidewalls of the first quantum well layer and the second quantum well layer, a first electrode located on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode located on the third side sidewall of the second quantum well layer, where the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively. A superfluid phase in Bose-Einstein condensation is generated through the coupling between the quantum well layers. Since an aluminum layer is provided on the first side sidewalls of the first quantum well layer and the second quantum well layer, the formation process of the aluminum layer is simple and it is easy to form a high-quality film layer, realizing the coupling of the superfluid phase with the superconducting lead and ensuring a clear coupling interface, creating a high-quality, clear-interface quantum well structure that can be used to study the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology.

[0051] See Figure 1A 、 Figure 1B and Figure 1C , which are schematic structural diagrams of a quantum well structure provided by the embodiments of the present application. Among them, Figure 1A is a top view of the quantum well structure, Figure 1B is Figure 1A a cross-sectional view of the quantum well structure in the aa direction in Figure 1C is Figure 1A a cross-sectional view of the quantum well structure in the bb direction in

[0052] The substrate 11 is used to provide support for the film layers thereon. The material of the substrate 11 can be at least one of silicon and germanium, or other semiconductor materials and their combinations.

[0053] A first barrier layer 12, a first quantum well layer 13, a second quantum well layer 14, a second barrier layer 15, and a top gate 16 are sequentially stacked on a substrate 11. Among them, the first quantum well layer 13 and the second quantum well layer 14 serve as active layers. When their thicknesses are thinned to the order of the Bohr radius or the de Broglie wavelength, the quantum size effect appears. At this time, carriers are confined in the potential wells formed by the active layers, and such potential wells are called quantum wells. A quantum well is a narrow-bandgap ultra-thin layer sandwiched between two wide-bandgap barrier thin layers, which are respectively denoted as the first barrier layer 12 and the second barrier layer 15. The first barrier layer 12 can also be called the lower constant component layer, and the second barrier layer 15 can also be called the upper constant component layer. The materials of the first barrier layer 12 and the second barrier layer 15 can be Si 1-x Ge x alloy materials. The first quantum well layer 13 and the second quantum well layer 14 form a double quantum well layer, which is the key semiconductor structure for generating superfluid (counter flow) / Bose-Einstein condensate (BEC). The double-well structure has characteristics such as high mobility, low penetration density, and large symmetric-antisymmetric energy gaps. The material of the first quantum well layer 13 can be silicon or germanium, and the material of the second quantum well layer 14 can be silicon or germanium. The materials of the first quantum well 13 and the second quantum well 14 can be the same or different. The top gate 16 is used to apply a voltage to the upper surface of the second barrier layer 15. The material of the top gate 16 can be a material with good conductivity, such as titanium or aluminum, etc.

[0054] A bottom gate 17 located on the substrate 11 and in contact with the first barrier layer 12. The top gate and the bottom gate are used to achieve gate control for the double-well structure, enabling double quantum dot entanglement (superfluid / inverse flow quantum phenomenon) to occur in the double well, so as to achieve multiple Andreev reflections or singular quantum effects of superconducting-superfluid contact, or to achieve a longer superconducting induction gap and a more obvious gate-controlled transport current. The bottom gate 17 is used to apply a voltage to the lower surface of the first barrier layer 12. The bottom gate 17 can be located between the substrate 11 and the first barrier layer 12; the bottom gate 17 can also be used to apply a voltage to the upper surface of the first barrier layer 12. At this time, the bottom gate 17 is located above the first barrier layer 12. At this time, the area of the first barrier layer 12 is larger than the sum of the areas of the bottom gate 17 and the first quantum well layer 13. The first quantum well layer 13 and the bottom gate 17 are located in different regions on the first barrier layer 12.

[0055] An aluminum layer 18 located on the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14 is used as a superconducting lead. Combined with the superfluid generated by the double quantum well, the aluminum superconducting contact double-well structure becomes a "spacer layer" for superconducting tunneling, making this quantum well a high-quality and clear-interface quantum well structure that can be used to study the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology. The S-DQW-S made of a superconducting-semiconductor double quantum well heterostructure has superconducting-semiconductor / superfluid hybrid characteristics, and ballistic transport and mesoscopic transport effects that have never appeared can be observed. On the basis of ensuring a clear coupling interface, a double-well structure with high mobility, low penetration density, and a large symmetric-antisymmetric energy gap can be obtained, as well as a brand-new substrate platform for studying the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology and vertical-gated 3D quantum dots. A substrate platform that can stably observe the gated transport current and quantum effects can also be obtained; the aluminum layer 18 can only cover the first side sidewalls of the first quantum well 13 and the second quantum well 14, or can cover the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, as well as the fourth side sidewalls, and the first side sidewalls and the fourth side sidewalls are opposite sidewalls.

[0056] A first electrode 19 located on the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, and a second electrode 20 located on the third side sidewalls of the second quantum well layer 14. One of the first electrode 19 and the second electrode 20 is the source electrode, and the other is the drain electrode. Among them, the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively, and the second side sidewall and the third side sidewall are opposite sidewalls. In Figure 1A , 1B and 1C, the first side sidewall and the fourth side sidewall are respectively parallel to the bb direction, and the second side sidewall and the third side sidewall are both parallel to the aa direction.

[0057] Among them, the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14 are doped with the first doping type, and the first electrode 19 is provided on the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14. The third side sidewalls of the second quantum well layer 14 are doped with the second doping type, and the second electrode 20 is formed on the third side sidewalls of the first quantum well layer 13 and the second quantum well layer 14. Among them, the first doping type is P-type heavy doping P++, and the second doping type is N-type heavy doping N++. One of the first electrode 19 and the second electrode 20 is the source level, and the other is the drain level. The first electrode 19 and the second electrode 20 serve as contact source and drain, and are used to jointly regulate the generation of superfluid or strong Coulomb interaction in the quantum well structure in combination with the top gate and the bottom gate.

[0058] The aluminum layer 18 may only cover the sidewalls of the first quantum well layer 13 and the second quantum well layer 14, or may also cover the sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. That is to say, when the aluminum layer 18 covers the first sidewalls of the first quantum well layer 13 and the second quantum well layer 14, it may also cover the first sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. When the aluminum layer 18 covers the fourth sidewalls of the first quantum well layer 13 and the second quantum well layer 14, it may also cover the fourth sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. In addition, the aluminum layer 18 may also cover a part of the upper surface of the second barrier layer 15. Among them, Figure 1B The figure shows a schematic diagram of a quantum well structure when the aluminum layer 18 covers the first sidewalls of the first quantum well layer 13 and the second quantum well layer 14, and also covers the first sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time, and the bottom gate 17 is located between the substrate 11 and the first barrier layer 12.

[0059] Optionally, refer to Figure 2A 、 Figure 2B and Figure 2C , which is a schematic diagram of another quantum well structure provided by the embodiment of the present application. Figure 2A is a top view of the quantum well structure. Figure 2B is Figure 2A a cross-sectional view of the quantum well structure in the aa direction in. The aluminum layer 18 covers the first sidewalls and the fourth sidewalls of the first quantum well layer 13 and the second quantum well layer 14, as well as the first sidewalls and the fourth sidewalls of the first barrier layer 12 and the second barrier layer 15, enhancing the action range of the superconducting lead. The aluminum layer 18 is used to combine the double-well structure and the aluminum superconducting lead to realize a superconducting-superfluid hybrid quantum device, so as to prepare a substrate platform that can stably observe the gate-controlled transport current and quantum effects.

[0060] The graphic top view of the substrate platform in the embodiment of the present application may be rectangular, square, rhombic or circular, and the whole may be a cuboid, cylinder, frustum or cone, that is, the quantum well structure composed of the substrate 11, the first barrier layer 12, the first quantum well layer 13, the second quantum well layer 14, the second barrier layer 15 and the top gate 16 may be a cuboid, cylinder, frustum or cone, etc., and the top view may be rectangular, square, rhombic or circular, etc. In the embodiment of the present application, the case where the top view is rectangular is taken as an example for illustration. Of course, the graphic structure of the substrate platform is not specifically limited in the present application, which does not affect the implementation of the embodiment of the present application. In the embodiment of the present application, it is convenient to display the structure between the substrate platforms, and the rectangle is taken as an example for graphic display.

[0061] When the aluminum layer 18 covers the upper surface of a part of the second barrier layer 15, in order to achieve insulation between the aluminum layer 18 and the top gate 16, a dielectric layer 24 can be provided between the aluminum layer 18 and the top gate 16. The aluminum layer 18 covers the upper surface of a part of the second barrier layer 15, the dielectric layer 24 covers the remaining surface of the second barrier layer 15, the bottom surface of the dielectric layer 24 is in contact with the aluminum layer 18 for isolating the aluminum layer 18 and the top gate 16. The material of the dielectric layer 24 can be an insulating material such as an oxide or a nitride, or a semiconductor material such as intrinsic silicon or intrinsic germanium.

[0062] In the embodiments of the present application, when the materials of the substrate 11 and the first barrier layer 12 are inconsistent, for example, the material of the substrate 11 is silicon (100) and the material of the first barrier layer 12 is silicon germanium, due to the large lattice mismatch between silicon and germanium, it is extremely difficult to grow a high-quality and clear-interface double-well structure on the silicon substrate. Due to the requirements of interlayer coupling and superconducting long-range coupling, the difficulty of growing a high-quality superconducting double-well structure is further increased. If the first barrier layer 12 is directly formed on the substrate 11, due to the dislocations between the substrate 11 and the first barrier layer 12, the formation quality of the first barrier layer 12 is affected. At this time, a buffer layer 21 can be provided between the substrate 11 and the first barrier layer 12, so that the double quantum well thereon has the characteristics of high quality, high clarity and low dislocation.

[0063] Optionally, referring to Figure 3A 、 Figure 3B and Figure 3C , which is another schematic diagram of the quantum well structure provided by the embodiments of the present application. Figure 3A is a top view of the quantum well structure. Figure 3B is Figure 3A the cross-sectional view of the quantum well structure in the aa direction in Figure 3C is Figure 3A the cross-sectional view of the quantum well structure in the bb direction in Figure 3A . A buffer layer 21 is provided between the substrate 11 and the first barrier layer 12. The buffer layer 21 is doped and can be in contact with the bottom gate 17. The bottom gate 17 is located in other regions outside the projection area of the first barrier layer 12 on the substrate 11 and can be located on the side of the buffer layer 21, as shown in

[0064] When the material of the first quantum well layer 13 is silicon, the silicon element content in the buffer layer 21 gradually decreases from bottom to top, and the germanium content gradually increases. As a silicon-germanium forward graded layer (SiGe FG) or a forward silicon-germanium virtual substrate, there is more silicon element below the buffer layer 21, so the dislocation between the buffer layer 21 and the substrate 11 is smaller. There is more germanium element above, so the dislocation between the buffer layer 21 and the first barrier layer 12 is smaller, making the quality of the first barrier layer 12 less affected by dislocations and facilitating the formation of a first barrier layer 12 with higher quality. When the material of the first quantum well layer 13 is germanium, the silicon element content in the buffer layer 21 gradually increases from bottom to top, and the germanium content gradually decreases. As a silicon-germanium reverse graded layer (SiGe RG) or a reverse silicon-germanium virtual substrate, there is more silicon element above the buffer layer 21, so the dislocation between the buffer layer 21 and the first barrier layer 12 is smaller, making the quality of the first barrier layer 12 less affected by dislocations and facilitating the formation of a first barrier layer 12 with higher quality.

[0065] When the material of the first quantum well layer 13 is germanium, due to the higher germanium content below the buffer layer 21, a relatively large dislocation is likely to occur between the buffer layer 21 and the substrate 11. Therefore, a germanium material layer 22 can be provided between the substrate 11 and the buffer layer 21. The germanium material layer 22 includes a low-temperature germanium layer on the side facing the substrate 11 and a high-temperature germanium layer on the side facing the buffer layer 21, so that it can act as a buffer between the substrate 11 and the buffer layer 21, facilitating the formation of a high-quality buffer layer 21, and enabling the double quantum well thereon to have the characteristics of high quality, high clarity, and low dislocation.

[0066] Optionally, referring to Figure 4A 、 Figure 4B and Figure 4C which is another schematic diagram of the quantum well structure provided by the embodiment of the present application. A germanium material layer 22 is further included between the substrate 11 and the buffer layer 21. The buffer layer 21 is in contact with the bottom gate 17, and the bottom gate 17 is located in other regions outside the projection area of the first barrier layer 12 on the germanium material layer 22, and can be located on the side of the buffer layer 21. The substrate 11 and the germanium material layer 22 can protrude from the side of the buffer layer 21, and the protruding part serves as a support for the bottom gate 17.

[0067] Optionally, in the embodiment of the present application, when the materials of the first quantum well layer 13 and the second quantum well layer 14 are the same, referring to Figure 5A 、 Figure 5B and Figure 5C, which is another schematic diagram of the quantum well structure provided by the embodiments of the present application. An isolation layer 23 is provided between the first quantum well layer 13 and the second quantum well layer 14. The material of the isolation layer 23 can be silicon germanium. The isolation layer 23 is used to separate two quantum well layers of the same material, forming different types of quantum well structures. When the materials of the first quantum well layer 13 and the second quantum well layer 14 are different, an isolation layer 23 can be provided between the first quantum well layer 13 and the second quantum well layer 14, or the first quantum well layer 13 and the second quantum well layer 13 are in direct contact. Among them, Figure 1A , Figure 1B , Figure 1C to Figure 4A , Figure 4B , Figure 4C in the schematic diagram of the quantum well structure shown, the first quantum well layer 13 and the second quantum well layer 13 are in direct contact.

[0068] When there is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, the first quantum well layer 13 and the second quantum well layer 14 form an interval quantum well structure. When the first quantum well layer 13 and the second quantum well layer 14 are in direct contact without an isolation layer 23, the first quantum well layer 13 and the second quantum well layer 14 form a tightly bound quantum well structure. The tightly structured quantum well structure and the interval quantum well structure can enable the coupling of double quantum wells to generate a superfluid phase under Bose-Einstein (BEC) condensation, with predictable extremely high coupling mobility and fractional quantum Hall effect. As an example, when the materials of both the first quantum well layer 13 and the second quantum well layer 14 are silicon, the carriers in the quantum well structure are mainly electrons. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, and the isolation layer 23 can be made of silicon germanium material. The quantum well structure is an interval (Si-Si) electron double well structure; when the materials of both the first quantum well layer 13 and the second quantum well layer 14 are germanium, the carriers in the quantum well structure are mainly holes. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, and the isolation layer 23 can be made of silicon germanium material. The quantum well structure is an interval (Ge-Ge) hole double well structure; when the material of the first quantum well layer 13 is germanium and the material of the second quantum well layer 14 is silicon, or the material of the first quantum well layer 13 is silicon and the material of the second quantum well layer 14 is germanium, the carriers in the quantum well structure include electrons and holes. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, and the isolation layer 23 can be made of silicon germanium material. The quantum well structure is an interval (Si-Ge) electron-hole double well structure; when the material of the first quantum well layer 13 is germanium and the material of the second quantum well layer 14 is silicon, or the material of the first quantum well layer 13 is silicon and the material of the second quantum well layer 14 is germanium, the carriers in the quantum well structure include electrons and holes. The first quantum well layer 13 and the second quantum well layer 14 can be in direct contact, and the quantum well structure is a tightly bound (Si-Ge) electron-hole double well structure.

[0069] An embodiment of the present application provides a quantum well structure, which includes a substrate, on which a first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate are sequentially stacked. A bottom gate is located on the substrate and in contact with the first barrier layer. An aluminum layer is included on the first side sidewalls of the first quantum well layer and the second quantum well layer. A first electrode is further included on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode is located on the third side sidewall of the second quantum well layer. The second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively. A superfluid phase under Bose-Einstein condensation is generated through the coupling between the quantum well layers. Since an aluminum layer is provided on the first side sidewalls of the first quantum well layer and the second quantum well layer, the formation process of the aluminum layer is simple and it is easy to form a high-quality film layer, realizing the coupling of the superfluid phase with a superconducting lead and ensuring a clear coupling interface, creating a high-quality and clear-interface quantum well structure that can be used to study fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology.

[0070] To better understand the technical solutions and technical effects of the present application, the following will combine the process Figure 6 and Figures 7-10 to describe specific embodiments in detail.

[0071] Reference Figure 6 As shown, it is a flowchart of a manufacturing method of a quantum well structure provided by an embodiment of the present application. The method includes the following steps:

[0072] S601, provide a substrate 11.

[0073] The substrate 11 is used to provide support for the film layers on the substrate 11. The material of the substrate 11 can be at least one of silicon and germanium, or other semiconductor materials and their combinations.

[0074] S602, form a first barrier layer 12, a first quantum well layer 13, a second quantum well layer 14, and a second barrier layer 15 that are sequentially stacked on the substrate.

[0075] On the substrate 11, a first barrier layer 12, a first quantum well layer 13, a second quantum well layer 14, and a second barrier layer 15 are sequentially formed by epitaxial growth using reduced-pressure chemical vapor deposition (PRCVD).

[0076] Among them, the first quantum well layer 13 and the second quantum well layer 14 serve as the active layer. When their thicknesses are thinned to the order of the Bohr radius or the de Broglie wavelength, the quantum size effect appears. At this time, the carriers are confined in the potential well formed by the active layer, and this potential well is called a quantum well. The quantum well is a narrow-bandgap ultra-thin layer sandwiched between two wide-bandgap potential barrier thin layers, which are respectively denoted as the first potential barrier layer 12 and the second potential barrier layer 15. The first potential barrier layer 12 can also be called the lower constant component layer, and the second potential barrier layer 15 can also be called the upper constant component layer. The materials of the first potential barrier layer 12 and the second potential barrier layer 15 can be Si 1-x Ge x alloy materials. The first quantum well layer 13 and the second quantum well layer 14 form a double quantum well layer, which is the key semiconductor structure for generating superfluid (counter flow) / Bose-Einstein condensate (BEC). The double-well structure has characteristics such as high mobility, low penetration density, and large symmetric-antisymmetric energy gap. The material of the first quantum well layer 13 can be silicon or germanium, the material of the second quantum well layer 14 can be silicon or germanium, and the materials of the first quantum well 13 and the second quantum well 14 can be the same or different.

[0077] S603, an aluminum layer 18 is formed on the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, and a first electrode 19 is formed on the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14. A second electrode 20 is formed on the third side sidewall of the second quantum well layer 14, a top gate 16 is formed on the second potential barrier layer 15, and a bottom gate 17 is formed on the substrate 11 and in contact with the first potential barrier layer 12. The second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively.

[0078] In the embodiments of the present application, a contact step can be formed on the second barrier layer 15 through electron beam lithography and chemical wet etching, and then aluminum layer 18 is formed by evaporation or chemical vapor deposition RP-CVD. The aluminum layer 18 is located on the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14 and is used as a superconducting lead to combine with the superfluid generated by the double quantum well. The aluminum superconducting contact double-well structure becomes the "spacer layer" of superconducting tunneling, enabling the quantum well to be a high-quality quantum well structure with clear interfaces that can be used to study fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology. The S-DQW-S made of superconducting-semiconductor double quantum well heterostructure has superconducting-semiconductor / superfluid hybrid characteristics, and ballistic transport and mesoscopic transport effects that have never appeared can be observed. On the basis of ensuring clear coupling interfaces, a double-well structure with high mobility, low penetration density, and large symmetric-antisymmetric energy gap can be obtained, as well as a new substrate platform for studying fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology and vertical gate-controlled 3D quantum dots. Also, a substrate platform that can stably observe gate-controlled transport current and quantum effects can be obtained; the aluminum layer 18 can only cover the first side sidewalls of the first quantum well 13 and the second quantum well 14, or can cover the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, as well as the fourth side sidewalls. The first side sidewall and the fourth side sidewall are opposite sidewalls.

[0079] The aluminum layer 18 can only cover the sidewalls of the first quantum well layer 13 and the second quantum well layer 14, or can also cover the sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. That is to say, when the aluminum layer 18 covers the first side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, it can also cover the first side sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. When the aluminum layer 18 covers the fourth side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, it can also cover the fourth side sidewalls of the first barrier layer 12 and the second barrier layer 15 at the same time. In addition, the aluminum layer 18 can also cover a part of the upper surface of the second barrier layer 15.

[0080] In addition, when the aluminum layer 18 covers the first side sidewalls and the fourth side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, as well as the first side sidewalls and the fourth side sidewalls of the first barrier layer 12 and the second barrier layer 15, the action range of the superconducting lead is enhanced. The aluminum layer 18 is used to combine the double-well structure and the aluminum superconducting lead to realize a superconducting-superfluid hybrid quantum device, so as to prepare a substrate platform that can stably observe gate-controlled transport current and quantum effects.

[0081] The top view of the substrate platform in the embodiments of the present application can be rectangular, square, rhombic or circular, and the whole can be a cuboid, cylinder, frustum or cone, that is, the quantum well structure composed of the substrate 11, the first barrier layer 12, the first quantum well layer 13, the second quantum well layer 14, the second barrier layer 15 and the top gate 16 can be a cuboid, cylinder, frustum or cone, etc., and the top view can be rectangular, square, rhombic or circular, etc. In the embodiments of the present application, the case where the top view is rectangular is taken as an example for illustration. Of course, the present application does not specifically limit the graphic structure of the substrate platform, which does not affect the implementation of the embodiments of the present application. In the embodiments of the present application, taking the rectangle as an example for the graphic display is convenient for showing the structure between the substrate platforms.

[0082] A first electrode 19 is formed on the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14, and a second electrode 20 is formed on the third side sidewall of the second quantum well layer 14. One of the first electrode 19 and the second electrode 20 is the source electrode, and the other is the drain electrode. Wherein, the second side sidewall and the third side sidewall are respectively adjacent to the first side sidewall, and the second side sidewall and the third side sidewall are opposite sidewalls. Among them, the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14 are doped with the first doping type, and the first electrode 19 is formed on the second side sidewalls of the first quantum well layer 13 and the second quantum well layer 14. The third side sidewall of the second quantum well layer 14 is doped with the second doping type, and the second electrode 20 is formed on the third side sidewalls of the first quantum well layer 13 and the second quantum well layer 14. Wherein, the first doping type is P-type heavy doping P++, the second doping type is N-type heavy doping N++, and the first electrode 19 and the second electrode 20 are used as contact source and drain, which are used to jointly adjust with the top gate and the bottom gate to generate superfluid or strong Coulomb interaction in the quantum well structure.

[0083] After depositing the top gate 16 and the bottom gate 17, electron beam lithography patterning can be performed to define the top gate 16 and the bottom gate 17 that contacts the heavily doped constant group layer, that is, the bottom gate 17 that contacts the first barrier layer 12. The top gate 16 is used to apply a voltage to the upper surface of the second barrier layer 15. The material of the top gate 16 can be a material with good conductivity, such as titanium or aluminum. When the material of the top gate 16 is aluminum, it can be deposited simultaneously with the aluminum layer 18 and then electron beam lithography can be performed simultaneously. When the material of the top gate 16 is not aluminum, the top gate 16 can be deposited first, then electron beam lithography can be performed on the top gate 16, and then after depositing the aluminum layer 18, electron beam lithography can be performed on the aluminum layer 18. The bottom gate 17 is used to apply a voltage to the lower surface of the first barrier layer 12. The bottom gate 17 can be located between the substrate 11 and the first barrier layer 12; the bottom gate 17 can also be used to apply a voltage to the upper surface of the first barrier layer 12. At this time, the bottom gate 17 is located above the first barrier layer 12. At this time, the area of the first barrier layer 12 is larger than the sum of the areas of the bottom gate 17 and the first quantum well layer 13. The first quantum well layer 13 and the bottom gate 17 are located in different regions on the first barrier layer 12. The top gate 16 and the bottom gate 17 are used to achieve gate control of the double-well structure, so that double quantum dot entanglement (superfluid / backflow quantum phenomenon) appears in the double well, so as to achieve multiple Andreev reflections or exotic quantum effects of superconducting-superfluid contact, or to achieve a longer superconducting induction gap and a more obvious gate-controlled transport current.

[0084] In the embodiment of the present application, the sequence of forming the aluminum layer 18, the first electrode 19, the second electrode 20, the top gate 16, and the bottom gate 17 is not specifically limited. The aluminum layer 18, the first electrode 19, the second electrode 20, the top gate 16, and the bottom gate 17 can also be formed simultaneously, which does not affect the implementation of the embodiment of the present application.

[0085] In addition, when the aluminum layer 18 covers a part of the upper surface of the second barrier layer 15, in order to achieve insulation between the aluminum layer 18 and the top gate 16, a dielectric layer 24 can be formed between the aluminum layer 18 and the top gate 16. The natural oxide on the aluminum layer 18 can be removed by argon milling, and then hafnium dioxide can be deposited by atomic layer deposition (ALD) to form the dielectric layer 24. A part of the upper surface of the second barrier layer 15 is covered by the aluminum layer 18, and the remaining surface of the second barrier layer 15 is covered by the dielectric layer 24. The bottom surface of the dielectric layer 24 is in contact with the aluminum layer 18, which is used to isolate the aluminum layer 18 and the top gate 16. The material of the dielectric layer 24 can be an insulating material such as an oxide or a nitride, or a semiconductor material such as intrinsic silicon or intrinsic germanium. Of course, the material of the dielectric layer 24 in the embodiment of the present application can also be other semiconductor materials. The material of the dielectric layer 24 is not specifically limited here, which does not affect the implementation of the embodiment of the present application.

[0086] In the embodiments of the present application, when the materials of the substrate 11 and the first barrier layer 12 are inconsistent, for example, the material of the substrate 11 is silicon (100) and the material of the first barrier layer 12 is silicon germanium, due to the large lattice mismatch between silicon and germanium, it becomes extremely difficult to grow a high-quality and clear-interface double-well structure on the silicon substrate. Due to the requirements of interlayer coupling and superconducting long-range coupling, the difficulty of growing a high-quality superconducting double-well structure is further increased. If the first barrier layer 12 is directly formed on the substrate 11, due to the dislocations between the substrate 11 and the first barrier layer 12, the formation quality of the first barrier layer 12 is affected. At this time, a buffer layer 21 can be formed on the substrate 11 before forming the first barrier layer 12, so that the double quantum well thereon has the characteristics of high quality, high clarity, and low dislocations.

[0087] See Figure 7A 、 Figure 7B and Figure 7C , which is another schematic diagram of a quantum well structure provided by the embodiments of the present application. A buffer layer 21 is provided between the substrate 11 and the first barrier layer 12. The buffer layer 21 is doped and can be in contact with the bottom gate 17. The bottom gate 17 is located in other areas outside the projection area of the first barrier layer 12 on the substrate 11 and can be located on the side of the buffer layer 21. Among them, the way of doping the buffer layer 21 can be ion implantation.

[0088] When the material of the first quantum well layer 13 is silicon, the silicon element content in the buffer layer 21 gradually decreases from bottom to top, and the germanium content gradually increases. As a silicon germanium forward graded layer (SiGe FG) or a forward silicon germanium virtual substrate, there is more silicon element below the buffer layer 21, so the dislocations between it and the substrate 11 are smaller, and there is more germanium element above, so the dislocations between it and the first barrier layer 12 are smaller, making the quality of the first barrier layer 12 less affected by dislocations and facilitating the obtaining of a higher-quality first barrier layer 12; when the material of the first quantum well layer 13 is germanium, the silicon element content in the buffer layer 21 gradually increases from bottom to top, and the germanium content gradually decreases. As a silicon germanium reverse graded layer (SiGe RG) or a reverse silicon germanium virtual substrate, there is more silicon element above the buffer layer 21, so the dislocations between it and the first barrier layer 12 are smaller, making the quality of the first barrier layer 12 less affected by dislocations and facilitating the obtaining of a higher-quality first barrier layer 12.

[0089] When the material of the first quantum well layer 13 is germanium, due to the higher germanium content below the buffer layer 21, large dislocations are likely to occur between the buffer layer 21 and the substrate 11. Therefore, a germanium material layer 22 is formed between the substrate 11 and the buffer layer 21. The germanium material layer 22 includes a low-temperature germanium layer facing the substrate 11 and a high-temperature germanium layer facing the buffer layer 21, so that it can act as a buffer between the substrate 11 and the buffer layer 21, facilitating the obtaining of a high-quality buffer layer 21, and making the double quantum well thereon have the characteristics of high quality, high clarity, and low dislocations.

[0090] See Figure 8A 、 Figure 8B and Figure 8C , which is another schematic diagram of a quantum well structure provided by an embodiment of the present application. A germanium material layer 22 is further included between the substrate 11 and the buffer layer 21. The buffer layer 21 is in contact with the bottom gate 17, and the bottom gate 17 is located in other areas outside the projection area of the first barrier layer 12 on the germanium material layer 22, and can be located on the side of the buffer layer 21. The substrate 11 and the germanium material layer 22 can protrude from the side of the buffer layer 21, and the protruding part serves as the support of the bottom gate 17.

[0091] In the embodiment of the present application, when the materials of the first quantum well layer 13 and the second quantum well layer 14 are the same, an isolation layer 23 is provided between the first quantum well layer 13 and the second quantum well layer 14. The material of the isolation layer 23 can be silicon germanium. The isolation layer 23 is used to separate two quantum well layers of the same material to form different types of quantum well structures. When the materials of the first quantum well layer 13 and the second quantum well layer 14 are different, an isolation layer 23 can be provided between the first quantum well layer 13 and the second quantum well layer 14, or the first quantum well layer 13 and the second quantum well layer 13 are in direct contact.

[0092] When there is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, the first quantum well layer 13 and the second quantum well layer 14 form an interval type quantum well structure. When the first quantum well layer 13 and the second quantum well layer 14 are in direct contact without an isolation layer 23, the first quantum well layer 13 and the second quantum well layer 14 form a tightly bound type quantum well structure. The tightly bound type quantum well structure and the interval type quantum well structure can enable the double quantum well coupling to generate a superfluid phase under Bose-Einstein (BEC) condensation, and have foreseeable extremely high coupling mobility and fractional quantum Hall effect.

[0093] As an example, see Figure 9A 、 Figure 9B and Figure 9C , which is another schematic diagram of a quantum well structure provided by an embodiment of the present application. When the materials of both the first quantum well layer 13 and the second quantum well layer 14 are silicon, the carriers in the quantum well structure are mainly electrons. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14, and the isolation layer 23 can be made of silicon germanium material. The quantum well structure is an interval type (Si-Si) electron double well structure; see Figure 10A 、 Figure 10B and Figure 10C, which is another schematic diagram of the quantum well structure provided by the embodiments of the present application. When the materials of the first quantum well layer 13 and the second quantum well layer 14 are both germanium, the carriers in the quantum well structure are mainly holes. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14. The isolation layer 23 can be a silicon-germanium material, and the quantum well structure is a spaced (Ge-Ge) hole double well structure; when the material of the first quantum well layer 13 is germanium and the material of the second quantum well layer 14 is silicon, or when the material of the first quantum well layer 13 is silicon and the material of the second quantum well layer 14 is germanium, the carriers in the quantum well structure include electrons and holes. There is an isolation layer 23 between the first quantum well layer 13 and the second quantum well layer 14. The isolation layer 23 can be a silicon-germanium material, and the quantum well structure is a spaced (Si-Ge) electron-hole double well structure. For details, see also Figure 10A , Figure 10B and Figure 10C ; when the material of the first quantum well layer 13 is germanium and the material of the second quantum well layer 14 is silicon, or when the material of the first quantum well layer 13 is silicon and the material of the second quantum well layer 14 is germanium, the carriers in the quantum well structure include electrons and holes. The first quantum well layer 13 and the second quantum well layer 14 can be in direct contact with each other. The quantum well structure is a tightly bound (Si-Ge) electron-hole double well structure. For details, see also Figure 8A , Figure 8B and Figure 8C .

[0094] The embodiments of the present application provide a manufacturing method of a quantum well structure, including providing a substrate, and forming a first barrier layer, a first quantum well layer, a second quantum well layer, and a second barrier layer stacked in sequence on the substrate. An aluminum layer is formed on the first side sidewalls of the first quantum well layer and the second quantum well layer, and a first electrode is formed on the second side sidewalls of the first quantum well layer and the second quantum well layer. A second electrode is formed on the third side sidewall of the second quantum well layer, and a top gate is formed on the second barrier layer, and a bottom gate in contact with the first barrier layer is formed on the substrate. The second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively. A superfluid phase in Bose-Einstein condensation is generated through the coupling between the quantum well layers. Since an aluminum layer is provided on the first side sidewalls of the first quantum well layer and the second quantum well layer, the formation process of the aluminum layer is simple and it is easy to form a high-quality film layer, realizing the coupling of the superfluid phase with a superconducting lead and ensuring a clear coupling interface, creating a high-quality and clear-interface quantum well structure for researching the fractional quantum Hall effect and superconducting-superfluid hybrid quantum computing technology.

[0095] Each embodiment in this specification is described in a progressive manner. For the same or similar parts between the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0096] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application shall still be within the scope of the protection of the technical solution of the present application.

Claims

1. A quantum well structure, characterized in that, Comprising: A substrate; A first barrier layer, a first quantum well layer, a second quantum well layer, a second barrier layer, and a top gate sequentially stacked on the substrate; A bottom gate located on the substrate and in contact with the first barrier layer; An aluminum layer located on the first side sidewalls of the first quantum well layer and the second quantum well layer; A first electrode located on the second side sidewalls of the first quantum well layer and the second quantum well layer, and a second electrode located on the third side sidewall of the second quantum well layer, the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively.

2. The structure according to claim 1, characterized in that, A buffer layer is provided between the substrate and the first barrier layer, the buffer layer is doped, the buffer layer is in contact with the bottom gate, and the bottom gate is located in other regions outside the projection area of the first barrier layer on the substrate.

3. The structure according to claim 2, wherein, The material of the substrate is silicon; When the material of the first quantum well layer is silicon, the silicon element content in the buffer layer gradually decreases from bottom to top, and the germanium content gradually increases; when the material of the first quantum well layer is germanium, a germanium material layer is further included between the substrate and the buffer layer, and the silicon element in the buffer layer gradually increases from bottom to top, and the germanium content gradually decreases.

4. The structure according to claim 3, characterized in that, The material of the second quantum well layer is silicon or germanium; When the materials of the second quantum well layer and the first quantum well layer are the same, an isolation layer is provided between the first quantum well layer and the second quantum well layer; when the materials of the second quantum well layer and the first quantum well layer are different, an isolation layer is provided between the first quantum well layer and the second quantum well layer, or the first quantum well layer and the second quantum well layer are in direct contact.

5. The structure according to any one of claims 1-4, characterized in that, The aluminum layer further covers the fourth side sidewalls of the first quantum well layer and the second quantum well layer, and the first side sidewall and the fourth side sidewall are opposite sidewalls.

6. The structure according to claim 5, characterized in that, The aluminum layer further covers the first side sidewalls of the first barrier layer and the second barrier layer, the fourth side sidewalls of the first barrier layer and the second barrier layer, and a partial upper surface of the second barrier layer. There is a dielectric layer between the aluminum layer and the top gate, and the dielectric layer covers the partial upper surface of the second barrier layer.

7. The structure according to any one of claims 1-4, characterized in that, The second side sidewalls of the first quantum well layer and the second quantum well layer are doped with a first doping type, and the third side sidewall of the second quantum well layer is doped with a second doping type.

8. A manufacturing method of a quantum well structure, characterized in that, Comprising: Providing a substrate; Forming a first barrier layer, a first quantum well layer, a second quantum well layer, and a second barrier layer sequentially stacked on the substrate; Forming an aluminum layer on the first side sidewalls of the first quantum well layer and the second quantum well layer, forming a first electrode on the second side sidewalls of the first quantum well layer and the second quantum well layer, forming a second electrode on the third side sidewall of the second quantum well layer, forming a top gate on the second barrier layer, and forming a bottom gate on the substrate and in contact with the first barrier layer, the second side sidewall and the third side sidewall are adjacent to the first side sidewall respectively.

9. The method according to claim 8, wherein The method further includes: Before forming the first barrier layer on the substrate, a buffer layer is formed on the substrate. The buffer layer is doped and is used for bottom gate contact. The bottom gate is located in other areas outside the projection area of the first barrier layer on the substrate.

10. The method according to claim 9, wherein The material of the substrate is silicon; When the material of the first quantum well layer is silicon, the silicon element content in the buffer layer gradually decreases from bottom to top, and the germanium content gradually increases; when the material of the first quantum well layer is germanium, a germanium material layer is further included between the substrate and the buffer layer, and the silicon element in the buffer layer gradually increases from bottom to top, and the germanium content gradually decreases.

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