storage unit and memory

Abstract

The application provides a storage unit and a memory, wherein the storage unit comprises: a first doped structure, a second doped structure and a semiconductor structure which are sequentially stacked along a first direction, a semiconductor structure, a tunnel layer, a charge trapping layer, a conductive layer which are sequentially stacked along a second direction, and the first doped structure and the second doped structure are opposite in doping type. The application improves the microfabrication capability of the storage unit and the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a memory cell and a memory. Background Technology

[0002] With the development of 5G, big data, and machine learning, the realization of these fields places higher demands on chip performance. As chip computing power improves, memory becomes a crucial factor affecting chip performance.

[0003] The memory consists of multiple memory cells. Currently, memory cells generally use ferroelectric thin films as the gate dielectric layer of field-effect transistors. By changing the threshold voltage of the field-effect transistor through the polarization properties of the ferroelectric thin film, the storage state of "0" or "1" can be achieved.

[0004] Due to the depolarization field of ferroelectric thin films, their polarization properties become unstable when the film thickness is less than 5 nm. Therefore, to ensure the normal operation of field-effect transistors (FETs), the thickness of the ferroelectric thin film cannot be reduced further after reaching a certain limit. This limitation restricts the miniaturization capability of FETs (i.e., memory cells), thus limiting the miniaturization capability of memory. Summary of the Invention

[0005] This application provides a storage cell and a memory to solve the problem that the miniaturization capability of field-effect transistors (i.e., storage cells) and memory is limited because the thickness of ferroelectric thin films cannot be further reduced after reaching a certain thickness.

[0006] In a first aspect, this application provides a memory cell, comprising: a first doped structure, a second doped structure, and a semiconductor structure stacked sequentially along a first direction; the semiconductor structure, a tunneling layer, and a charge trapping layer stacked sequentially along a second direction; and a conductive layer located on the charge trapping layer; wherein the doping types of the first doped structure and the second doped structure are opposite.

[0007] This invention presents a novel and simple structure with a low manufacturing cost. Furthermore, compared to existing methods that utilize the polarization properties of ferroelectric thin films for data storage, the charge trapping layer primarily utilizes bulk and / or interface defects in the material to trap charges for data storage. Therefore, the charge trapping layer can be made thinner, reducing the size of the storage cell and consequently the overall memory size, thus enhancing the miniaturization capability of the storage cell and memory. Moreover, based on the relative positions of the various parts within the storage cell, this storage cell is a vertical structure, facilitating the integration of multiple storage cells. This allows for the three-dimensional stacking of multiple storage cells, enabling a three-dimensional memory. Due to the small size of the storage cell, more storage cells can be integrated into the same area compared to existing storage cells, increasing the storage cell density. Additionally, since charge trapping devices have lower operating voltages compared to existing ferroelectric thin films, and the storage cell in this application achieves read / write operations through the charge trapping layer, the operating voltage is reduced compared to existing ferroelectric thin films, improving the durability of the storage cell.

[0008] In one possible implementation, if the charge trapping layer is an electron trapping layer, then the charge trapping layer is used to trap electrons from the semiconductor structure or release trapped electrons; if the charge trapping layer is a hole trapping layer, then the charge trapping layer is used to trap holes from the semiconductor structure or release trapped holes.

[0009] In one possible implementation, the electron trapping layer is made of any one of HfO2, HfSiO, HfAlO, Si3N4, AlN, and InGaZnO; and the hole trapping layer is made of any one of HfZrO and NiO.

[0010] In one possible implementation, the first doped structure, the second doped structure, and the semiconductor structure are all cylindrical; or the first doped structure, the second doped structure, and the semiconductor structure are all cuboids.

[0011] In one possible implementation, the memory cell further includes: a first electrode layer disposed on the semiconductor structure; and a second electrode layer disposed on the first doped structure.

[0012] In one possible implementation, a dipole is introduced at the interface between the tunneling layer and the charge trapping layer; the dipole is used to prevent the charge trapped by the charge trapping layer from passing through the tunneling layer into the semiconductor structure.

[0013] By introducing a dipole between the charge trapping layer and the tunneling layer, the flat-band voltage and work function of the system can be adjusted through the built-in electric field generated by the dipole, thereby enhancing the charge trapping layer's ability to retain charge and thus improving the storage characteristics of the memory cell.

[0014] In one possible implementation, the characteristic is that if the charge trapping layer is an electron trapping layer, then the dipole is a positive dipole; if the charge trapping layer is a hole trapping layer, then the dipole is a negative dipole.

[0015] In one possible implementation, the material forming the positive dipole is a rare earth element, and the material forming the negative dipole is a metallic element.

[0016] In one possible implementation, the storage cell further includes a barrier layer disposed between the charge trapping layer and the conductive layer, for preventing electrons in the conductive layer from being injected into the charge trapping layer and preventing the charge trapped by the charge trapping layer from escaping to the conductive layer.

[0017] In one possible implementation, the undoped first doped structure, the undoped second doped structure, and the semiconductor structure are made of any one of silicon, silicon-germanium, and germanium.

[0018] In one possible implementation, the tunneling layer is made of silicon dioxide or aluminum oxide.

[0019] In a second aspect, this application provides a memory comprising: a plurality of memory cells as described in any one of the first aspects, wherein the plurality of memory cells are arranged in an array; a plurality of word lines for applying a voltage to a first doped structure of the memory cells; a plurality of bit lines for applying a voltage to a semiconductor structure of the memory cells; a plurality of gate lines for applying a voltage to a conductive layer of the memory cells; wherein if the word lines applying voltage to the first doped structures of at least two memory cells are the same, then the bit lines applying voltage to the semiconductor structures of the at least two memory cells are different; and if the bit lines applying voltage to the semiconductor structures of at least two memory cells are the same, then the word lines applying voltage to the first doped structures of the at least two memory cells are different.

[0020] In one possible implementation, the plurality of memory cells are arranged in N rows and M columns; the plurality of word lines are N, and each of the N word lines corresponds one-to-one with the N rows of memory cells, each word line being used to apply a voltage to the first doped structure of the corresponding row of memory cells; the plurality of bit lines are M, and each of the M bit lines corresponds one-to-one with the M columns of memory cells, each bit line being used to apply a voltage to the semiconductor structure of the corresponding column of memory cells; the plurality of gate lines are N, and each of the N gate lines corresponds one-to-one with the N rows of memory cells, each gate line being used to apply a voltage to the conductive layer of the corresponding row of memory cells.

[0021] Thirdly, this application provides a three-dimensional memory, comprising: a plurality of memory cells as described in any one of the first aspects above, wherein the plurality of memory cells are located in different memory layers, and the memory cells in each memory layer are arranged in an array, and the array arrangement of each memory layer is the same; a plurality of word lines for applying a voltage to a first doped structure in a first memory layer; a plurality of bit lines divided into multiple groups, wherein the number of groups of bit lines is the same as the number of memory layers, and the multiple groups of bit lines correspond one-to-one with multiple memory layers, and each group of bit lines is used to apply a voltage to the semiconductor structure of the memory cell in the corresponding memory layer; a group of bit lines corresponding to each memory layer is also used to apply a voltage to the first doped structure of the memory cell in the memory layer above it; and a plurality of gate lines divided into multiple groups, wherein the number of groups of gate lines is the same as the number of memory layers, and the multiple groups of gate lines correspond one-to-one with multiple memory layers. Each set of gate lines is used to apply a voltage to the conductive layer of the corresponding memory cell in the memory layer. For memory cells in the first memory layer, if the word lines for applying voltage to the first doped structure of at least two memory cells are the same, then the bit lines for applying voltage to the semiconductor structure of the at least two memory cells are different; if the bit lines for applying voltage to the semiconductor structure of at least two memory cells are the same, then the word lines for applying voltage to the first doped structure of the at least two memory cells are different. For memory cells in other memory layers, if the bit lines for applying voltage to the first doped structure of at least two memory cells are the same, then the bit lines for applying voltage to the semiconductor structure of the at least two memory cells are different; if the bit lines for applying voltage to the semiconductor structure of at least two memory cells are the same, then the bit lines for applying voltage to the first doped structure of the at least two memory cells are different.

[0022] In one possible implementation, the memory cells in each memory layer are arranged in N rows and M columns; the semiconductor structure of the M columns of memory cells in the i-th memory layer corresponds one-to-one with the M column bit lines; the semiconductor structure of the N rows of memory cells in the j-th memory layer corresponds one-to-one with the N rows of bit lines; the first doped structure of the N rows of memory cells in the first memory layer corresponds one-to-one with the N rows of word lines; the first doped structure of the M columns of memory cells in the (i+1)-th memory layer corresponds one-to-one with the M column bit lines corresponding to the i-th memory layer; the first doped structure of the N rows of memory cells in the (j+1)-th memory layer corresponds one-to-one with the N rows of bit lines corresponding to the j-th memory layer; wherein i is an odd number and j is an even number.

[0023] Fourthly, this application provides an electronic device, characterized in that it comprises: a processor and a storage device; the storage device includes a memory as described in any one of the second aspects and / or a three-dimensional memory as described in any one of the third aspects; the processor is configured to perform write operations or read operations on the memory and / or the three-dimensional memory. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a storage unit provided in the first embodiment of this application.

[0025] Figure 2 for Figure 1 A cross-sectional view of the storage cell along the ab direction;

[0026] Figure 3 This is a schematic diagram of the structure of the storage unit provided in the second embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the structure of the storage unit provided in the third embodiment of this application;

[0028] Figure 5 for Figure 4 A cross-sectional view of the storage cells along the cd direction;

[0029] Figure 6 This is a schematic diagram of the structure of the storage unit provided in the fourth embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of the storage unit provided in the fifth embodiment of this application;

[0031] Figure 8 This is a schematic diagram of the structure of the storage unit provided in the sixth embodiment of this application;

[0032] Figure 9 for Figure 1 A cross-sectional view of the storage cell in the image along the ab direction when "1" is written;

[0033] Figure 10 for Figure 1 A cross-sectional view of the storage cell along the ab direction when "0" is written;

[0034] Figure 11 for Figure 1 A cross-sectional view along the ab direction after a positive dipole is introduced into the storage cell;

[0035] Figure 12 A schematic diagram illustrating the effect of introducing a positive dipole into a storage cell on the band structure;

[0036] Figure 13 for Figure 1 A cross-sectional view along the ab direction after a negative dipole is introduced into the storage cell;

[0037] Figure 14 A schematic diagram illustrating the effect of introducing a negative dipole into the band structure of a storage cell;

[0038] Figure 15 For the embodiments of this application in Figure 1 A schematic diagram of the structure after adding a barrier layer to the storage cell;

[0039] Figure 16 A schematic diagram of the structure of a memory including 3 rows and 3 columns of storage units provided for embodiments of this application;

[0040] Figure 17 This is a voltage distribution diagram when a "1" is written to the memory cell in the second row and second column.

[0041] Figure 18 A voltage distribution diagram when writing "0" to the memory cell in the second row and second column of the memory.

[0042] Figure 19 The voltage distribution diagram when reading data from the memory cell in the second row and second column of the memory. Detailed Implementation

[0043] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0046] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0047] This application provides a memory cell comprising a first doped structure, a second doped structure, and a semiconductor structure sequentially stacked along a first direction; a semiconductor structure, a tunneling layer, and a charge trapping layer sequentially stacked along a second direction; and a conductive layer disposed on the charge trapping layer; wherein the doping types of the first doped structure and the second doped structure are opposite. The angle between the second direction and the first direction is not equal to 180°. The conductive layer being located on the charge trapping layer can be understood as the conductive layer being located on at least one surface of the charge trapping layer outside the contact surface with the tunneling layer.

[0048] For example, Figure 1 This is a schematic diagram of the structure of a storage unit provided in the first embodiment of this application. Figure 2 for Figure 1 A cross-sectional view of the storage cell along the ab direction, as shown below. Figure 1 and Figure 2 As shown, the memory cell includes: a first doped structure 101, a second doped structure 102, a semiconductor structure 103, a tunneling layer 104, a charge trapping layer 105, and a conductive layer 106, wherein:

[0049] The first doped structure 101, the second doped structure 102, and the semiconductor structure 103 are all cylindrical in shape. The size and specifications of the first doped structure 101, the second doped structure 102, and the semiconductor structure 103 can be determined according to design requirements. This application embodiment does not impose any special limitations on this.

[0050] It should be noted that the shapes of the first doped structure 101, the second doped structure 102, and the semiconductor structure 103 described above are merely exemplary and are not intended to limit this application. For example, the shapes of the first doped structure 101, the second doped structure 102, and the semiconductor structure 103 can also be cubes, cuboids, semi-cylinders, etc., and this application embodiment does not impose any special limitations on them. The shapes of the first doped structure 101, the second doped structure 102, and the semiconductor structure 103 can be exactly the same, not exactly the same, or completely different, and this application embodiment does not impose any special limitations on them.

[0051] A first doped structure 101, a second doped structure 102, and a semiconductor structure 103 are sequentially stacked along a first direction 111. A semiconductor structure 103, a tunneling layer 104, and a charge trapping layer 105 are sequentially stacked along a second direction. A conductive layer 106 is located on the charge trapping layer 105. Figure 1 As shown, the second direction 112 is perpendicular to the first direction 111.

[0052] like Figure 1 As shown, the second doped structure 102 is located on the upper surface of the first doped structure 101, and the semiconductor structure 103 is located on the upper surface of the second doped structure 102.

[0053] The tunneling layer 104 is located on the side of the semiconductor structure 103. Here, the tunneling layer 104 being located on the side of the semiconductor structure 103 can be understood as: the tunneling layer 104 completely covers the side of the semiconductor structure 103 (e.g., ...). Figure 1 (As shown) or the tunneling layer 104 covers a portion of the side of the semiconductor structure 103.

[0054] The charge trapping layer 105 is located on the tunneling layer 104. Specifically, the tunneling layer 104 includes two opposing upper and lower surfaces. If the upper surface of the tunneling layer 104 is located on the side of the semiconductor structure 103, then the charge trapping layer 105 is located on the lower surface of the tunneling layer 104; if the lower surface of the tunneling layer 104 is located on the side of the semiconductor structure 103, then the charge trapping layer 105 is located on the upper surface of the tunneling layer 104.

[0055] The charge trapping layer 105 is located on the tunneling layer 104, which can be understood as the charge trapping layer 105 completely covering the tunneling layer 104 (e.g. Figure 1 (as shown), or the charge trapping layer 105 covers a portion of the tunneling layer 104.

[0056] The conductive layer 106 is located on the charge trapping layer 105. Specifically, the conductive layer 106 may be located on at least one surface of the charge trapping layer 105 outside the contact surface with the tunneling layer 104.

[0057] For example, Figure 1 The charge trapping layer 105 includes four surfaces: two opposing upper surfaces and a lower surface, and two opposing surfaces perpendicular to the upper surface. If the upper surface of the charge trapping layer 105 is located on the tunneling layer 104, the conductive layer 106 may be located on at least one of the lower surface of the charge trapping layer 105 and the two surfaces perpendicular to the upper surface; if the lower surface of the charge trapping layer 105 is located on the tunneling layer 104, the conductive layer 106 may be located on at least one of the upper surface of the charge trapping layer 105 and the two surfaces perpendicular to the upper surface.

[0058] It should be noted that the conductive layer 106 is located on one surface of the charge trapping layer 105 in such a way that the conductive layer 106 completely covers one surface of the charge trapping layer 105 (e.g., Figure 1 (as shown), or the conductive layer 106 covers a portion of a surface of the charge trapping layer 105.

[0059] The doping type of the first doped structure 101 is opposite to that of the second doped structure 102. For example, if the doping type of the first doped structure 101 is N-type, then the doping type of the second doped structure 102 is P-type. If the doping type of the first doped structure 101 is P-type, then the doping type of the second doped structure 102 is N-type.

[0060] Semiconductor structure 103 can be an intrinsic semiconductor (i.e., an undoped semiconductor) or a doped semiconductor; this application embodiment does not impose any special limitations on this. If semiconductor structure 103 is a doped semiconductor, then the doping type of semiconductor structure 103 is the same as the doping type of the second doped structure 102. That is, if the doping type of the second doped structure 102 is N-type, then the doping type of semiconductor structure 103 is N-type; if the doping type of the second doped structure 102 is P-type, then the doping type of semiconductor structure 103 is P-type.

[0061] The materials of the undoped first doped structure 101, the undoped second doped structure 102, and the semiconductor structure 103 can be any one of silicon, silicon-germanium, germanium, or oxide semiconductors (such as InGaZnO). The materials of the undoped first doped structure 101, the undoped second doped structure 102, and the semiconductor structure 103 can be exactly the same, not exactly the same, or completely different; this application does not impose any special limitations on this.

[0062] It should be noted that the material of semiconductor structure 103 here can be understood as follows: if semiconductor structure 103 is an intrinsic semiconductor, then the material of semiconductor structure 103 is the material of intrinsic semiconductor; if semiconductor structure 103 is a doped semiconductor, then the material of semiconductor structure 103 refers to the semiconductor material before it is doped.

[0063] For example, if the first doped structure 101 is N-type doped silicon, then the second doped structure 102 and the semiconductor structure 103 can be P-type doped silicon; if the first doped structure 101 is P-type doped silicon-germanium, then the second doped structure 102 and the semiconductor structure 103 can be N-type doped silicon-germanium. If the first doped structure 101 is N-type doped silicon-germanium, then the second doped structure 102 can be P-type doped silicon-germanium, and the semiconductor structure 103 can be undoped silicon-germanium.

[0064] It should be noted that because silicon-germanium and germanium have relatively small band gaps, their PN junctions are easier to open, meaning they operate at lower voltages. Based on this principle, if the undoped first doped structure 101, the undoped second doped structure 102, and the semiconductor structure 103 all use silicon-germanium or germanium materials, the operating voltage of the memory cell can be reduced.

[0065] The doping concentrations of the first doped structure 101, the second doped structure 102, and the semiconductor structure 103 (in the case of a doped semiconductor) can be determined according to the design requirements of the memory cell, and this application embodiment does not impose any special limitations on this. For example, the first doped structure 101 is heavily doped P-type silicon, the second doped structure 102 is heavily doped N-type silicon, and the semiconductor structure 103 is lightly doped N-type silicon.

[0066] It should be noted that N-type doping refers to a doped structure in which the majority carriers are electrons, while P-type doping refers to a doped structure in which the majority carriers are holes.

[0067] The material of the tunneling layer 104 can be insulating materials such as silicon dioxide or aluminum oxide, and this application embodiment does not make any special limitation on this.

[0068] In an alternative embodiment, the charge trapping layer 105 can be shaped as an electron trapping layer or a hole trapping layer. If the charge trapping layer 105 is an electron trapping layer, it is used to trap electrons from the semiconductor structure 103 or release trapped electrons. If the charge trapping layer 105 is a hole trapping layer, it is used to trap holes from the semiconductor structure 103 or release trapped holes.

[0069] The electron trapping layer can be made of any of the following materials with electron trapping capabilities: HfO2, HfSiO, HfAlO, Si3N4, AlN, InGaZnO, etc. The hole trapping layer can be made of any of the following materials with hole trapping capabilities: HfZrO, NiOd, etc.

[0070] The material of the conductive layer 106 can be, for example, a metal or a heavily doped polycrystalline silicon, and this application does not impose any special limitations on this.

[0071] It should be noted that the larger the area covered by each of the above layers is by the layer preceding it, the stronger the driving capability of the storage unit.

[0072] For example, Figure 3 This is a schematic diagram of the structure of the storage unit provided in the second embodiment of this application. Figure 3 The storage unit in Figure 1 The differences between the storage units in the two languages ​​are as follows:

[0073] The first doped structure 101, the second doped structure 102, and the semiconductor structure 103 are all cuboid in shape.

[0074] The tunneling layer 104 completely covers the four sides of the semiconductor structure 103, the charge trapping layer 105 completely covers the tunneling layer 104, and the conductive layer 106 is located on the outer surface of the charge trapping layer 105 and completely covers the outer surface of the charge trapping layer 105.

[0075] For example, Figure 4 This is a schematic diagram of the structure of the storage unit provided in the third embodiment of this application. Figure 5 for Figure 4 A cross-sectional view of the storage cell along the cd direction. Figure 4 The storage unit in Figure 1 The differences between the storage units in the two languages ​​are as follows:

[0076] The first doped structure 101, the second doped structure 102, and the semiconductor structure 103 are all cuboid in shape. The tunneling layer 104 covers one side of the semiconductor structure 103. The charge trapping layer 105 completely covers the tunneling layer 104. The conductive layer 106 is located on one surface of the charge trapping layer 105 and completely covers that surface.

[0077] For example, Figure 6 This is a schematic diagram of the structure of the storage unit provided in the fourth embodiment of this application. Figure 6 The storage unit in Figure 1 The differences between the storage units in the two languages ​​are as follows:

[0078] The first doped structure 101, the second doped structure 102, and the semiconductor structure 103 are all semi-cylinders.

[0079] The semi-cylinder includes two sides, a curved side and a flat side. The tunneling layer 104 covers the curved side of the semiconductor structure 103, the charge trapping layer 105 completely covers the tunneling layer 104, and the conductive layer 106 is located on one surface of the charge trapping layer 105 and completely covers that surface.

[0080] For example, Figure 7 This is a schematic diagram of the structure of the storage unit provided in the fifth embodiment of this application. Figure 7 The storage unit in Figure 1 The differences between the storage units in the two languages ​​are as follows:

[0081] The first doped structure 101 and the second doped structure 102 are cuboids, the semiconductor structure 103 is trapezoidal, and the angle between the first direction 110 and the second direction 112 is greater than 90°.

[0082] The tunneling layer 104 completely covers the four sides of the semiconductor structure 103, the charge trapping layer 105 completely covers the tunneling layer 104, and the conductive layer 106 is located on the four sides of the charge trapping layer 105 and completely covers the four sides.

[0083] For example, Figure 8 This is a schematic diagram of the structure of the storage unit provided in the sixth embodiment of this application. Figure 8 The storage unit in Figure 1 The differences between the storage units in the two languages ​​are as follows:

[0084] The first doped structure 101 and the second doped structure 102 are cuboids in shape, and the semiconductor structure 103 is a sphere formed by removing the top and bottom parts. The tunneling layer 104 completely covers the side surface of the semiconductor structure 103, the charge trapping layer 105 completely covers the tunneling layer 104, and the conductive layer 106 completely covers the outer surface of the charge trapping layer 105.

[0085] It should be noted that the above description of the structure of the storage unit is merely exemplary and is not intended to limit this application.

[0086] The working principle of the storage unit will be explained below.

[0087] The operation of a storage unit consists of two parts: write operations and read operations. Specifically:

[0088] The working principle of write operations is as follows:

[0089] When writing "1", a voltage is applied to the first doped structure 101 and the semiconductor structure 103, so that the first doped structure 101 and the second doped structure are 0 biased or reverse biased, that is, the PN junction formed by the first doped structure 101 and the second doped structure 102 is 0 biased or reverse biased; a positive bias voltage or a negative bias voltage is applied to the conductive layer 106. If the charge trapping layer 105 is an electron trapping layer, a positive bias voltage is applied to the conductive layer 106. If the charge trapping layer 105 is a hole trapping layer, a negative bias voltage is applied to the conductive layer 106; the voltage difference between the conductive layer 106 and the semiconductor structure 103 is greater than or equal to +V1 or less than or equal to -V1. If the charge trapping layer 105 is an electron trapping layer, the voltage difference between the conductive layer 106 and the semiconductor structure 103 is greater than or equal to +V1. If the charge trapping layer 105 is a hole trapping layer, the voltage difference between the conductive layer 106 and the semiconductor structure 103 is less than or equal to -V1.

[0090] After the above three conditions are met, the bias voltage applied to the conductive layer 106 generates an electric field. Charges in the semiconductor structure 103 respond to this electric field, passing through the tunneling layer 104 to reach the charge trapping layer 105. The charge trapping layer 105 utilizes its bulk defects and / or interface defects to trap charges, thus changing the resistance of the memory cell. It should be noted that if the charge trapping layer 105 is an electron trapping layer, the charge trapped by the charge trapping layer 105 from the semiconductor structure 103 is electrons; if the charge trapping layer 105 is a hole trapping layer, the charge trapped by the charge trapping layer 105 from the semiconductor structure 103 is holes.

[0091] When writing "0", a voltage is applied to the first doped structure 101 and the semiconductor structure 103, so that the first doped structure 101 and the second doped structure 102 are 0-biased or reverse-biased, that is, the PN junction formed by the first doped structure 101 and the second doped structure 102 is 0-biased or reverse-biased; a positive bias voltage or a negative bias voltage is applied to the conductive layer 106. If the charge trapping layer 105 is an electron trapping layer, a negative bias voltage is applied to the conductive layer 106. If the charge trapping layer 105 is a hole trapping layer, a positive bias voltage is applied to the conductive layer 106; the voltage difference between the conductive layer 106 and the semiconductor structure 103 is greater than or equal to +V1 or less than or equal to -V1. If the charge trapping layer 105 is an electron trapping layer, the voltage difference between the conductive layer 106 and the semiconductor structure 103 is less than or equal to -V1. If the charge trapping layer 105 is a hole trapping layer, the voltage difference between the conductive layer 106 and the semiconductor structure 103 is greater than or equal to +V1.

[0092] After the above three conditions are met, the bias voltage applied to the conductive layer 106 generates an electric field. The charge trapping layer 105 responds to the electric field and releases the trapped charge. At this time, the memory cell returns to its original state and the resistance of the memory cell is changed.

[0093] In other embodiments of this application, when writing "1" or "0", the first doped structure 101 and the second doped structure 102 may also be positively biased to utilize the hot carrier effect to promote charge trapping.

[0094] It should be noted that the specific values ​​of +V1 and -V1 are related to the material, thickness, and ratio of high to low current during reading of each part of the memory cell.

[0095] The principle of read operation is as follows:

[0096] The conductive layer 106 is grounded (i.e., a zero bias voltage is applied to the conductive layer 106). A voltage is applied to the first doped structure 101 and the semiconductor structure 103, making the first doped structure 101 and the second doped structure 102 forward biased. That is, the PN junction formed by the first doped structure 101 and the second doped structure 102 is forward biased, and the forward bias voltage between the first doped structure 101 and the second doped structure 102 is greater than or equal to V2. After the above conditions are met, the level of the current read from the first doped structure 101 and the semiconductor structure 103 determines whether the read data is "0" or "1". Specifically, when a "0" is written to the memory cell, the charge trapping layer 105 releases the trapped charge, resulting in a high read current. This means that if a high read current is detected, it indicates that the data stored in the memory cell is 0, and the data read is 0. When a "1" is written to the memory cell, the charge trapping layer 105 traps charge from the semiconductor structure 103, resulting in a low read current. This means that if a low read current is detected, it indicates that the data stored in the memory cell is "1".

[0097] One way to determine whether the read current is high or low is to set a first current and a second current, where the first current is greater than the second current. If the read current is greater than the first current, then the read current is high; if the read current is less than the second current, then the read current is low.

[0098] It should be noted that the above process is merely exemplary and is not intended to limit this application.

[0099] The specific value of V2 is related to the material of the storage cell, the doping concentration of the first doped structure 101 and the second doped structure 102, and the magnitude of the high and low currents read out.

[0100] It should be noted that the principles of the write and read operations of the above-mentioned storage cells are merely exemplary and are not intended to limit this application. For example, "1" can also be written in the manner described above for writing "0", and "0" can be written in the manner described above for writing "1". Based on this, the bias voltage application principle in the above-mentioned read operation is adopted, and if a high current is read, it indicates that "1" is stored in the storage cell, and if a low current is read, it indicates that "0" is stored in the storage cell.

[0101] To facilitate the application of voltage to the first doped structure 101 and the semiconductor structure 103 and to facilitate the reading of current, the storage cell further includes a first electrode layer 107 and a second electrode layer 108, wherein the first electrode layer 107 is disposed on the semiconductor structure 103 and the second electrode layer 108 is disposed on the first doped structure 101.

[0102] The first electrode layer 107 can be disposed on a region of the semiconductor structure 103 that is not covered by other structures, and the second electrode layer 108 can be disposed on a region of the first doped structure 101 that is not covered by other structures.

[0103] For example, if the storage unit is like Figure 1 As shown, the first electrode layer 107 can be disposed on the upper surface of the semiconductor structure 103, and the second electrode layer 108 can be disposed on the lower surface and / or side surface of the first doped structure 101. If the memory cell is as follows... Figure 5 As shown, the first electrode layer 107 can be disposed on the upper surface of the semiconductor structure 103 and at least one of the three sides of the semiconductor structure 103, wherein the three sides of the semiconductor structure 103 are the sides not covered by the tunneling layer 104. The second electrode layer 108 can be disposed on the lower surface of the first doped structure 101 and at least one of the four sides.

[0104] It should be noted that the positions of the first electrode layer 107 and the second electrode layer 108 described above are merely exemplary and are not intended to limit this application.

[0105] It should be noted that since silicon and germanium have higher carrier mobility and smaller bandgap, if the undoped first doped structure 101 and semiconductor structure 103 are made of silicon or germanium, the conductivity of the device can be improved while the contact resistance with the electrode layer is reduced, thereby improving the read and write speed of the memory cell.

[0106] Below, in conjunction with Figure 1 The structure of the storage unit in the diagram explains the working principle of the storage unit.

[0107] exist Figure 1 In this example, the doping type of the first doped structure 101 is P-type, the doping type of the second doped structure 102 is N-type, the semiconductor structure 103 is a doped semiconductor with the doping type N-type, and the first doped structure 101 and the second doped structure 102 are heavily doped, the semiconductor structure 103 is lightly doped, and the charge trapping layer 105 is an electron trapping layer.

[0108] The principle of write operations is as follows:

[0109] Figure 9 for Figure 1The storage cell in the image is a cross-sectional view along the ab direction when "1" is written. (Example) Figure 9 As shown, when writing "1", both the first electrode layer 107 and the second electrode layer 108 are grounded, thus making the first doped structure 101 and the second doped structure 102 zero biased. A positive bias voltage +V1 is applied to the conductive layer 106, making the voltage difference between the conductive layer 106 and the semiconductor structure 103 +V1. Based on this, electrons in the semiconductor structure 103 pass through the tunneling layer 104 and reach the charge trapping layer 105 under the action of the electric field generated by the positive bias voltage +V1. The charge trapping layer 105 traps electrons, changing the resistance of the memory cell.

[0110] It should be noted that the voltage applied when writing "1" is merely exemplary and is not intended to limit this application. "1" can also be written using other voltage application methods. For example, when writing "1", a positive bias voltage of +1 / 2V1 is applied to the conductive layer 106, a negative voltage of -1 / 2V1 is applied to the first electrode layer 107, and a positive voltage of 1 / 2V1 is applied to the second electrode layer 108. Another example is that when writing "1", a positive bias voltage of +1 / 2V1 is applied to the conductive layer 106, a negative voltage of -1 / 2V1 is applied to the first electrode layer 107, and a negative voltage of -1 / 2V1 is applied to the second electrode layer 108. Yet another example is that when writing "1", a positive bias voltage of +1 / 2V1 is applied to the conductive layer 106, a negative bias voltage of -1 / 2V1 is applied to the first electrode layer 107, and the second electrode layer 108 is grounded.

[0111] It should be noted that when writing "1", regardless of the method of applying voltage, as long as the three conditions required for writing "1" mentioned above are met, "1" can be written.

[0112] Figure 10 for Figure 1 The storage cell in the image is a cross-sectional view along the ab direction when "0" is written. (Example) Figure 10 As shown, when writing "0", both the first electrode layer 107 and the second electrode layer 108 are grounded, making the first doped structure 101 and the second doped structure 102 zero biased; a negative bias voltage -V1 is applied to the conductive layer 106, so that the voltage difference between the conductive layer 106 and the semiconductor structure 103 is -V1; based on this, the charge trapping layer 105 releases the trapped electrons under the action of the electric field generated by the negative bias voltage -V1, that is, the electrons trapped by the charge trapping layer 105 are removed, and the memory cell returns to its original state, changing the resistance of the memory cell.

[0113] It should be noted that the voltage application method described above when writing "0" is merely exemplary and is not intended to limit this application. "0" can also be written using other voltage application methods. For example, when writing "0", a negative bias voltage of -1 / 2V1 is applied to the conductive layer 106, a positive voltage of 1 / 2V1 is applied to the first electrode layer 107, and a negative voltage of -1 / 2V1 is applied to the second electrode layer 108.

[0114] It should be noted that when writing "0", regardless of the method of applying voltage, as long as the three conditions required for writing "0" mentioned above are met, "0" can be written.

[0115] The principle of read operation is as follows:

[0116] The conductive layer 106 is grounded, a negative voltage of -1 / 2V2 is applied to the first electrode layer 107, and a positive voltage of +1 / 2V2 is applied to the second electrode layer 108, so that the first doped structure 101 and the second doped structure 102 are forward biased and the forward bias voltage between the first doped structure 101 and the second doped structure 102 is V2. At this time, if a high current is read from the second electrode layer 108 and the first electrode layer 107, the data "0" is read; if a low current is read from the second electrode layer 108 and the first electrode layer 107, the data "1" is read.

[0117] It should be noted that the voltage application method for the read operation is merely exemplary and is not intended to limit this application. Data can also be read using other voltage application methods. For example, conductive layer 106 is grounded, the first electrode layer 107 is given a negative bias voltage -V2, and the second electrode layer 108 is grounded. Another example is conductive layer 106 grounded, the first electrode layer 107 grounded, and the second electrode layer 108 given a positive bias voltage +V2.

[0118] It should be noted that during the read operation, regardless of the method of applying voltage, as long as the conductive layer 106 is grounded, the first doped structure 101 and the second doped structure 102 are forward biased, and the forward bias voltage between the first doped structure 101 and the second doped structure 102 is greater than or equal to V2, data can be read.

[0119] Below, in Figure 1 In this example, the doping type of the first doped structure 101 is N-type, the doping type of the second doped structure 102 is P-type, the semiconductor structure 103 is a doped semiconductor with a doping type of P-type, and the first doped structure 101 and the second doped structure 102 are heavily doped, the semiconductor structure 103 is lightly doped, and the charge trapping layer 105 is a hole trapping layer are used for illustration.

[0120] The principle of write operations is as follows:

[0121] When writing a "1", both the first electrode layer 107 and the second electrode layer 108 are grounded, thus making the first doped structure 101 and the second doped structure 102 zero bias. A negative bias voltage -V1 is applied to the conductive layer 106, making the voltage difference between the conductive layer 106 and the semiconductor structure 103 -V1. Based on this, holes in the semiconductor structure 103 pass through the tunneling layer 104 and reach the charge trapping layer 105 under the action of the electric field generated by the bias voltage -V1. The charge trapping layer 105 traps the holes, changing the resistance of the memory cell.

[0122] It should be noted that the voltage applied when writing "1" is merely exemplary and not intended to limit this application. "1" can also be written using other voltage application methods. For example, when writing "1", a negative bias voltage of -1 / 2V1 is applied to the conductive layer 106, a positive voltage of +1 / 2V1 is applied to the first electrode layer 107, and a negative voltage of -1 / 2V1 is applied to the second electrode layer 108. Another example is that when writing "1", a negative bias voltage of -1 / 2V1 is applied to the conductive layer 106, a positive voltage of +1 / 2V1 is applied to the first electrode layer 107, and a positive voltage of +1 / 2V1 is applied to the second electrode layer 108. Yet another example is that when writing "1", a negative bias voltage of -1 / 2V1 is applied to the conductive layer 106, a positive voltage of +1 / 2V1 is applied to the first electrode layer 107, and the second electrode layer 108 is grounded.

[0123] It should be noted that when writing "1", regardless of the method of applying voltage, as long as the three conditions required for writing "1" mentioned above are met, "1" can be written.

[0124] When writing "0", both the first electrode layer 107 and the second electrode layer 108 are grounded, thus making the first doped structure 101 and the second doped structure 102 zero bias; a positive bias voltage +V1 is applied to the conductive layer 106, making the voltage difference between the conductive layer 106 and the semiconductor structure 103 +V1; based on this, the charge trapping layer 105 releases the trapped holes under the action of the electric field generated by the positive bias voltage +V1, that is, the holes trapped by the charge trapping layer 105 are removed, and the memory cell returns to its original state, changing the resistance of the memory cell.

[0125] It should be noted that the voltage application method described above when writing "0" is merely exemplary and is not intended to limit this application. "0" can also be written in other ways. For example, a positive bias voltage of +1 / 2V1 can be applied to the conductive layer 106, a negative voltage of -1 / 2V1 can be applied to the first electrode layer 107, and a positive voltage of +1 / 2V1 can be applied to the second electrode layer 108.

[0126] It should be noted that when writing "0", regardless of the method of applying voltage, as long as the three conditions required for writing "0" mentioned above are met, "0" can be written.

[0127] The principle of read operation is as follows:

[0128] The conductive layer 106 is grounded, a positive voltage of +1 / 2V2 is applied to the first electrode layer 107, and a negative voltage of -1 / 2V2 is applied to the second electrode layer 108, so that the first doped structure 101 and the second doped structure 102 are forward biased and the forward bias voltage between the first doped structure 101 and the second doped structure 102 is V2. At this time, if a high current is read from the second electrode layer 108 and the first electrode layer 107, the data "0" is read; if a low current is read from the second electrode layer 108 and the first electrode layer 107, the data "1" is read.

[0129] It should be noted that the voltage application method for the read operation is merely exemplary and is not intended to limit this application. Data can also be read using other voltage application methods. For example, conductive layer 106 is grounded, first electrode layer 107 is grounded, and a negative bias voltage -V2 is applied to second electrode layer 108. As another example, conductive layer 106 is grounded, first electrode layer 107 is positively biased with +V2, and second electrode layer 108 is grounded.

[0130] It should be noted that during the read operation, regardless of the method of applying voltage, as long as the conductive layer 106 is grounded, the first doped structure 101 and the second doped structure 102 are forward biased, and the forward bias voltage between the first doped structure 101 and the second doped structure 102 is greater than or equal to V2, data can be read.

[0131] In summary, the memory cell includes a first doped structure 101, a second doped structure 102, a semiconductor structure 103, a tunneling layer 104, a charge trapping layer 105, and a conductive layer 106, providing a novel and simple structure with easy fabrication and low manufacturing cost. Furthermore, compared to existing methods that utilize the polarization properties of ferroelectric thin films for data storage, the charge trapping layer 105 primarily utilizes bulk and / or interface defects in the material to trap charges for data storage. Therefore, the charge trapping layer 105 can be made thinner, thereby reducing the size of the memory cell and consequently the overall memory size, improving the miniaturization capability of both the memory cell and the memory itself. Moreover, based on the relative positions of the various parts within the memory cell, it is known that this memory cell is a vertical structure. This facilitates the integration of multiple memory cells, enabling three-dimensional stacking of multiple memory cells to achieve a three-dimensional memory. Furthermore, due to the small size of the memory cell, compared to existing memory cells, more memory cells can be integrated into a memory with the same area, increasing the memory cell density. In addition, since charge-trapping devices have a lower operating voltage compared to existing ferroelectric thin films, and the memory cell in this application performs read and write operations through a charge-trapping layer, the operating voltage is reduced and the durability of the memory cell is improved compared to existing ferroelectric thin films.

[0132] To further enhance the retention properties of the charge trapping layer 105 for trapped charges, a dipole is introduced at the interface between the tunneling layer 104 and the charge trapping layer 105. The dipole serves to prevent the charges trapped by the charge trapping layer 105 from passing through the tunneling layer 104 and entering the semiconductor structure 103. The dipole can be located in the charge trapping layer 105 and close to the interface between the tunneling layer 104 and the charge trapping layer 105. Introducing a dipole at the interface between the charge trapping layer 105 and the tunneling layer 104 can be understood as introducing a dipole in a portion of the interface between the charge trapping layer 105 and the tunneling layer 104, or introducing a dipole in all regions of the interface between the charge trapping layer 105 and the tunneling layer 104.

[0133] A dipole can be either positive or negative charge and can generate a built-in electric field. Specifically, there are two types of dipoles: positive dipoles and negative dipoles. A positive dipole is a dipole that can generate a built-in electric field from the charge trapping layer 105 to the tunneling layer 104. The material forming a positive dipole can be, for example, rare earth elements (lanthanum (La), strontium (Sr), scandium (Sc), erbium (Er), etc.), and this application does not make any special limitation on this. A negative dipole is a dipole that can generate a built-in electric field from the tunneling layer 104 to the charge trapping layer 105. The material forming a negative dipole can be, for example, metallic elements (aluminum (Al), niobium (Nb), etc.), and this application embodiment does not make any special limitation on this.

[0134] Different types of charge trapping layers 105 introduce different types of dipoles. Specifically:

[0135] If the charge trapping layer 105 is an electron trapping layer, then the dipole is a positive dipole.

[0136] A built-in electric field is generated by a positive dipole pointing from the charge trapping layer 105 to the tunneling layer 104, which increases the bending of the semiconductor band at the control interface of the conductive layer 106, promotes electron binding, reduces the loss of bound electrons, and thus enhances the electron retention properties of the charge trapping layer 105.

[0137] Figure 11 for Figure 1 A cross-sectional view along the ab direction after a positive dipole is introduced into the storage cell. (Example) Figure 11 As shown, the first doped structure 101 is P-type, the second doped structure 102 and the semiconductor structure 103 are N-type, the charge trapping layer 105 is an electron trapping layer, and the positive dipole generates a built-in electric field (e.g., from the charge trapping layer 105 to the tunneling layer 104) pointing from the charge trapping layer 105 to the tunneling layer 104. Figure 11 (As indicated by the middle arrow).

[0138] Figure 12This is a schematic diagram illustrating the impact of introducing a positive dipole into the band structure of a memory cell. Figure 12 The medium charge trapping layer 105 is an electron trapping layer. For example... Figure 12 As shown, after the introduction of the positive dipole 1202, the positive dipole increases the bending of the energy band 1201 of the semiconductor structure at the interface controlled by the conductive layer 106, promoting the confinement of electrons 1203. E in the figure... f For the Fermi level, E C For the conductor, E V This refers to the price band.

[0139] If the charge trapping layer 105 is a hole trapping layer, then the dipole is a negative dipole.

[0140] A built-in electric field is generated by the negative dipole pointing from the tunneling layer 104 to the charge trapping layer 105, which promotes the accumulation of holes at the control interface of the conductive layer 106, increases the binding of holes by the charge trapping layer 105, reduces the loss of bound holes, and thus enhances the hole retention characteristics of the charge trapping layer 105.

[0141] Figure 13 for Figure 1 A cross-sectional view along the ab direction after a negative dipole is introduced into the storage cell. (Example) Figure 13 As shown, the first doped structure 101 is N-type, the second doped structure 102 and the semiconductor structure 103 are P-type, the charge trapping layer 105 is a hole trapping layer, and the negative dipole generates a built-in electric field (e.g., from the tunneling layer 104 to the charge trapping layer 105) that extends from the tunneling layer 104 to the charge trapping layer 105. Figure 13 (As indicated by the middle arrow).

[0142] Figure 14 This is a schematic diagram illustrating the impact of introducing a negative dipole into the band structure of a memory cell. Figure 14 The medium charge trapping layer 105 is a hole trapping layer. For example... Figure 14 As shown, after the introduction of the negative dipole 1204, the negative dipole 1204 increases the bending of the energy band 1201 of the semiconductor structure at the interface controlled by the conductive layer 106, promoting the confinement of holes 1205. E in the figure... f For the Fermi level, E C For the conductor, E V This refers to the price band.

[0143] The process of introducing dipoles at the interface between the charge trapping layer 105 and the tunneling layer 104 can be achieved through deposition or ion implantation. Specifically, the ion implantation process involves coating the first surface of the charge trapping layer 105 with rare earth elements or metal elements, and then allowing these elements to diffuse at high temperature to the interface between the charge trapping layer 105 and the tunneling layer 104, thus forming dipoles. Clearly, the process of introducing dipoles is simple, compatible with existing CMOS processes, and inexpensive.

[0144] In summary, by introducing a dipole between the charge trapping layer and the tunneling layer, the built-in electric field generated by the dipole can be used to adjust the flat-band voltage and work function of the system, thereby enhancing the charge trapping layer's ability to retain charge and thus improving the storage characteristics of the memory cell.

[0145] Furthermore, to further enhance the charge retention properties of the charge trapping layer in the memory cell and prevent electrons from escaping from the conductive layer to the charge trapping layer, the memory cell also includes a barrier layer. This barrier layer is disposed between the charge trapping layer and the conductive layer to prevent electrons from the conductive layer from injecting into the charge trapping layer and to prevent charges in the charge trapping layer from escaping to the conductive layer.

[0146] For example, Figure 15 For the embodiments of this application in Figure 1 A schematic diagram of the structure after adding a barrier layer to the memory cell. (See diagram below.) Figure 15 As shown, the barrier layer 109 is located between the charge trapping layer 105 and the conductive layer 106.

[0147] The barrier layer can be made of insulating materials such as HfO2 or alumina. It should be noted that if the charge trapping layer 105 is made of HfO2, then the barrier layer can be made of other insulating materials besides HfO2, or HfO2 can be used, but other ions need to be doped into HfO2 to increase the band gap and suppress the escape of the trapped charge.

[0148] Below, with Figure 1 Taking a memory cell as an example, where the first doped structure 101 is P-type doped silicon, the second doped structure 102 and the semiconductor structure 103 are N-type doped silicon, and the first doped structure 101 and the second doped structure 102 are heavily doped, while the semiconductor structure 103 is lightly doped, the fabrication process of the memory cell will be explained. The specific process is as follows:

[0149] Grow a layer of P+ silicon (i.e., P-type heavily doped silicon);

[0150] A layer of N+ silicon (i.e., N-type heavily doped silicon) is grown on P+ silicon;

[0151] A layer of N-silicon (i.e., lightly doped N-type silicon) is grown on N+ silicon;

[0152] An anisotropic etching process is used to etch vertically downwards from N-silicon to the lower surface of P+silicon to obtain a first doped structure 101, a second doped structure 102, and a semiconductor structure 103. The first doped structure 101, the second doped structure, and the semiconductor structure 103 are all cylindrical in shape.

[0153] A tunneling layer 104 is deposited on the side of the cylinder;

[0154] A charge trapping layer 105 is deposited on the tunneling layer 104;

[0155] A conductive layer 106 is deposited on the charge trapping layer 105.

[0156] It should be noted that the manufacturing process of the above-mentioned storage unit is merely exemplary and is not intended to limit this application.

[0157] This application also provides a memory comprising a plurality of memory cells of any of the types described above, a plurality of word lines, a plurality of bit lines, and a plurality of gate lines. Wherein:

[0158] Multiple storage cells are arranged in an array. The array arrangement can be a circular array, a rectangular array, etc., and the embodiments of this application do not impose any special limitations on this.

[0159] Multiple word lines are used to apply voltage to the first doped structure of the memory cell. That is, the first doped structure of the memory cell is connected to the word lines to which the voltage is applied. Specifically, the word lines can be connected through the second electrode layer on the first doped structure of the memory cell.

[0160] Multiple bit lines are used to apply voltage to the semiconductor structure of the memory cell. That is, the semiconductor structure of the memory cell is connected to the bit lines to which the voltage is applied. Specifically, the bit lines can be connected through the first electrode layer on the semiconductor structure of the memory cell.

[0161] Multiple gate lines are used to apply voltage to the conductive layer of the memory cell; that is, the conductive layer of the memory cell is connected to the gate lines to which the voltage is applied.

[0162] If the word lines to which voltages are applied to the first doped structures of at least two memory cells are the same, then the bit lines to which voltages are applied to the semiconductor structures of the at least two memory cells are different.

[0163] If the bit lines to which voltage is applied to the semiconductor structure of at least two memory cells are the same, then the word lines to which voltage is applied to the first doped structure of the at least two memory cells are different.

[0164] The number and arrangement of bit lines, word lines, and gate lines are determined based on the specific array arrangement of multiple memories.

[0165] For example, if multiple storage cells are arranged in a rectangular array, that is, multiple storage cells are arranged in N rows and M columns. N and M are both integers greater than or equal to 1. N and M may be equal or unequal, and the embodiments of this application do not impose special limitations on this.

[0166] Based on this, the number of multiple word lines is N, and the N word lines correspond one-to-one with the N rows of memory cells. Each word line is used to apply voltage to the first doped structure of the corresponding row of memory cells. That is, the first doped structure of each memory cell in each row of memory cells is connected to the corresponding word line.

[0167] The number of multiple bit lines is M, and each of the M bit lines corresponds one-to-one with an M column of memory cells. Each bit line is used to apply voltage to the semiconductor structure of the corresponding column of memory cells. That is, the semiconductor structure of each memory cell in each column of memory cells is connected to the corresponding bit line.

[0168] The number of gate lines can be N, and the N gate lines correspond one-to-one with the N rows of memory cells. Each gate line is used to apply voltage to the conductive layer of the corresponding row of memory cells. That is, the conductive layer of each memory cell in each row of memory cells is connected to the corresponding gate line.

[0169] The number of gate lines can also be M, and the M gate lines correspond one-to-one with the M columns of memory cells. Each gate line is used to apply voltage to the conductive layer of the corresponding column of memory cells, that is, the conductive layer of each memory cell in each column of memory cells is connected to the corresponding gate line.

[0170] In other embodiments of this application, the number of multiple word lines can be M, and the M word lines correspond one-to-one with the M columns of memory cells. Each word line is used to apply a voltage to the first doped structure of the corresponding column of memory cells. The number of multiple bit lines can also be N, and the N bit lines correspond one-to-one with the N rows of memory cells. Each bit line is used to apply a voltage to the semiconductor structure of the corresponding row of memory cells.

[0171] The following explanation uses an example of N=3 and M=3 to illustrate the structure of the memory. Figure 16 This is a schematic diagram of a memory structure including 3 rows and 3 columns of storage units, provided for an embodiment of this application. (See attached diagram.) Figure 16 As shown, the memory includes nine memory cells 100, arranged in a 3x3 grid. There are three word lines (WL), three bit lines (BL), and three gate lines (CL). Each row of memory cells corresponds to one word line, each column of memory cells corresponds to one bit line, and each row of memory cells corresponds to one gate line. Specifically, the first doped structure of each memory cell in a row is connected to the corresponding word line, the conductive layer of each memory cell in a row is connected to the corresponding gate line, and the semiconductor structure of each memory cell in a column is connected to the corresponding bit line.

[0172] The working principle of the memory will be explained below.

[0173] To perform a write operation on a memory cell, a voltage is applied to the memory cell according to the principle described above, so that the memory cell is written with "0" or "1". For other memory cells, the first doped structure and the second doped structure of the memory cell can be set to reverse bias, forward bias or zero bias, and the voltage difference between the conductive layer of the memory cell and the semiconductor structure can be set to be less than +V1 or greater than -V1, so as to avoid performing write operations on other memory cells.

[0174] To perform a read operation from a memory cell, a voltage is applied to that cell according to the principles described above, and the read data ("0" or "1") is determined based on the magnitude of the current. For other memory cells, the first doped structure and the second doped structure are reverse biased or zero biased to avoid performing read operations on other memory cells.

[0175] Below, in conjunction with Figure 16 The principle of how the memory performs write and read operations on the memory cell in the second row and second column is explained. Specifically, it is based on... Figure 16 The memory shown in the figure has a first doped structure of P-type doping, and a second doped structure and a semiconductor structure of N-type doping. The charge trapping layer is an electron trapping layer, which is used as an example for illustration.

[0176] It should be noted that, for ease of description, the storage unit in the second row and second column will be named the target storage unit, that is, the target storage unit in the following text is the storage unit in the second row and second column.

[0177] Figure 17 This is a voltage distribution diagram when a "1" is written to the memory cell in the second row and second column. (Example:) Figure 17 As shown, a negative bias of -1 / 2V1 is applied to the first and third word lines, a positive bias of +1 / 2V1 is applied to the second word line, a zero bias is applied to the first and third gate lines, a positive bias of +1 / 2V1 is applied to the second gate line, a positive bias of +1 / 2V1 is applied to the first and third bit lines, and a negative bias of -1 / 2V1 is applied to the second bit line.

[0178] As can be seen from the above, since the first doped structure and the second doped structure of the target memory cell are forward biased, a forward bias voltage of +1 / 2V1 is applied to the conductive layer of the target memory cell, and the voltage difference between the conductive layer of the target memory cell and the semiconductor structure is +V1. Therefore, the data "1" is written to the target memory cell.

[0179] For the memory cells in the first row and first column, the third row and first column, the first row and third column, and the third row and third column, since the first doped structure and the second doped structure in these four memory cells are reverse biased, and the voltage difference between the conductive layer and the semiconductor structure in these four memory cells is -1 / 2V1, which is less than +V1, no data is written to these four memory cells.

[0180] For the memory cells in the first row and second column and the second row and third column, since the first doped structure and the second doped structure of these two memory cells are 0 biased, and the voltage difference between the conductive layer and the semiconductor structure in these two memory cells is +1 / 2V1, which is less than +V1, no data is written to these two memory cells.

[0181] For the memory cells in the second row and first column and the second row and third column, since the first doped structure and the second doped structure of these two memory cells are 0 biased, the voltage difference between the conductive layer and the semiconductor structure in these two memory cells is 0, that is, less than +V1. Therefore, no data is written to these two memory cells.

[0182] Figure 18 This is a voltage distribution diagram when a "0" is written to the memory cell in the second row and second column. (Example:) Figure 18 As shown, a negative bias of -1 / 2V1 is applied to the first word line, the second word line, and the third word line; a zero bias is applied to the first gate line and the third gate line; a negative bias of -1 / 2V1 is applied to the second gate line; a zero bias is applied to the first bit line and the third bit line; and a positive bias of +1 / 2V1 is applied to the second bit line.

[0183] As can be seen from the above, since the first doped structure and the second doped structure of the target memory cell are reverse biased, a negative bias voltage of -1 / 2V1 is applied to the conductive layer of the target memory cell, and the voltage difference between the conductive layer of the target memory cell and the semiconductor structure is -V1, therefore, the data "0" is written to the target memory cell.

[0184] For the memory cells in the first row and first column, the third row and first column, the first row and third column, and the third row and third column, since the first doped structure and the second doped structure in these four memory cells are reverse biased, and the voltage difference between the conductive layer and the semiconductor structure in these four memory cells is 0, that is, greater than -V1, no data is written to these four memory cells.

[0185] For the memory cells in the first row and second column and the second row and third column, since the first doped structure and the second doped structure of these two memory cells are reverse biased, and the voltage difference between the conductive layer and the semiconductor structure in these two memory cells is -1 / 2V1, which is greater than -V1, no data is written to these two memory cells.

[0186] For the memory cells in the second row and first column and the second row and third column, since the first doped structure and the second doped structure of these two memory cells are reverse biased, the voltage difference between the conductive layer and the semiconductor structure in these two memory cells is -1 / 2V1, which is greater than -V1. Therefore, no data is written to these two memory cells.

[0187] Figure 19 This is a voltage distribution diagram when reading data from the memory cell in the second row and second column. (Example:) Figure 19 As shown, a negative bias of -1 / 2V2 is applied to the first and third word lines, a positive bias of +1 / 2V2 is applied to the second word line, a zero bias is applied to the first, second, and third gate lines, a positive bias of +1 / 2V2 is applied to the first and third bit lines, and a negative bias of -1 / 2V2 is applied to the second bit line.

[0188] As can be seen from the above, since the first doped structure and the second doped structure of the target memory cell are forward biased and the forward bias voltage is equal to V2, a zero bias voltage is applied to the conductive layer of the target memory cell, i.e., grounded. Therefore, the current is read from the target memory cell, and the data read is determined to be "0" or "1" based on the current level.

[0189] For the memory cells in the first row and first column, the third row and first column, the first row and third column, and the third row and third column, since the first doped structure and the second doped structure in these four memory cells are reverse biased, no read operation is performed on these four cells.

[0190] For the memory cells in the first row and second column and the memory cells in the third row and second column, since the first doped structure and the second doped structure of these two memory cells are 0 biased, no read operation is performed on these four cells.

[0191] For the memory cells in the second row and first column, and the memory cells in the second row and third column, since the first doped structure and the second doped structure of these two memory cells are 0 biased, no read operation is performed on these four cells.

[0192] This application also provides a three-dimensional memory, which includes a plurality of memory cells of any of the types described above, a plurality of word lines, a plurality of bit lines, and a plurality of gate lines. Wherein:

[0193] Multiple memory cells are located in different memory layers, and the memory cells in each memory layer are arranged in an array, with each memory layer having the same array arrangement. Multiple word lines are used to apply voltage to the first doped structure in the first memory layer. Multiple bit lines are divided into multiple groups, with the number of groups matching the number of memory layers, and each group of bit lines corresponds one-to-one with multiple memory layers. Each group of bit lines applies voltage to the semiconductor structure of the memory cell in its corresponding memory layer. Each memory layer also has a set of bit lines used to apply voltage to the first doped structure of the memory cell in the memory layer above it. Multiple gate lines are divided into multiple groups, with the number of gate lines matching the number of memory layers, and each group of gate lines corresponds one-to-one with multiple memory layers. Each group of gate lines applies voltage to the memory cell in its corresponding memory layer. A voltage is applied to the conductive layer of the cell; for a memory cell in the first memory layer, if the word lines to which the voltage is applied to the first doped structure of at least two memory cells are the same, then the bit lines to which the voltage is applied to the semiconductor structure of at least two memory cells are different; if the bit lines to which the voltage is applied to the semiconductor structure of at least two memory cells are the same, then the word lines to which the voltage is applied to the first doped structure of at least two memory cells are different; for a memory cell in each of the other memory layers, if the bit lines to which the voltage is applied to the first doped structure of at least two memory cells are the same, then the bit lines to which the voltage is applied to the semiconductor structure of at least two memory cells are different; if the bit lines to which the voltage is applied to the semiconductor structure of at least two memory cells are the same, then the bit lines to which the voltage is applied to the first doped structure of at least two memory cells are different.

[0194] The number and arrangement of bit lines, word lines, and gate lines are determined based on the specific array arrangement of the memory cells in each layer and the number of memory layers.

[0195] For example, the memory cells in each memory layer are arranged in N rows and M columns; the semiconductor structure of the M columns of memory cells in the i-th memory layer corresponds one-to-one with the M column bit lines; the semiconductor structure of the N rows of memory cells in the j-th memory layer corresponds one-to-one with the N rows of bit lines; the first doped structure of the N rows of memory cells in the first memory layer corresponds one-to-one with the N rows of word lines; the first doped structure of the M columns of memory cells in the (i+1)-th memory layer corresponds one-to-one with the M column bit lines corresponding to the i-th memory layer; the first doped structure of the N rows of memory cells in the (j+1)-th memory layer corresponds one-to-one with the N rows of bit lines corresponding to the j-th memory layer; wherein i is an odd number and j is an even number.

[0196] Based on the above arrangement, the number of word lines, bit lines, and gate lines can be calculated, and the arrangement of word lines, bit lines, and gate lines can be determined.

[0197] It should be noted that the above arrangement is merely exemplary and is not intended to limit this application. In other embodiments of this application, the arrangement of storage units in each storage layer and the connection relationship between storage layers may be other feasible methods.

[0198] This application also provides an electronic device, which includes a processor and a storage device, the storage device including any of the aforementioned memory and / or any of the aforementioned three-dimensional memory. The processor is used to perform write operations or read operations on the memory and / or the three-dimensional memory.

[0199] Specifically, electronic devices can be, for example, computers, smartphones, smart TVs, smart set-top boxes, smart routers, digital cameras, and other devices with memory and / or three-dimensional memory. The electronic devices described in this application typically also include input / output devices, display devices, etc. Memory and three-dimensional memory are used to store files, instructions, data, etc., for processor access.

[0200] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage unit, characterized in that, include: A first doped structure, a second doped structure, and a semiconductor structure are sequentially superimposed along a first direction; The semiconductor structure, tunneling layer, and charge trapping layer are sequentially stacked along the second direction; A conductive layer is located on the charge trapping layer; The projections of the tunneling layer, the charge trapping layer, and the conductive layer onto the stacked structure including the first doped structure, the second doped structure, and the semiconductor structure are all within the semiconductor structure; The first doped structure has the opposite doping type to the second doped structure.

2. The storage unit according to claim 1, characterized in that, If the charge trapping layer is an electron trapping layer, then the charge trapping layer is used to trap electrons from the semiconductor structure or release trapped electrons. If the charge trapping layer is a hole trapping layer, then the charge trapping layer is used to trap holes from the semiconductor structure or release trapped holes.

3. The storage unit according to claim 2, characterized in that, The electron trapping layer is made of any one of HfO2, HfSiO, HfAlO, Si3N4, AlN, and InGaZnO; the hole trapping layer is made of any one of HfZrO and NiO.

4. The storage cell according to any one of claims 1 to 3, characterized in that, The first doped structure, the second doped structure, and the semiconductor structure are all cylindrical in shape; or The first doped structure, the second doped structure, and the semiconductor structure are all rectangular parallelepipeds.

5. The storage cell according to any one of claims 1 to 3, characterized in that, The storage unit further includes: A first electrode layer is disposed on the semiconductor structure; The second electrode layer is disposed on the first doped structure.

6. The storage cell according to any one of claims 1 to 3, characterized in that, A dipole is introduced at the interface between the tunneling layer and the charge trapping layer; The dipole is used to prevent the charge trapped by the charge trapping layer from passing through the tunneling layer into the semiconductor structure.

7. The storage unit according to claim 6, characterized in that, If the charge trapping layer is an electron trapping layer, then the dipole is a positive dipole; If the charge trapping layer is a hole trapping layer, then the dipole is a negative dipole.

8. The storage unit according to claim 7, characterized in that, The material forming the positive dipole is a rare earth element, and the material forming the negative dipole is a metallic element.

9. The storage cell according to any one of claims 1 to 3, 7 to 8, characterized in that, The storage unit further includes: A barrier layer is disposed between the charge trapping layer and the conductive layer to prevent electrons in the conductive layer from being injected into the charge trapping layer and to prevent the charge trapped in the charge trapping layer from escaping into the conductive layer.

10. The storage cell according to any one of claims 1 to 3, 7 to 8, characterized in that, The materials of the undoped first doped structure, the undoped second doped structure, and the semiconductor structure are any one of silicon, silicon germanium, and germanium.

11. The storage unit according to claim 1, characterized in that, The material of the tunneling layer is silicon dioxide or aluminum oxide.

12. A memory, characterized in that, include: A plurality of storage cells as described in any one of claims 1 to 11, wherein the plurality of storage cells are arranged in an array; Multiple word lines are used to apply voltage to the first doped structure of the memory cell; Multiple bit lines are used to apply voltage to the semiconductor structure of the memory cell; Multiple gate lines are used to apply voltage to the conductive layer of the memory cell; If the word lines to which voltages are applied to the first doped structures of at least two memory cells are the same, then the bit lines to which voltages are applied to the semiconductor structures of the at least two memory cells are different. If the bit lines to which voltage is applied to the semiconductor structure of at least two memory cells are the same, then the word lines to which voltage is applied to the first doped structure of the at least two memory cells are different.

13. The memory according to claim 12, characterized in that, The plurality of said storage cells are arranged in N rows and M columns; The number of the plurality of word lines is N, and the N word lines correspond one-to-one with the N rows of the memory cells. Each word line is used to apply a voltage to the first doped structure of the corresponding row of the memory cells. The number of the plurality of bit lines is M, and the M bit lines correspond one-to-one with the M columns of the memory cells. Each bit line is used to apply a voltage to the semiconductor structure of the corresponding column of the memory cells. The number of the plurality of gate lines is N, and the N gate lines correspond one-to-one with the N rows of the memory cells. Each gate line is used to apply a voltage to the conductive layer of the corresponding row of the memory cells.

14. A three-dimensional memory, characterized in that, include: A plurality of storage cells as described in any one of claims 1 to 11 above, wherein the plurality of storage cells are located in different storage layers, and the storage cells in each storage layer are arranged in an array, and the array arrangement of each storage layer is the same; Multiple word lines are used to apply voltage to the first doped structure in the first memory layer; Multiple bit lines are divided into multiple groups. The number of bit line groups is the same as the number of memory layers. Each group of bit lines corresponds to a different memory layer. Each group of bit lines is used to apply voltage to the semiconductor structure of the memory cell in the corresponding memory layer. Each set of bit lines corresponding to each memory layer is also used to apply voltage to the first doped structure of the memory cell in the memory layer above it. Multiple gate lines are divided into multiple groups. The number of gate line groups is the same as the number of storage layers. Each group of gate lines corresponds to a different storage layer. Each group of gate lines is used to apply voltage to the conductive layer of the storage cell in the corresponding storage layer. For memory cells in the first memory layer, if the word lines to which voltages are applied to the first doped structures of at least two memory cells are the same, then the bit lines to which voltages are applied to the semiconductor structures of the at least two memory cells are different; if the bit lines to which voltages are applied to the semiconductor structures of at least two memory cells are the same, then the word lines to which voltages are applied to the first doped structures of the at least two memory cells are different. For memory cells in other memory layers, if the bit lines to which the voltage is applied to the first doped structure of at least two memory cells are the same, then the bit lines to which the voltage is applied to the semiconductor structure of the at least two memory cells are different; if the bit lines to which the voltage is applied to the semiconductor structure of at least two memory cells are the same, then the bit lines to which the voltage is applied to the first doped structure of the at least two memory cells are different.

15. The three-dimensional memory according to claim 14, characterized in that, The storage cells in each storage layer are arranged in N rows and M columns; The semiconductor structure of the M columns of memory cells in the i-th memory layer corresponds one-to-one with the M column bit lines; The semiconductor structure of the N rows of memory cells in the j-th memory layer corresponds one-to-one with the N rows of bit lines; The first doped structure of the N rows of memory cells in the first memory layer corresponds one-to-one with the N rows of word lines; The first doped structure of the M column memory cells in the (i+1)th memory layer corresponds one-to-one with the M column bit lines of the i-th memory layer. The first doped structure of the N rows of memory cells in the (j+1)th memory layer corresponds one-to-one with the N rows of bit lines in the jth memory layer. Where i is an odd number and j is an even number.

16. An electronic device, characterized in that, include: Processors and storage devices; The storage device includes the memory as described in claim 12 or 13 and / or the three-dimensional memory as described in claim 14 or 15; The processor is used to perform write or read operations on the memory and / or the three-dimensional memory.

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