A distributed rapid distribution method for active phased array correction data

Abstract

The present application provides a distributed rapid distribution method for active phased array correction data, including: an initial loading operation and a query distribution operation; the initial loading operation is performed after the phased array is powered on, and the correction data stored in the initial data space is loaded into the configuration data space for distributed storage; the query distribution operation is performed in real time during operation, and the correction data in the configuration data space is read with the working state of the phased array and the original beam control code of the array element as the address to obtain the corrected beam control code. The phased array beam control system includes a beam control host and multiple sub-boards; the initial data space is arranged in a large-capacity power-off non-volatile NandFlash storage array of the beam control host, and the configuration data space is arranged in a high-speed random access memory DDR storage array of the sub-board. The present application can realize the distributed rapid distribution of active phased array correction data.

Description

Technical Field

[0001] The present application relates to the technical field of phased array beam control, and in particular to a distributed rapid distribution method for active phased array surface correction data. Background Art

[0002] Active phased arrays have the ability to quickly change beam direction and beam shape, and are widely used in military and communications fields. Phased arrays require that the amplitude and phase between each array element be stable, consistent, and controllable, otherwise it will have an adverse effect on beam forming.

[0003] However, in actual systems, due to differences in component performance, equipment processing and assembly accuracy, and equipment operating frequency and environment, it is difficult to ensure the consistency of the original amplitude and phase of each element of the phased array. Therefore, the phased array must be amplitude-phase corrected, and the beam control code must be corrected with the correction data, and the corrected beam control code is used for phase arrangement. Large broadband phased arrays have a wide operating frequency band and multiple operating modes, and the amount of amplitude-phase correction data is large, requiring a large-capacity, high-performance amplitude-phase correction unit to achieve rapid distribution of correction data.

[0004] However, in the prior art, large-capacity amplitude and phase correction units have not yet achieved rapid distribution of correction data. Summary of the invention

[0005] The present application provides a distributed rapid distribution method for active phased array correction data, which can be used to solve the technical problem of large-capacity amplitude and phase correction units needing to achieve rapid distribution of correction data.

[0006] The present application provides a distributed rapid distribution method for active phased array surface correction data, the method comprising:

[0007] Initial loading operations and query distribution operations;

[0008] Among them, the initial loading operation is performed after the phased array surface is powered on, and the correction data stored in the initial data space is loaded into the configuration data space for distributed storage;

[0009] The query distribution operation is executed in real time during operation, and the correction data in the configuration data space is read with the working state of the phased array surface and the original beam control code of the array element as the address to obtain the corrected beam control code.

[0010] The phased array beam control system includes a beam control host and a plurality of sub-boards;

[0011] The initial data space is arranged in a large-capacity power-off non-volatile NandFlash storage array of the beam control host, and the configuration data space is arranged in a high-speed random access memory DDR storage array of the daughter board;

[0012] The beam control host and sub-board use FPGA as the control core; the beam control host is configured with multiple optical sending modules, and each sub-board is configured with an optical receiving module. Multiple one-to-one optical links are formed between the beam control host and each sub-board. Correction data is transmitted between the beam control host and each sub-board through corresponding optical links, and the correction data is transmitted in the form of data streams.

[0013] Optionally, the correction data structure of the initial data space is as follows: the correction data of each sub-board is taken as a unit and stored in each Plane of the Nand Flash storage array in sequence. If the number of sub-boards exceeds the number of Planes, the excess part is arranged again starting from the Plane. During the initial loading operation, the read operation of the Nand Flash is pipelined between the Planes.

[0014] Optionally, taking daughter board 1 as an example, the initial loading operation includes:

[0015] Step 11, the beam control host receives the initial loading operation instruction and enters the initial loading operation state;

[0016] Step 12, the beam control host sends a request to read the correction data packet 1 of the daughter board 1;

[0017] Step 13, the beam control host waits for data output from daughter board 1;

[0018] Step 14, after the beam control host reads the correction data of the daughter board 1, it adds information such as the message identifier, message length, data type, etc. before the correction data, and transmits it to the daughter board 1 through the optical link;

[0019] Step 15: After receiving the correction data, the daughter board 1 updates the correction data into the DDR storage array according to the data type information.

[0020] Optionally, the initial loading operation of other sub-boards starts from step 12 and ends at step 15, and when sub-board 1 executes step 13, sub-board 2 simultaneously executes step 12, and when sub-board 2 executes step 13, sub-board 3 synchronously executes step 12, and so on.

[0021] Optionally, the correction data structure of the configuration storage space is as follows:

[0022] The DDR memory array includes n DDR chips, each of which contains m banks;

[0023] The storage order stores the array elements in the order of numbering into Bank1 of DDR1, Bank1 of DDR2, ..., Bank1 of DDRn, Bank2 of DDR1, Bank2 of DDR2, ... until all banks are traversed, and then storage starts from Bank1 of DDR1.

[0024] Optionally, taking array element 1 as an example, the query distribution operation includes:

[0025] Step 21, the beam control sub-board receives the query distribution operation instruction and enters the query distribution operation state;

[0026] Step 22, query the correction data of array element 1, query the array element number, the initial amplitude and the initial phase of array element 1 according to the current array plane working frequency, determine the query address of array element 1, and send the query address and the read request to the DDR memory;

[0027] Step 23, waiting for data output of array element 1;

[0028] Step 24: Update the calibration data of array element 1.

[0029] Optionally, the initial test loading operations of other array elements are the same, and when array element 1 executes step 23 , array element 2 executes step 22 at the same time.

[0030] Since the objects of two consecutive operations on the same DDR memory are different banks, there is no pre-charge operation and all operations are executed continuously.

[0031] The present invention can realize distributed rapid distribution of active phased array correction data. In the initial loading operation stage, a large amount of correction data can be quickly loaded into the configuration data space, saving the active phased array preparation time and enabling the array to have combat capability as soon as possible. In the query distribution operation stage, the correction data of each array element, that is, the corrected beam control code, can be quickly obtained to realize rapid switching of the active phased array beam pointing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a correction data structure of the initial data space provided in the embodiment of the present application;

[0033] Figure 2 It is an initial loading operation flow chart of the distributed rapid distribution method of correction data provided by the embodiment of the present application;

[0034] Figure 3 is a correction data structure of the configuration data space provided in the embodiment of the present application;

[0035] Figure 4 It is a query distribution operation flow chart of the distributed rapid distribution method of correction data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0037] The following first introduces the embodiments of the present application with reference to the drawings.

[0038] The present application provides a distributed rapid distribution method for active phased array surface correction data, the method comprising:

[0039] Initial loading operations and query distribution operations;

[0040] Among them, the initial loading operation is performed after the phased array surface is powered on, and the correction data stored in the initial data space is loaded into the configuration data space for distributed storage;

[0041] The query distribution operation is executed in real time during operation, and the correction data in the configuration data space is read with the working state of the phased array surface and the original beam control code of the array element as the address to obtain the corrected beam control code.

[0042] The phased array beam control system includes a beam control host and a plurality of sub-boards;

[0043] The initial data space is arranged in the large-capacity power-off non-volatile Nand Flash storage array of the beam control host, and the configuration data space is arranged in the high-speed random access memory DDR storage array of the daughter board;

[0044] The beam control host and sub-board use FPGA as the control core, making full use of the parallel operation characteristics of FPGA to improve data distribution efficiency; the beam control host is equipped with multiple optical sending modules, and each sub-board is equipped with an optical receiving module. Multiple one-to-one optical links are formed between the beam control host and each sub-board. Correction data is transmitted between the beam control host and each sub-board through corresponding optical links, and the correction data is transmitted in the form of data streams.

[0045] In order to reduce the initial loading operation time, the correction data structure of the initial data space is as follows: the correction data of each sub-board is used as a unit and stored in each Plane of the Nand Flash storage array in sequence. If the number of sub-boards exceeds the number of Planes, the excess part is arranged again starting from the Plane. During the initial loading operation, the reading operation of the Nand Flash is pipelined between the Planes; the waiting time for reading the Nand Flash can be reduced.

[0046] Specifically, for example, the correction data of sub-board 1 is stored in Plane1, the correction data of sub-board 2 is stored in Plane2, ..., the correction data of sub-board 12 is stored in Plane12; since the number of sub-boards exceeds the total number of Planes, the correction data of sub-board 13 is stored in Plane1, the correction data of sub-board 14 is stored in Plane2, and the storage locations of the correction data of other sub-boards are similar.

[0047] Taking daughter board 1 as an example, the initial loading operation includes:

[0048] Step 11, the beam control host receives the initial loading operation instruction and enters the initial loading operation state;

[0049] Step 12, the beam control host sends a request to read the correction data packet 1 of the daughter board 1;

[0050] Step 13, the beam control host waits for data output from daughter board 1;

[0051] Step 14, after the beam control host reads the correction data of the daughter board 1, it adds information such as the message identifier, message length, data type, etc. before the correction data, and transmits it to the daughter board 1 through the optical link;

[0052] Step 15: After receiving the correction data, the daughter board 1 updates the correction data into the DDR storage array according to the data type information.

[0053] The initial loading operation of other sub-boards starts from step 12 and ends at step 15, and when sub-board 1 executes step 13, sub-board 2 executes step 12 at the same time, when sub-board 2 executes step 13, sub-board 3 executes step 12 synchronously, and so on.

[0054] The beam control host continues to request correction data packet 2 from sub-board 1, repeating the above steps until all correction data of sub-array 1 is loaded, and the initial loading operation of sub-board 1 is completed. When sub-board 1 is waiting for data output, sub-board 2 can send a read data request. Since the waiting time for data output is long, data operations between different Planes can be considered as synchronous operations, and read and write operations on the same Plane must wait until the current operation is completed before sending a request. If the initial loading operation time of a single sub-board is T0, the beam control system includes M sub-boards, and the initial data space is composed of N Planes according to the physical structure, then the initial loading operation time of M sub-boards is T0. sum satisfy Much shorter than the time T required to complete the initial loading of M daughter boards in sequence ’ sum =MT0.

[0055] Correction data structure for configuration storage space:

[0056] The DDR memory array includes n DDR chips, each of which contains m banks;

[0057] The storage order stores the array elements in the order of numbering into Bank1 of DDR1, Bank1 of DDR2, ..., Bank1 of DDRn, Bank2 of DDR1, Bank2 of DDR2, ... until all banks are traversed, and then storage starts from Bank1 of DDR1.

[0058] Specifically, for example, the correction data of array element 1 is stored in Bank 1 of DDR1, the correction data of array element 2 is stored in Bank 1 of DDR2, ..., the correction data of array element 16 is stored in Bank 8 of DDR2;

[0059] Since the number of array elements exceeds the total number of banks, the correction data of array element 17 is stored in Bank 1 of DDR1, the correction data of array element 18 is stored in Bank 1 of DDR2, and the correction data storage locations of other array elements are similar.

[0060] Taking array element 1 as an example, the query distribution operation includes:

[0061] Step 21, the beam control sub-board receives the query distribution operation instruction and enters the query distribution operation state;

[0062] Step 22, query the correction data of array element 1, query the array element number, the initial amplitude and the initial phase of array element 1 according to the current array plane working frequency, determine the query address of array element 1, and send the query address and the read request to the DDR memory;

[0063] Step 23, waiting for data output of array element 1;

[0064] Step 24: Update the calibration data of array element 1.

[0065] The initial test loading operation of other array elements is the same, and when array element 1 executes step 23, array element 2 simultaneously executes step 22.

[0066] After all array data are queried and updated, the query distribution operation is completed. When array 1 is waiting for data output, array 2 can continue to send data read requests. The operations on different DDRs can be considered synchronous. Since the two consecutive operations on the same DDR memory are for different banks, there is no pre-charge operation, and all operations can be executed continuously. If the query distribution operation time of a single array element is T0 = T s23 +T others , where T s23 is the time required to execute step 23, T others The time required to execute other steps is: Much shorter than the time T required to complete the query distribution operation of P array elements in sequence ‘ sum =PT0 =PT s23 +PT others .

[0067] The present application is described below in conjunction with two specific embodiments.

[0068] Embodiment 1:

[0069] Take an active phased array as an example. The array includes 48 sub-arrays. The beam control system consists of 1 beam control host and 48 beam control sub-boards. The beam control host and sub-boards use FPGA as the control core. The Nand Flash storage array configured by the beam control host is physically composed of 12 Planes. The DDR storage array configured by the beam control sub-board is composed of 2 DDRs, each of which includes 8 Banks. The beam control host is configured with 48 optical transmission modules, and each sub-board is configured with 1 optical receiving module. 48 one-to-one optical links are formed between the beam control host and each sub-board. The correction data is transmitted between the beam control host and each sub-board through the optical link. The correction data is transmitted in the form of data stream.

[0070] The corrected data structure of the initial data space is as follows Figure 1 As shown, the correction data of sub-boards 1 to 12 are respectively stored in Plane1 to Plane12. Since the number of sub-boards exceeds the number of Planes, the correction data of sub-boards 13 to 24 are respectively stored in Plane1 to Plane12, the correction data of sub-boards 25 to 36 are respectively stored in Plane1 to Plane12, and the correction data of sub-boards 37 to 48 are respectively stored in Plane1 to Plane12.

[0071] The initial loading operation flow chart of the distributed rapid distribution method for correction data is shown in Question 2. For sub-board 1, the initial loading operation includes the following steps:

[0072] Step 11: The beam control host receives the initial loading operation instruction and enters the initial loading operation state;

[0073] Step 12: The beam control host sends a request to read the correction data packet 1 of the daughter board 1. The correction data of the daughter board 1 is stored in Plane1. The correction data of the daughter board is divided into multiple correction data packets according to the transmission length.

[0074] Step 13: The beam control host waits for data output from daughter board 1;

[0075] Step 14: After the beam control host reads the correction data of the daughter board 1, it adds information such as the message identifier, message length, data type, etc. before the correction data, and transmits it to the daughter board 1 through the optical link;

[0076] Step 15: After receiving the correction data, daughter board 1 updates the correction data to two DDR memories according to the data type information;

[0077] Then, the beam control host requests correction data packet 2 of daughter board 1, and repeats steps 12 to 15 until all correction data are loaded, and the initial loading operation of daughter board 1 is completed.

[0078] Thanks to the correction data structure of the initial data space and the parallel operation characteristics of the FPGA, when sub-board 1 executes step 13, sub-board 2 can execute step 12 at the same time. When sub-board 2 executes step 13, sub-board 3 can execute step 12 synchronously, and so on. Since step 13 takes the longest time in the initial loading operation, when sub-board 12 executes step 12, sub-boards 1 to 11 are still executing step 13. Therefore, the initial loading operation of the 12 sub-boards can be considered to be executed in parallel. For different Planes, read and write operations can be executed in parallel, but for the same Plane, it is necessary to wait for the current read and write operation to be completed before executing the next operation. Therefore, sub-board 13 must wait for sub-board 12 to complete step 13 before executing step 12. If the initial loading operation time of a single sub-board is T0, and the correction data structure and operation steps of the initial data space of the present invention are used, the actual initial loading operation time of 48 sub-boards is T0. sum Meet 4T0 <T sum <8T0, much shorter than the initial loading time T required to sequentially complete 48 daughter boards ’ sum =48T0, which greatly improves the efficiency of correction data distribution.

[0079] Embodiment 2:

[0080] Still taking the active phased array as an example, each sub-array has 64 array elements, so each query distribution operation needs to query the correction data of 64 array elements in a certain working state.

[0081] The correction data structure of the configuration storage space is as follows Figure 3 As shown, the DDR storage array is composed of 2 DDRs, each DDR contains 8 banks, the correction data of array element 1 is stored in Bank 1 of DDR1, the correction data of array element 2 is stored in Bank 1 of DDR2, ..., the correction data of array element 16 is stored in Bank 8 of DDR2. Since the number of array elements exceeds the total number of banks, the correction data of array element 17 is stored in Bank 1 of DDR1, the correction data of array element 18 is stored in Bank 1 of DDR2, and the correction data storage locations of other array elements are similar.

[0082] The query distribution operation flow chart of the distributed fast distribution method of correction data is as follows: Figure 4 For array element 1, the query distribution operation includes the following steps:

[0083] Step 21: After receiving the query distribution operation instruction, the beam control sub-board enters the query distribution operation state;

[0084] Step 22: query the correction data of array element 1, calculate the query address Addr1 = {Freq, Ch1, Atten1, Phase1} of array element 1 according to the current array operating frequency Freq, the query array element number Ch1, the initial amplitude Atten1 and the initial phase Phase1 of array element 1, and the data is located in Bank1 of DDR1, and send the address and the read request to DDR1;

[0085] Step 23: Wait for data output from array element 1;

[0086] Step 24: Update the calibration data of array element 1.

[0087] Thanks to the correction data structure of the configuration storage space and the parallel operation characteristics of the FPGA, when array element 1 executes step 23, array element 2 can simultaneously execute step 22, and the operations on different DDRs can be considered as synchronous operations. For the same DDR memory, when two consecutive operations are performed on the same Bank, a pre-charge operation is required, and then a read operation is performed. There is a large delay between the two operations. With the data structure of the present invention, the two operations are performed on different Banks and can be performed simultaneously. For the query distribution operation of a single array element, if the required time T0 = T s23 +T others , where T s23 is the time required to execute step 23, T others is the time required to execute other steps. Since the operations of the two DDRs are executed in parallel, the time required for the query distribution operation of 64 array elements is T sum =T s23 +32T others , which is much shorter than the time T required to execute the query distribution operation in sequence with 64 elements. ‘ sum =64T0, which greatly improves the efficiency of correction data distribution.

[0088] The present invention can realize distributed rapid distribution of active phased array correction data. In the initial loading operation stage, a large amount of correction data can be quickly loaded into the configuration data space, saving the active phased array preparation time and enabling the array to have combat capability as soon as possible. In the query distribution operation stage, the correction data of each array element, that is, the corrected beam control code, can be quickly obtained to realize rapid switching of the active phased array beam pointing.

[0089] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A distributed rapid distribution method for active phased array surface correction data, characterized in that: The method comprises: Initial loading operations and query distribution operations; Among them, the initial loading operation is performed after the phased array surface is powered on, and the correction data stored in the initial data space is loaded into the configuration data space for distributed storage; The query distribution operation is executed in real time during operation, and the correction data in the configuration data space is read using the working state of the phased array surface and the original beam control code of the array element as the address to obtain the corrected beam control code; The phased array beam control system includes a beam control host and a plurality of sub-boards; The initial data space is arranged in a large-capacity power-off non-volatile Nand Flash storage array of the beam control host, and the configuration data space is arranged in a high-speed random access memory DDR storage array of the daughter board; The beam control host and the sub-board use FPGA as the control core; the beam control host is configured with multiple optical transmission modules, and each sub-board is configured with an optical receiving module. A multi-channel one-to-one optical link is formed between the beam control host and each sub-board. The beam control host and each sub-board transmit correction data through the corresponding optical link, and the correction data is transmitted in the form of a data stream; The initial loading operation includes: Step 11, the beam control host receives the initial loading operation instruction and enters the initial loading operation state; Step 12, the beam control host sends a request to read a first calibration data packet of a first sub-board; Step 13, the beam control host waits for data output from the first daughter board; Step 14, after the beam control host reads the correction data of the first daughter board, it adds a message identifier, message length, and data type before the correction data, and transmits it to the first daughter board through the optical link; Step 15, after receiving the correction data, the first daughter board updates the correction data to the DDR storage array according to the data type information; Query distribution operations include: Step 21, the beam control sub-board receives the query distribution operation instruction and enters the query distribution operation state; Step 22, query the correction data of the first array element, query the array element number, the initial amplitude and the initial phase of the first array element according to the current array operating frequency, determine the query address of the first array element, and send the query address and the read request to the DDR memory; Step 23, waiting for data output of the first array element; Step 24: Update the calibration data of the first array element.

2. The method according to claim 1, characterized in that The correction data structure of the initial data space is as follows: the correction data of each sub-board is taken as a unit and stored in each Plane of the NandFlash storage array in sequence. If the number of sub-boards exceeds the number of Planes, the excess part is arranged again starting from the Plane. During the initial loading operation, the read operation of Nand Flash is pipelined between each Plane.

3. The method according to claim 2, characterized in that The initial loading operation of other sub-boards starts from step 12 and ends at step 15, and when the first sub-board executes step 13, the second sub-board executes step 12 at the same time, when the second sub-board executes step 13, the third sub-board executes step 12 synchronously, and so on.

4. The method according to claim 1, characterized in that: The correction data structure of the configuration storage space is as follows: The DDR memory array includes n DDR chips, each of which contains m banks; The storage order is to store the array elements in the order of numbering in Bank1 of DDR1, Bank1 of DDR2, ..., Bank1 of DDRn, Bank2 of DDR1, Bank2 of DDR2, ... until all banks are traversed, and then start storing from Bank1 of DDR1.

5. The method according to claim 4, characterized in that The initial test loading operation of other array elements is the same, and when the first array element executes step 23, the second array element executes step 22 at the same time. Since the objects of two consecutive operations on the same DDR memory are different banks, there is no pre-charge operation and all operations are executed continuously.

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