Method and apparatus for detecting memory

Abstract

The application relates to a memory detection method and a detection device. The memory detection method comprises the following steps: writing data into a to-be-detected memory, the to-be-detected memory comprising a storage unit, a redundant unit and a fuse, the fuse being used for replacing the storage unit with the redundant unit; adjusting the temperature of the to-be-detected memory, repeatedly refreshing the to-be-detected memory and repeatedly recording the state of the fuse in the process of changing the temperature of the to-be-detected memory; judging whether the temperature of the to-be-detected memory is stable at a preset temperature, if yes, reading the data of the to-be-detected memory; judging whether the read data of the to-be-detected memory is accurate, if no, determining that the fuse has a defect. The test method is simple, does not need to increase additional test steps and does not need to increase additional test time, can efficiently screen out defective fuses, and reduces the failure probability of a client.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a memory detection method and a detection device. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, which is composed of a plurality of memory cells, each memory cell usually including a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] In dynamic random access memory, fuses are widely used to repair failed memory cells in the memory array, thereby improving product yield and reducing production costs. However, the increase of fuse circuits itself also puts additional requirements on the testing of dynamic random access memory products. There is currently no effective method to detect the performance of the fuse, thereby burying quality risks for the application of memory products in the market.

[0004] Therefore, how to simplify the detection operation of fuse defects, efficiently screen out defective fuses, and improve the yield of the memory is a technical problem to be solved at present. SUMMARY

[0005] Some embodiments of the present application provide a memory detection method and a detection device for simplifying the detection operation of fuse defects, efficiently screening out defective fuses, and improving the yield of the memory.

[0006] According to some embodiments, the present application provides a memory detection method, comprising the following steps:

[0007] writing data to a to-be-tested memory, the to-be-tested memory including a failed memory cell, a fuse, and a redundant cell replacing the failed memory cell through the fuse;

[0008] adjusting the temperature of the to-be-tested memory, and repeatedly refreshing the to-be-tested memory and repeatedly entering the state of the fuse during the change of the temperature of the to-be-tested memory;

[0009] determining whether the temperature of the to-be-tested memory is stable at a preset temperature, and if so, reading the data of the to-be-tested memory;

[0010] determining whether the read data of the to-be-tested memory is accurate, and if not, determining that the fuse has a defect.

[0011] In some embodiments, the memory under test comprises a plurality of memory cells, and the plurality of memory cells are arranged into a memory array, the memory array comprising at least one failed memory cell replaced by the redundant cell through the fuse; the specific step of writing data into the memory under test comprises:

[0012] writing data into the memory under test until the memory array is full.

[0013] In some embodiments, the specific step of adjusting the temperature of the memory under test comprises:

[0014] continuously increasing the temperature of the memory under test.

[0015] In some embodiments, the specific steps of repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature change of the memory under test comprise:

[0016] repeating the following steps during the temperature increase of the memory under test:

[0017] refreshing the memory array;

[0018] recording the state of the fuse.

[0019] In some embodiments, the specific steps of repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature change of the memory under test comprise:

[0020] repeating the steps of refreshing the memory under test and recording the state of the fuse every first predetermined time interval during the temperature increase of the memory under test.

[0021] In some embodiments, the specific steps of repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature change of the memory under test comprise:

[0022] repeating the steps of refreshing the memory under test and recording the state of the fuse every first predetermined temperature interval during the temperature increase of the memory under test.

[0023] In some embodiments, the specific step of determining whether the temperature of the memory under test is stable at a preset temperature, and if so, reading data from the memory under test comprises:

[0024] determining whether the temperature of the memory under test is stable at a first sub-pre-set temperature, and if so, reading data from the memory array.

[0025] In some embodiments, the first sub-pre-set temperature is 30-120℃.

[0026] In some embodiments, after determining that the temperature of the storage under test is stabilized at the first sub-pre-set temperature and reading the data in the storage array, the method further comprises the steps of:

[0027] continuously lowering the temperature of the storage under test, and repeating the steps of refreshing the storage under test and recording the state of the fuse during the lowering of the temperature of the storage under test;

[0028] determining whether the temperature of the storage under test is stabilized at a second sub-pre-set temperature, and if so, reading the data in the storage array, the second sub-pre-set temperature being lower than the first sub-pre-set temperature.

[0029] In some embodiments, the second sub-pre-set temperature is 10℃ to -30℃.

[0030] In some embodiments, before lowering the temperature of the storage under test, the method further comprises the step of:

[0031] maintaining the first sub-pre-set temperature for a pre-set time.

[0032] In some embodiments, the steps of repeating the refreshing of the storage under test and the recording of the state of the fuse during the lowering of the temperature of the storage under test comprise the steps of:

[0033] performing the steps of refreshing the storage under test and recording the state of the fuse every second pre-determined time interval during the lowering of the temperature of the storage under test.

[0034] In some embodiments, the steps of repeating the refreshing of the storage under test and the recording of the state of the fuse during the lowering of the temperature of the storage under test comprise the steps of:

[0035] performing the steps of refreshing the storage under test and recording the state of the fuse every second pre-determined temperature interval during the lowering of the temperature of the storage under test.

[0036] In some embodiments, the step of determining whether the data of the storage under test read is accurate, if not, determining that the fuse has a defect comprises the steps of:

[0037] determining whether the data in the storage array read at the first sub-pre-set temperature and the data in the storage array read at the second sub-pre-set temperature are both accurate, and if not, determining that the fuse has a defect.

[0038] In some embodiments, the rate of lowering the temperature of the storage under test is less than the rate of raising the temperature of the storage under test.

[0039] In some embodiments, the memory is a DRAM memory, and the fuse is an electrically programmable fuse.

[0040] According to another aspect, the present application provides a memory testing device, comprising:

[0041] a writing circuit configured to write data to a memory under test, the memory under test comprising a failed memory cell, a fuse, and a redundant cell replacing the failed memory cell via the fuse;

[0042] a temperature adjuster configured to adjust a temperature of the memory under test;

[0043] a processor configured to repeatedly refresh the memory under test and repeatedly record a state of the fuse during a temperature change of the memory under test;

[0044] a reading circuit configured to determine whether the temperature of the memory under test is stable at a preset temperature, and if so, read data of the memory under test;

[0045] a controller configured to determine whether the read data of the memory under test is accurate, and if not, determine that the fuse has a defect.

[0046] In some embodiments, the memory under test comprises a plurality of memory cells, and the plurality of memory cells are arranged into a memory array, the memory array comprising at least one failed memory cell replaced by the redundant cell via the fuse;

[0047] the writing circuit is configured to write data to the memory under test until the memory array is full.

[0048] In some embodiments, the temperature adjuster is configured to continuously increase the temperature of the memory under test.

[0049] In some embodiments, the processor is configured to repeatedly perform the following steps during the temperature increase of the memory under test:

[0050] refresh the memory array;

[0051] record the state of the fuse.

[0052] In some embodiments, the processor is configured to perform the steps of refreshing the memory under test and recording the state of the fuse every first predetermined time interval during the temperature increase of the memory under test.

[0053] In some embodiments, the processor is configured to perform the steps of refreshing the memory under test and recording the state of the fuse every first predetermined temperature interval during the temperature increase of the memory under test.

[0054] In some embodiments, the reading circuit is configured to determine whether the temperature of the memory under test is stabilized at a first sub-predefined temperature, and if so, read data in the memory array.

[0055] In some embodiments, the temperature adjuster is further configured to, after determining that the temperature of the memory under test is stabilized at the first sub-predefined temperature and reading data in the memory array, continuously decrease the temperature of the memory under test.

[0056] The processor is further configured to repeatedly refresh the memory under test and repeatedly record the state of the fuse during the process of decreasing the temperature of the memory under test.

[0057] The reading circuit is further configured to determine whether the temperature of the memory under test is stabilized at a second sub-predefined temperature, and if so, read data in the memory array, the second sub-predefined temperature being lower than the first sub-predefined temperature.

[0058] In some embodiments, the processor is further configured to, during the process of decreasing the temperature of the memory under test, perform the steps of refreshing the memory under test and recording the state of the fuse at a second predetermined time interval.

[0059] In some embodiments, the processor is further configured to, during the process of decreasing the temperature of the memory under test, perform the steps of refreshing the memory under test and recording the state of the fuse at a second predetermined temperature interval.

[0060] In some embodiments, the controller is configured to determine whether the data in the memory array read at the first sub-predefined temperature and the data in the memory array read at the second sub-predefined temperature are both accurate, and if not, determine that the fuse has a defect.

[0061] In some embodiments, the memory is a DRAM memory, and the fuse is an electrically programmable fuse.

[0062] The memory detection method and detection device provided in some embodiments of the present application adjust the temperature of the memory under test, and repeatedly refresh the memory under test and record the state of the fuse during the process of changing the temperature of the memory under test. If there is a process of changing the state of the fuse during the process of changing the temperature, the error array will be refreshed, resulting in error data in the final reading. The memory detection method and detection device provided in some embodiments of the present application have a simple test method, do not need to increase additional test steps, and do not need to increase additional test time, can efficiently screen out defective fuses, reduce the probability of client failure, and improve the yield of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 2 is a flow chart of a method for detecting a memory according to an embodiment of the present application; Figure 1 Figure 3 is a schematic diagram of a change in temperature over time according to an embodiment of the present application;

[0064] Figure 4 is a structure block diagram of a detection device for a memory according to an embodiment of the present application; Figure 2 Figure 5 is a schematic diagram of a change in temperature over time according to an embodiment of the present application;

[0065] Figure 6 is a schematic diagram of a storage array after a redundant unit replaces a storage unit according to an embodiment of the present application; Figure 3 Figure 7 is a structure block diagram of a detection device for a memory according to an embodiment of the present application.

[0066] Figure 8 is a structure block diagram of a detection device for a memory according to an embodiment of the present application. Figure 4 Figure 9 is a structure block diagram of a detection device for a memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] The embodiments of the method for detecting a memory and the detection device for a memory provided by the present application will be described in detail below with reference to the accompanying drawings.

[0068] The embodiments of the present application provide a method for detecting a memory, and the method comprises the following steps: Figure 1 Figure 1 is a flow chart of a method for detecting a memory according to an embodiment of the present application. As shown in Figure 1, the method for detecting a memory comprises the following steps: Figure 1

[0069] Step S11, write data to a to-be-detected memory, the to-be-detected memory comprising a failed storage unit, a fuse, and a redundant unit replacing the failed storage unit through the fuse.

[0070] In some embodiments, the to-be-detected memory comprises a plurality of storage units, and the plurality of storage units are arranged into a storage array, the storage array comprising at least one failed storage unit replaced by the redundant unit through the fuse; the specific step of writing data to the to-be-detected memory comprises:

[0071] write data to the to-be-detected memory until the storage array is full.

[0072] In some embodiments, the memory is a DRAM memory, and the fuse is an electrically programmable fuse (E-fuse). The following is described by taking the fuse as an electrically programmable fuse as an example. The electric fuse comprises a cathode, an anode, and a fuse chain, one end of the fuse chain is connected to the cathode, and the other end of the fuse chain is connected to the anode, and the electrically programmable fuse can be broken under the action of electromigration.

[0073] Figure 5 is a schematic diagram of a change in temperature over time according to an embodiment of the present application; Figure 3 Figure 6 is a schematic diagram of a storage array after a redundant unit replaces a storage unit according to an embodiment of the present application; Figure 3 ​As shown, the to-be-tested memory includes a storage array, and a first redundant row R1 and a second redundant row R2 outside the storage array, the storage array includes a plurality of storage units 30 arranged in an array, and the first redundant row R1 and the second redundant row R2 each include a plurality of redundant units 31. For example, when the storage units 30 in the 0th row and the 2nd row of the storage array fail (i.e. are defective), the first redundant row R1 can replace the 0th row of the storage array and the second redundant row R2 can replace the 2nd row of the storage array by fusing the fuses, so as to repair the storage array.

[0074] After the present specific embodiment replaces the defective storage units in the to-be-tested memory with the redundant units, the entire storage space of the to-be-tested memory is filled with data, i.e. all the storage units of the to-be-tested memory and the redundant units that have replaced the defective storage units are filled with data.

[0075] In step S12, the temperature of the to-be-tested memory is adjusted, and the refreshing of the to-be-tested memory and the recording of the state of the fuses are repeated while the temperature of the to-be-tested memory changes.

[0076] In some embodiments, the specific steps of adjusting the temperature of the to-be-tested memory include:

[0077] Continuously increasing the temperature of the to-be-tested memory.

[0078] In some embodiments, the specific steps of repeating the refreshing of the to-be-tested memory and the recording of the state of the fuses while the temperature of the to-be-tested memory changes include:

[0079] The following steps are repeatedly performed while the temperature of the to-be-tested memory increases:

[0080] Refreshing the storage array;

[0081] Recording the state of the fuses.

[0082] Figure 2 is a schematic diagram of the temperature change over time in the present specific embodiment. Specifically, as shown in Figure 2, the temperature of the to-be-tested memory is increased from room temperature to a high temperature, and then decreased to room temperature. Figure 2 Figure 2 ​In the first phase P1, the temperature of the memory under test is continuously increased by increasing the temperature of the test machine carrying the memory under test. During the temperature increase of the memory under test (i.e. in the first phase P1), refresh operations can be performed on the memory array according to JEDEC (Joint Electron Device Engineering Council) specification, and the operation of re-entering the state of the fuse into the register of the memory under test can be inserted between two adjacent refresh operations. The refresh operation and the operation of re-entering the state of the fuse are alternately performed during the temperature increase of the memory under test.

[0083] In some embodiments, the specific steps of repeatedly refreshing the memory under test and repeatedly re-entering the state of the fuse during the temperature change of the memory under test include:

[0084] During the temperature increase of the memory under test, the steps of refreshing the memory under test and re-entering the state of the fuse are performed every first predetermined time interval.

[0085] Specifically, during the temperature increase of the memory under test, the refresh operation and the operation of re-entering the state of the fuse can be performed in equal time intervals, so as to control the frequency of performing the refresh operation and the operation of re-entering the state of the fuse, thereby more accurately and quickly locating the memory cell where the error occurs. The specific value of the first predetermined time interval can be selected by those skilled in the art according to actual needs, for example, it can be 30s, 1min, 2min, or 5min.

[0086] In some embodiments, the specific steps of repeatedly refreshing the memory under test and repeatedly re-entering the state of the fuse during the temperature change of the memory under test include:

[0087] During the temperature increase of the memory under test, the steps of refreshing the memory under test and re-entering the state of the fuse are performed every first predetermined temperature interval.

[0088] Specifically, during the temperature increase of the memory under test, the refresh operation and the operation of re-entering the state of the fuse can be performed in equal temperature intervals, so as to accurately know the temperature that causes the state of the fuse to change, i.e. accurately know the temperature that causes the fuse to be abnormal. The specific value of the first predetermined temperature interval can be selected by those skilled in the art according to actual needs, for example, it can be 1℃, 2℃, 5℃ or 10℃.

[0089] Step S13: Determine whether the temperature of the memory under test is stable at a preset temperature. If so, read the data of the memory under test.

[0090] Step S14: Determine whether the data read from the memory under test is accurate. If not, determine that the fuse has a defect.

[0091] In some embodiments, the specific steps for determining whether the temperature of the memory under test is stable at a preset temperature, and if so, for reading the data of the memory under test, include:

[0092] Determine whether the temperature of the memory under test is stable at a first preset temperature; if so, read the data from the memory array.

[0093] Specifically, the temperature of the memory under test stabilizes at the first preset temperature (for example, the memory under test reaches...). Figure 2 After the second stage (P2) in the process, data is read from the storage array of the memory under test. Changes in the temperature of the memory under test cause changes in the state of the fuse. For example, when the temperature of the memory under test is within a threshold temperature range, the fuse remains in a continuous state; however, when the temperature of the memory under test reaches the threshold temperature, the fuse changes from a continuous state to a burned-out state due to the presence of a defect. Since the fuse is used to replace the storage cell with the redundant unit, changes in the state of the fuse can lead to errors in the data read from the redundant unit. Based on the above principle, when errors occur in the data read from the memory under test, it can be determined that the fuse in the memory under test has a defect.

[0094] In some embodiments, the first sub-preset temperature is 30°C to 120°C. In one example, the first sub-preset temperature can be 30°C, 40°C, 50°C, 88°C, or 100°C.

[0095] In some embodiments, after determining that the temperature of the memory under test has stabilized at a first sub-preset temperature and reading the data in the memory array, the following steps are further included:

[0096] The temperature of the memory under test is continuously reduced, and the memory under test is repeatedly refreshed and the status of the fuse is repeatedly recorded during the process of temperature reduction.

[0097] Determine whether the temperature of the memory under test is stable at the second sub-preset temperature. If so, read the data in the memory array. The second sub-preset temperature is lower than the first sub-preset temperature.

[0098] In some embodiments, the second sub preset temperature is 10°C to -30°C. In an example, the first sub preset temperature can be 10°C, 0°C, -10°C, -15°C or -20°C.

[0099] In some embodiments, before reducing the temperature of the to-be-tested memory, the method further comprises the following steps:

[0100] The first sub preset temperature is maintained for a preset time.

[0101] Specifically, in order to comprehensively reflect the influence of temperature change (including high temperature and low temperature) on the fuse in the to-be-tested memory, after the to-be-tested memory reaches the first sub preset temperature through the temperature rising process and is stabilized for a preset time, the to-be-tested memory can be subjected to a temperature reduction process, i.e., the to-be-tested memory is caused to enter Figure 2 a third phase P3. In the process of reducing the temperature of the to-be-tested memory (i.e., in the third phase P3), the memory array can also be subjected to a refresh operation according to the JEDEC specification, and an operation of re-entering the state of the fuse into the register of the to-be-tested memory can be inserted between two adjacent refresh operations. The refresh operation and the operation of re-entering the state of the fuse are alternately performed in cycles in the process of reducing the temperature of the to-be-tested memory.

[0102] In some embodiments, the specific steps of repeatedly refreshing the to-be-tested memory and repeatedly entering the state of the fuse in the process of reducing the temperature of the to-be-tested memory comprise:

[0103] In the process of reducing the temperature of the to-be-tested memory, the steps of refreshing the to-be-tested memory and entering the state of the fuse are performed every second predetermined time.

[0104] Specifically, in the process of reducing the temperature of the to-be-tested memory, the to-be-tested memory can be subjected to the refresh operation and the operation of re-entering the state of the fuse in an equal time interval manner, so as to control the frequency of performing the refresh operation and the operation of re-entering the state of the fuse, thereby being able to more accurately and quickly locate the storage unit where the error occurs. The second predetermined time can be the same as or different from the first predetermined time.

[0105] In some embodiments, the specific steps of repeatedly refreshing the to-be-tested memory and repeatedly entering the state of the fuse in the process of reducing the temperature of the to-be-tested memory comprise:

[0106] In the process of reducing the temperature of the to-be-tested memory, the steps of refreshing the to-be-tested memory and entering the state of the fuse are performed every second predetermined temperature interval.

[0107] Specifically, during the process of lowering the temperature of the to-be-tested memory, the to-be-tested memory can be refreshed and the state of the fuse can be re-entered in an equal temperature interval, so as to accurately obtain the temperature that causes the state of the fuse to change, that is, the temperature that causes the fuse to be abnormal. The second predetermined temperature interval can be the same as or different from the first predetermined temperature interval.

[0108] In some embodiments, if the read data of the to-be-tested memory is not accurate, the specific step of determining that the fuse has a defect includes:

[0109] determining whether the data in the memory array read at the first sub-pre-set temperature and the data in the memory array read at the second sub-pre-set temperature are both accurate, and if not, determining that the fuse has a defect.

[0110] Specifically, if the data in the memory array read at the first sub-pre-set temperature and the data in the memory array read at the second sub-pre-set temperature are both accurate, it indicates that the temperature rising process and the temperature lowering process do not cause the state of the fuse to change, that is, it is determined that the fuse does not have a defect. If one or both of the data in the memory array read at the first sub-pre-set temperature and the data in the memory array read at the second sub-pre-set temperature are not accurate, it is determined that the fuse has a defect.

[0111] In some embodiments, the temperature lowering rate of the to-be-tested memory is less than the temperature rising rate of the to-be-tested memory. This can avoid the temperature of the to-be-tested memory from being lowered too quickly and causing damage to the film layer inside the to-be-tested memory.

[0112] The application also provides a memory detection device, and the accompanying Figure 4 is a structure block diagram of the memory detection device in the specific embodiment of the application. The memory detection device provided in the specific embodiment can detect the memory by using the memory detection method as shown in Figures 1-3 As shown in FIG. 4, the memory detection device includes: Figure 4 The write circuit 40 is configured to write data to the to-be-tested memory, and the to-be-tested memory includes a failed memory cell, a fuse, and a redundant cell replacing the failed memory cell through the fuse.

[0113] The temperature adjuster 41 is configured to adjust the temperature of the to-be-tested memory.

[0114]

[0115] ​a processor 42 configured to repeatedly refresh the memory under test and to repeatedly record the status of the fuse during a temperature change of the memory under test;

[0116] a reading circuit 43 configured to determine whether the temperature of the memory under test is stable at a preset temperature, and if so, to read data from the memory under test;

[0117] a controller 44 configured to determine whether the data read from the memory under test is accurate, and if not, to determine that the fuse is defective.

[0118] The specific structure of the writing circuit 40 can be set by those skilled in the art according to actual needs, as long as the writing of data can be achieved. The specific structure of the reading circuit 43 can be set by those skilled in the art according to actual needs, as long as the determination of whether the temperature of the memory under test is stable at a preset temperature and the reading of data can be achieved.

[0119] In some embodiments, the memory under test includes a plurality of memory cells, and the plurality of memory cells are arranged into a memory array, and the memory array includes at least one failed memory cell replaced by the redundant cell through the fuse;

[0120] The writing circuit 40 is configured to write data to the memory under test until the memory array is full.

[0121] In some embodiments, the temperature adjuster 41 is configured to continuously increase the temperature of the memory under test.

[0122] In some embodiments, the processor 42 is configured to repeatedly perform the following steps during the temperature increase of the memory under test:

[0123] refreshing the memory array;

[0124] recording the status of the fuse.

[0125] In some embodiments, the processor 42 is configured to perform the steps of refreshing the memory under test and recording the status of the fuse every first predetermined time interval during the temperature increase of the memory under test.

[0126] In some embodiments, the processor 42 is configured to perform the steps of refreshing the memory under test and recording the status of the fuse every first predetermined temperature interval during the temperature increase of the memory under test.

[0127] In some embodiments, the reading circuit 43 is configured to determine whether the temperature of the memory under test is stable at a first sub-pre-set temperature, and if so, to read data from the memory array.

[0128] In some embodiments, the temperature adjuster 41 is further configured to continuously decrease the temperature of the memory under test after determining that the temperature of the memory under test is stabilized at the first sub-predefined temperature and reading the data in the memory array.

[0129] The processor 42 is further configured to repeatedly refresh the memory under test and repeatedly record the state of the fuse during the process of decreasing the temperature of the memory under test.

[0130] The read circuit 43 is further configured to determine whether the temperature of the memory under test is stabilized at a second sub-predefined temperature, and if so, read the data in the memory array, the second sub-predefined temperature being lower than the first sub-predefined temperature.

[0131] In some embodiments, the processor 42 is further configured to perform the steps of refreshing the memory under test and recording the state of the fuse every second predetermined time interval during the process of decreasing the temperature of the memory under test.

[0132] In some embodiments, the processor 42 is further configured to perform the steps of refreshing the memory under test and recording the state of the fuse every second predetermined temperature interval during the process of decreasing the temperature of the memory under test.

[0133] In some embodiments, the controller 44 is configured to determine whether the data in the memory array read at the first sub-predefined temperature and the data in the memory array read at the second sub-predefined temperature are both accurate, and if not, determine that the fuse has a defect.

[0134] In some embodiments, the memory is a DRAM memory, and the fuse is an electrically programmable fuse.

[0135] The memory detection method and the detection device provided in the foregoing specific embodiments of the present application adjust the temperature of the memory under test, and repeatedly refresh the memory under test and record the state of the fuse during the process of changing the temperature of the memory under test. If there is a process of changing the state of the fuse during the process of changing the temperature, the error array will be refreshed, resulting in error data read finally. The memory detection method and the detection device provided in some embodiments of the present application have a simple test method, do not need to increase additional test steps, and do not need to increase additional test time, and can efficiently screen out defective fuses, reduce the probability of client failure, and improve the yield of the memory.

[0136] The above merely describes the preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, some improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A method of detecting a memory, characterized by, The method comprises the following steps: writing data into a to-be-tested memory, the to-be-tested memory comprising a failed memory cell, a fuse, and a redundant cell replacing the failed memory cell through the fuse; adjusting the temperature of the to-be-tested memory, and repeatedly refreshing the to-be-tested memory and repeatedly recording the state of the fuse during the change of the temperature of the to-be-tested memory; judging whether the temperature of the to-be-tested memory is stable at a preset temperature, and if yes, reading the data of the to-be-tested memory; judging whether the read data of the to-be-tested memory is accurate, and if no, determining that the fuse has a defect; wherein the to-be-tested memory comprises a plurality of memory cells arranged into a memory array, and the memory array comprises at least one failed memory cell replaced by the redundant cell through the fuse; the step of writing data into the to-be-tested memory comprises: writing data into the to-be-tested memory until the memory array is full.

2. The memory detection method of claim 1, wherein, The step of adjusting the temperature of the to-be-tested memory comprises: continuously increasing the temperature of the to-be-tested memory.

3. The memory detection method according to claim 2, wherein, The step of repeatedly refreshing the to-be-tested memory and repeatedly recording the state of the fuse during the change of the temperature of the to-be-tested memory comprises: repeatedly performing the following steps during the increase of the temperature of the to-be-tested memory: refreshing the memory array; recording the state of the fuse.

4. The memory detection method of claim 2, wherein, The step of repeatedly refreshing the to-be-tested memory and repeatedly recording the state of the fuse during the change of the temperature of the to-be-tested memory comprises: performing the steps of refreshing the to-be-tested memory and recording the state of the fuse once every first predetermined time interval during the increase of the temperature of the to-be-tested memory.

5. The memory detection method of claim 2, wherein, The step of repeatedly refreshing the to-be-tested memory and repeatedly recording the state of the fuse during the change of the temperature of the to-be-tested memory comprises: performing the steps of refreshing the to-be-tested memory and recording the state of the fuse once every first predetermined temperature interval during the increase of the temperature of the to-be-tested memory.

6. The memory detection method of claim 2, wherein, The step of judging whether the temperature of the to-be-tested memory is stable at a preset temperature, and if yes, reading the data of the to-be-tested memory comprises: judging whether the temperature of the to-be-tested memory is stable at a first sub-pre-set temperature, and if yes, reading the data in the memory array.

7. The memory detection method according to claim 6, wherein, The first sub-pre-set temperature is 30-120℃.

8. The memory detection method of claim 6, wherein, After determining that the temperature of the to-be-tested memory is stable at the first sub-pre-set temperature and reading the data in the memory array, the method further comprises the following steps: continuously decreasing the temperature of the to-be-tested memory, and repeatedly refreshing the to-be-tested memory and repeatedly recording the state of the fuse during the decrease of the temperature of the to-be-tested memory; judging whether the temperature of the to-be-tested memory is stable at a second sub-pre-set temperature, and if yes, reading the data in the memory array, the second sub-pre-set temperature being lower than the first sub-pre-set temperature.

9. The memory detection method according to claim 8, wherein, The second sub-pre-set temperature is 10-30℃.

10. The memory detection method of claim 8, wherein, Before decreasing the temperature of the to-be-tested memory, the method further comprises the following step: maintaining the first sub-pre-set temperature for a preset time.

11. The memory detection method of claim 8, wherein, The specific steps of repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature decrease of the memory under test include: The steps of refreshing the memory under test and recording the state of the fuse are performed every second predetermined time interval during the temperature decrease of the memory under test.

12. The memory detection method of claim 8, wherein, The specific steps of repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature decrease of the memory under test include: The steps of refreshing the memory under test and recording the state of the fuse are performed every second predetermined temperature interval during the temperature decrease of the memory under test.

13. The memory detection method of claim 8, wherein, The specific steps of determining whether the read data of the memory under test is accurate include: The steps of determining whether the data in the memory array read at the first sub-pre-set temperature and the data in the memory array read at the second sub-pre-set temperature are both accurate, and if not, determining that the fuse has a defect.

14. The memory detection method of claim 8, wherein, The temperature decrease rate of the memory under test is less than the temperature increase rate of the memory under test.

15. The memory detection method of claim 1, wherein, The memory is a DRAM memory, and the fuse is an electrically programmable fuse.

16. A memory detection apparatus, comprising: It comprises: a write circuit for writing data to a memory under test, the memory under test comprising a failed memory cell, a fuse, and a redundant cell replacing the failed memory cell through the fuse; a temperature adjuster for adjusting the temperature of the memory under test; a processor for repeatedly refreshing the memory under test and repeatedly recording the state of the fuse during the temperature change of the memory under test; a read circuit for determining whether the temperature of the memory under test is stable at a pre-set temperature, and if so, reading the data of the memory under test; a controller for determining whether the read data of the memory under test is accurate, and if not, determining that the fuse has a defect; The memory under test comprises a plurality of memory cells, and the plurality of memory cells are arranged into a memory array, the memory array comprising at least one failed memory cell replaced by the redundant cell through the fuse. The write circuit is used to write data to the memory under test until the memory array is full.

17. The memory detection device of claim 16, wherein, The temperature adjuster is used to continuously increase the temperature of the memory under test.

18. The memory detection device of claim 17, wherein, The processor is used to repeatedly perform the following steps during the temperature increase of the memory under test: refreshing the memory array; recording the state of the fuse.

19. The memory detection device of claim 17, wherein, The processor is used to perform the steps of refreshing the memory under test and recording the state of the fuse every first predetermined time interval during the temperature increase of the memory under test.

20. The memory detection device of claim 17, wherein, The processor is used to perform the steps of refreshing the memory under test and recording the state of the fuse every first predetermined temperature interval during the temperature increase of the memory under test.

21. The memory detection device of claim 17, wherein, The read circuit is used to determine whether the temperature of the memory under test is stable at a first sub-pre-set temperature, and if so, read the data in the memory array.

22. The memory detection device of claim 21, wherein, The temperature adjuster is further configured to continuously decrease the temperature of the memory under test after determining that the temperature of the memory under test is stabilized at a first sub-predefined temperature and reading data in the memory array; The processor is further configured to repeatedly refresh the memory under test and repeatedly record the state of the fuse during the temperature decreasing of the memory under test. The reading circuit is further configured to determine whether the temperature of the memory under test is stabilized at a second sub-predefined temperature, and if so, read data in the memory array, the second sub-predefined temperature being lower than the first sub-predefined temperature.

23. The memory detection device of claim 22, wherein, The processor is further configured to perform the steps of refreshing the memory under test and recording the state of the fuse every second predetermined time interval during the temperature decreasing of the memory under test.

24. The memory detection device of claim 22, wherein, The processor is further configured to perform the steps of refreshing the memory under test and recording the state of the fuse every second predetermined temperature interval during the temperature decreasing of the memory under test.

25. The memory detection device of claim 22, wherein, The controller is configured to determine whether the data in the memory array read at the first sub-predefined temperature and the data in the memory array read at the second sub-predefined temperature are both accurate, and if not, determine that the fuse has a defect.

26. The memory detection device of claim 16, wherein, The memory is a DRAM memory, and the fuse is an electrically programmable fuse.

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