Semiconductor structure and method for forming the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure comprises the following steps: providing a substrate; etching the substrate to form a plurality of active areas and a plurality of grooves, wherein the grooves include a first groove and a second groove that are interconnected, wherein the active area extends along a first direction, wherein the first groove is located between two adjacent active areas arranged in parallel along the first direction, and the second groove is located below the first groove and below a portion of the active area, and the inner diameter of the second groove is larger than the inner diameter of the first groove; and filling the grooves to form a filling layer having an air gap, wherein the air gap is located at least within the second groove. The present invention blocks the migration of electrons between adjacent active areas, reduces the impact of the hammering effect, and improves the yield and performance reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] In semiconductor structures such as DRAM, each active area overlaps with two word lines (i.e., two word lines pass through the same active area). When one word line is activated and repeatedly refreshed, two effects occur: on the one hand, it generates noise or interference on the other word line passing through the same active area; on the other hand, if the refresh frequency of the activated word line is too high before the active area adjacent to the activated word line is activated or refreshed, the active area adjacent to the activated word line becomes fragile, resulting in charge loss or leakage. Both of these effects can cause data errors in one or more active areas adjacent to the activated word line, resulting in the so-called row hammer effect.

[0004] Therefore, how to alleviate the hammering effect, reduce the mutual interference between adjacent active areas, and improve the yield and performance reliability of semiconductor structures is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a semiconductor structure and a method for forming the same, which are used to solve the problem that the semiconductor structure in the prior art is prone to a hammering effect, thereby reducing mutual interference between adjacent active regions and improving the yield and performance reliability of the semiconductor structure.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0007] providing a substrate;

[0008] Etching the substrate to form a plurality of active areas and a plurality of grooves, wherein the grooves include a first groove and a second groove that are interconnected, the active areas extending along a first direction, the first groove being located between two adjacent active areas arranged parallel to each other along the first direction, and the second groove being located below the first groove and below a portion of the active areas, and the inner diameter of the second groove being larger than the inner diameter of the first groove;

[0009] The groove is filled to form a filling layer having an air gap, wherein the air gap is at least located in the second groove.

[0010] Optionally, the specific steps of forming the multiple active areas and the multiple recesses include:

[0011] forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate;

[0012] Etching the substrate along the opening to form an initial active area extending along the first direction;

[0013] Etching the initial active area to form the first groove and a plurality of active areas extending along the first direction and arranged in parallel along the first direction;

[0014] The substrate is continuously etched along the first groove to form a second groove located below the first groove and below a portion of the active area, wherein the inner diameter of the second groove is larger than the inner diameter of the first groove.

[0015] Optionally, the plurality of initial active regions are arranged in parallel along a second direction, with gaps between adjacent initial active regions, and the second direction intersects the first direction; before etching the initial active regions, the method further includes the following steps:

[0016] A dielectric material is deposited on the substrate to form a dielectric layer that fills the gap.

[0017] Optionally, the specific steps of forming the first groove include:

[0018] The initial active area is etched to form a first groove penetrating the initial active area, wherein the first groove separates the initial active area into a plurality of active areas extending along the first direction and arranged in parallel along the first direction.

[0019] Optionally, a bottom surface of the first groove is flush with a bottom surface of the initial active area.

[0020] Optionally, the specific step of forming the second groove located below the first groove and below a portion of the active area includes:

[0021] forming a protective layer covering the sidewalls of the first groove;

[0022] Continue etching the substrate along the first groove to form an initial second groove located below the first groove;

[0023] The inner diameter of the initial second groove is enlarged to form the second groove having an inner diameter larger than that of the first groove.

[0024] Optionally, the specific step of enlarging the inner diameter of the initial second groove includes:

[0025] The initial second groove is etched using a wet etching process.

[0026] Optionally, the height of the initial second groove is 1 / 5 to 1 / 4 of the height of the active area.

[0027] Optionally, the specific steps of forming the filling layer with air gaps include:

[0028] removing the protective layer and the dielectric layer;

[0029] An insulating material is deposited in the groove to form a filling layer with an air gap in the second groove.

[0030] In order to solve the above problems, the present invention further provides a semiconductor structure, comprising:

[0031] substrate;

[0032] a groove located in the substrate, comprising a first groove communicating with each other and a second groove located below the first groove, wherein the inner diameter of the second groove is greater than the inner diameter of the first groove;

[0033] An active area extends along a first direction, the first groove is located between two adjacent active areas arranged in parallel along the first direction, and the second groove is also located below a portion of the active area;

[0034] A filling layer is filled in the groove, and the filling layer has an air gap at least located in the second groove.

[0035] Optionally, a bottom surface of the first groove is flush with a bottom surface of the active area.

[0036] Optionally, the height of the second groove is 1 / 5 to 1 / 4 of the height of the active area.

[0037] Optionally, the second groove is located below two adjacent active areas that are arranged in parallel along the first direction.

[0038] Optionally, a plurality of the active areas are arranged along the first direction and a second direction to form an active area array, and the second direction intersects with the first direction;

[0039] The filling layer further fills the gap between two adjacent active areas arranged along the second direction.

[0040] Optionally, the air gap is located only in the second groove; or,

[0041] The air gap extends from the second groove to the first groove.

[0042] The semiconductor structure and formation method provided by the present invention form grooves between adjacent active areas, and the grooves include a first groove that is interconnected and a second groove located below the first groove, and the second groove is also located below part of the active area, and the inner diameter of the second groove is larger than the inner diameter of the first groove. A filling layer with an air gap is formed at least in the second groove by a deposition process, and the characteristic of air having a lower dielectric constant is utilized to isolate the adjacent active areas, thereby blocking the migration of electrons between adjacent active areas, reducing the interference between adjacent active areas during the operation of the semiconductor structure, alleviating the impact of the hammering effect, and improving the yield and performance reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Attachment Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;

[0044] Attachment Figures 2A-2N It is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention;

[0045] Attachment Figures 3A-3B Schematic diagram of a semiconductor structure in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0046] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present invention are described in detail below with reference to the accompanying drawings.

[0047] This embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention, Figures 2A-2N This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 、 Figure 2A-Figure 2N As shown, the method for forming a semiconductor structure provided in this embodiment includes the following steps:

[0048] Step S11, providing a substrate 20, such as Figure 2A shown.

[0049] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This embodiment is described using a silicon substrate as an example. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.

[0050] Step S12: etching the substrate 20 to form a plurality of active areas 25 and a plurality of grooves, wherein the grooves include a first groove 26 and a second groove 30 that are interconnected. The active areas 25 extend along a first direction D1. The first groove 26 is located between two adjacent active areas 25 arranged in parallel along the first direction D1. The second groove 30 is located below the first groove 26 and below a portion of the active areas 25. The inner diameter R2 of the second groove 30 is larger than the inner diameter R1 of the first groove 26. Figure 2L shown.

[0051] Optionally, the specific steps of forming the multiple active areas 25 and the multiple recesses include:

[0052] A mask layer 21 covering the substrate 20 is formed, and the mask layer 21 has an opening 211 exposing the substrate 20, as shown in FIG. Figure 2A As shown;

[0053] The substrate 20 is etched along the opening 211 to form an initial active region 22 extending along the first direction D1. Figure 2B As shown;

[0054] The initial active area 22 is etched to form the first groove 26 and a plurality of active areas 25 extending along the first direction D1 and arranged in parallel along the first direction D1, as shown in FIG. Figure 2E and Figure 2F As shown, Figure 2F yes Figure 2E Schematic diagram of the top view structure;

[0055] The substrate 20 is further etched along the first groove 26 to form a second groove 30 located below the first groove 26 and part of the active area 25, and the inner diameter R2 of the second groove 30 is larger than the inner diameter R1 of the first groove 26. Figure 2L shown.

[0056] Specifically, chemical vapor deposition, physical vapor deposition or atomic layer deposition can be used to deposit polysilicon or other materials on the surface of the substrate 20 to form the mask layer 21, and by patterning the mask layer 21, a plurality of openings 211 exposing the substrate 20 are formed in the mask layer 21. Then, a dry etching process is used to etch the substrate 20 downward along the opening 211 to a preset depth to form a gap 221. An initial active area 22 is formed between two adjacent gaps 221. The plurality of gaps 221 separate the substrate 20 into a plurality of initial active areas 22. The plurality of initial active areas 22 and the plurality of gaps 221 all extend along the first direction D1, and the plurality of active areas are arranged in parallel along a second direction D2 intersecting with the first direction D1, as shown in FIG. Figure 2B The first direction D1 and the second direction D2 are both parallel to the surface of the substrate 20. During the dry etching process for etching the substrate 20, one of SF6, CF4, Cl2, CHF3, O2, and Ar, or a mixture of two or more gases can be used as etching gas.

[0057] Optionally, the plurality of initial active regions 22 are arranged in parallel along a second direction D2, with gaps 221 between adjacent initial active regions 22, and the second direction D2 intersects the first direction D1; before etching the initial active regions 22, the following steps are further included:

[0058] A dielectric material is deposited on the substrate 20 to form a dielectric layer 23 that fills the gap 221. Figure 2C shown.

[0059] Specifically, a low pressure chemical vapor deposition process (LPCVD) or an atomic layer deposition process can be used to deposit silicon nitride or other materials on the substrate 20 using SiH4 or SiH2Cl2 as a reaction gas to form the dielectric layer 23. When the dielectric layer 23 is formed using the atomic layer deposition process, the reaction gas can also include NH3 or a mixed gas including N2 and H2. By a planarization process such as chemical mechanical polishing, the top surface of the dielectric layer 23 is made flush with the top surface of the mask layer 21, as shown in FIG. Figure 2C In this embodiment, the term "plurality" refers to two or more.

[0060] Optionally, the specific steps of forming the first groove 26 include:

[0061] The initial active area 22 is etched to form a first groove 26 penetrating the initial active area 22. The first groove 26 divides the initial active area 22 into a plurality of active areas 25 extending along the first direction D1 and arranged in parallel along the first direction D1. Figure 2E and Figure 2F shown.

[0062] Specifically, a photoresist layer is formed on the dielectric layer 23 and the mask layer 21, and an etching window 24 is provided in the photoresist layer. Figure 2D The mask layer 21 and the initial active region 22 are etched downward along the etching window 24 to form a direction perpendicular to the surface of the substrate 20 (eg Figure 2E The first grooves 26 extend along the third direction D3 (in the first direction D1) through the initial active area 22. Multiple first grooves 26 arranged along the first direction D1 divide the initial active area 22 into multiple active areas 25 arranged parallel to the first direction D1. On the one hand, the dielectric layer 23 prevents collapse during etching of the initial active area 22, ensuring smooth semiconductor manufacturing. On the other hand, through selective etching, the dielectric layer 23 also ensures the stability of the characteristic dimensions of the first grooves 26, preventing them from tilting. This step etches only the initial active area 22 and does not etch the dielectric layer 23.

[0063] Optionally, the bottom surface of the first groove 26 is flush with the bottom surface of the initial active area 22 .

[0064] Those skilled in the art may also, according to actual needs, make the first groove 26 penetrate deep into the substrate 20 so that the bottom surface of the first groove 26 is located below the bottom surface of the initial active area 22, that is, the depth of the first groove 26 is greater than the depth of the initial active area 22, to ensure that the initial active area 22 is fully cut off.

[0065] Optionally, the specific steps of forming the second groove 30 located below the first groove 26 and below a portion of the active area 25 include:

[0066] A protective layer 27 is formed to cover the sidewalls of the first groove 26. Figure 2G As shown;

[0067] The substrate 20 is further etched along the first groove 26 to form an initial second groove 28 below the first groove 26. Figure 2H and Figure 2I As shown, Figure 2I yes Figure 2H Schematic diagram of the cross section along the AB direction;

[0068] The inner diameter of the initial second groove 28 is enlarged to form the second groove 30 having an inner diameter larger than that of the first groove 26. Figure 2J shown.

[0069] Optionally, the specific steps of enlarging the inner diameter of the initial second groove 28 include:

[0070] The initial second groove 28 is etched using a wet etching process.

[0071] Optionally, the height of the initial second groove 28 is 1 / 5 to 1 / 4 of the height of the active area 25 .

[0072] The material of the protective layer 27 can be, but is not limited to, a nitride material, such as silicon nitride, as long as a high etching selectivity between the protective layer 27 and the substrate 20 is ensured, for example, the etching selectivity between the protective layer 27 and the substrate 20 is greater than 3. For example, the surface of the mask layer 21 and the sidewalls of the first groove 26 (i.e., the surface of the active area 25) are subjected to plasma nitridation treatment to form the protective layer 27 covering the surface of the mask layer 21 and the sidewalls of the first groove 26. The reaction gas used in the plasma nitridation treatment can be NH3, the reaction temperature can be 600°C to 800°C, the RF power can be 600W to 2000W, and the reaction pressure can be 1Pa to 10Pa. The formation of the protective layer 27 can prevent subsequent processes from affecting the characteristic dimensions of the first groove 26 and avoid damage to the active area 25.

[0073] After forming the protective layer 27, the substrate 20 is further etched downward along the first groove 26 using a dry etching process to form the initial second groove 28 below the first groove 26 and connected to the first groove. Thereafter, the initial second groove 28 is cleaned using a wet etching process to increase the lateral dimension of the initial second groove 28 (i.e., the inner diameter of the initial second groove 28), thereby forming the second groove 30 extending toward the active area 25. Figure 2J As shown. Since the inner diameter R2 of the second groove 30 is larger than the inner diameter R1 of the first groove 26, the cross section of the groove formed by the first groove 26 and the second groove 30 is convex as a whole. Afterwards, the dielectric layer 23 and the protective layer 27 are removed to obtain the following Figure 2K In order to simplify the process steps, the material of the dielectric layer 23 can be set to be the same as the material of the protective layer 27, so that the dielectric layer 23 and the protective layer 27 can be removed simultaneously. Then, the mask layer 21 is removed to obtain the structure shown in FIG. Figure 2L The structure shown.

[0074] By adjusting parameters during the wet etching process, the size of the initial second groove 28 can be expanded only along the first direction D1, so that the inner diameter of the formed second groove 30 in only the first direction D1 is larger than the inner diameter of the first groove 26 in the first direction D1. Alternatively, the size of the initial second groove 28 can be expanded along both the first direction D1 and the second direction D2, so that the inner diameter of the formed second groove 30 in the first direction D1 is larger than the inner diameter of the first groove 26 in the first direction D1, and the inner diameter of the second groove 30 in the second direction D2 is also larger than the inner diameter of the first groove 26 in the second direction D2. When the size of the initial second groove 28 is expanded along both the first direction D1 and the second direction D2, the inner diameter of the second groove 30 in the second direction D2 should be smaller than the width of the gap 221 in the second direction D2.

[0075] Step S13, filling the groove to form a filling layer 31 with an air gap 32, wherein the air gap 32 is at least located in the second groove 30. Figure 2M and Figure 2N As shown, Figure 2M yes Figure 2N Schematic cross-section along the CD direction.

[0076] Optionally, the specific steps of forming the filling layer 31 having the air gap 32 include:

[0077] removing the protective layer 27 and the dielectric layer 23;

[0078] An insulating material is deposited in the groove to form a filling layer 31 with an air gap 32 in the second groove 30 .

[0079] Specifically, after removing the protective layer 27 and the dielectric layer 23, the grooves can be filled using an atomic layer deposition process. Taking advantage of the conformal deposition characteristics of the atomic layer deposition process, when the grooves are filled using the atomic layer deposition process, since the inner diameter R1 of the first groove 26 located above is smaller than the inner diameter R2 of the second groove 30 located below, the top of the first groove 26 is directly sealed during the deposition process, thereby forming the filling layer 31 having the air gap 32 within the groove. The air gap 32 exists at least within the second groove 30, that is, at least below two adjacent active regions 25 arranged parallel to each other along the first direction D1. By forming the air gap 32 below two adjacent active regions 25 arranged parallel to each other along the first direction D1, electron migration between adjacent active regions 25 arranged parallel to each other along the first direction D1 can be effectively avoided, thereby reducing the row hammering effect. The material of the filling layer 31 can be, but is not limited to, an oxide material, such as silicon dioxide. When the material of the filling layer 31 is silicon dioxide, the reaction gas may be LTO520 (aminosilane gas) / O2 or N zero / O2.

[0080] In addition, this embodiment also provides a semiconductor structure. Figures 3A-3B The semiconductor structure provided in this embodiment can be used as follows: Figure 1 、 Figure 2A-Figure 2N The semiconductor structure is formed by the method shown in FIG. Figure 2A-Figure 2N and Figure 3A-3B As shown, the semiconductor structure includes:

[0081] substrate 20;

[0082] A groove located in the substrate 20, including a first groove 26 connected to each other and a second groove 30 located below the first groove 26, wherein the inner diameter R2 of the second groove 30 is larger than the inner diameter R1 of the first groove 26;

[0083] The active area 25 extends along the first direction D1. The first groove 26 is located between two adjacent active areas 25 arranged in parallel along the first direction D1. The second groove 30 is also located below a portion of the active area 25.

[0084] The filling layer 31 is filled in the groove, and the filling layer 31 has an air gap 32 at least located in the second groove 30 .

[0085] Optionally, the bottom surface of the first groove 26 is flush with the bottom surface of the active area 25 .

[0086] Optionally, the height of the second groove 30 is 1 / 5 to 1 / 4 of the height of the active area 25 .

[0087] Optionally, the second groove 30 is located below two adjacent active regions 25 that are arranged in parallel along the first direction D1.

[0088] Optionally, the plurality of active regions 25 are arranged along the first direction D1 and the second direction D2 to form an active region array, and the second direction D2 intersects with the first direction D1;

[0089] The filling layer 31 also fills the gap 221 between two adjacent active regions 25 arranged along the second direction D2.

[0090] Optionally, the air gap 32 is located only in the second groove 30; or,

[0091] The air gap 32 extends from the second groove 30 to the first groove 26 .

[0092] The semiconductor structure and formation method provided in this specific embodiment form grooves between adjacent active areas, and the grooves include a first groove that is interconnected and a second groove located below the first groove, and the second groove is also located below part of the active area. The inner diameter of the second groove is larger than the inner diameter of the first groove. A filling layer with an air gap is formed at least in the second groove by a deposition process. The characteristic of air having a lower dielectric constant is utilized to isolate the adjacent active areas, thereby blocking the migration of electrons between adjacent active areas, reducing the interference between adjacent active areas during the operation of the semiconductor structure, alleviating the impact of the hammering effect, and improving the yield and performance reliability of the semiconductor structure.

[0093] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: providing a substrate; Etching the substrate to form a plurality of active areas and a plurality of grooves, wherein the grooves include a first groove and a second groove that are interconnected, the active areas extending along a first direction, the first groove being located between two adjacent active areas arranged parallel to each other along the first direction, and the second groove being located below the first groove and below a portion of the active areas, and the inner diameter of the second groove being larger than the inner diameter of the first groove; The groove is filled to form a filling layer having an air gap, wherein the air gap is at least located in the second groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming multiple active areas and multiple recesses include: forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate; Etching the substrate along the opening to form an initial active area extending along the first direction; Etching the initial active area to form the first groove and a plurality of active areas extending along the first direction and arranged in parallel along the first direction; The substrate is continuously etched along the first groove to form a second groove located below the first groove and below a portion of the active area, wherein the inner diameter of the second groove is larger than the inner diameter of the first groove.

3. The method for forming a semiconductor structure according to claim 2, wherein: The plurality of initial active regions are arranged in parallel along a second direction, with gaps between adjacent initial active regions, and the second direction intersects the first direction; before etching the initial active regions, the method further includes the following steps: A dielectric material is deposited on the substrate to form a dielectric layer that fills the gap.

4. The method for forming a semiconductor structure according to claim 3, wherein: The specific steps of forming the first groove include: The initial active area is etched to form a first groove penetrating the initial active area, wherein the first groove separates the initial active area into a plurality of active areas extending along the first direction and arranged in parallel along the first direction.

5. The method for forming a semiconductor structure according to claim 4, wherein: A bottom surface of the first groove is flush with a bottom surface of the initial active region.

6. The method for forming a semiconductor structure according to claim 3, wherein: The specific steps of forming the second groove located below the first groove and below a portion of the active area include: forming a protective layer covering the sidewalls of the first groove; Continue etching the substrate along the first groove to form an initial second groove located below the first groove; The inner diameter of the initial second groove is enlarged to form the second groove having an inner diameter larger than that of the first groove.

7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of enlarging the inner diameter of the initial second groove include: The initial second groove is etched using a wet etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The height of the initial second groove is 1 / 5 to 1 / 4 of the height of the active area.

9. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming the filling layer with air gaps include: removing the protective layer and the dielectric layer; An insulating material is deposited in the groove to form a filling layer with an air gap in the second groove.

10. A semiconductor structure, characterized in that include: substrate; a groove located in the substrate, comprising a first groove communicating with each other and a second groove located below the first groove, wherein the inner diameter of the second groove is greater than the inner diameter of the first groove; An active area extends along a first direction, the first groove is located between two adjacent active areas arranged in parallel along the first direction, and the second groove is also located below a portion of the active area; A filling layer is filled in the groove, and the filling layer has an air gap at least located in the second groove.

11. The semiconductor structure according to claim 10, wherein: A bottom surface of the first groove is flush with a bottom surface of the active area.

12. The semiconductor structure according to claim 10, wherein: The height of the second groove is 1 / 5 to 1 / 4 of the height of the active area.

13. The semiconductor structure according to claim 10, wherein: The second groove is located below two adjacent active regions that are arranged in parallel along the first direction.

14. The semiconductor structure according to claim 13, wherein: The plurality of active regions are arranged along the first direction and a second direction to form an active region array, wherein the second direction intersects the first direction; The filling layer further fills the gap between two adjacent active areas arranged along the second direction.

15. The semiconductor structure according to claim 10, wherein: The air gap is located only in the second groove; or, The air gap extends from the second groove to the first groove.

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