Semiconductor Structure, Memory, and Crack Testing Method

Abstract

Embodiments of the present disclosure provide a semiconductor structure, a memory, and a crack testing method. The semiconductor structure includes: a through-silicon via that penetrates a substrate; a protection structure including a conductive first test ring and a conductive second test ring, both of which are disposed around the through-silicon via and are electrically insulated from the through-silicon via; a first dielectric layer located between the first test ring and the second test ring for electrically isolating the first test ring and the second test ring; and a first connection layer located within the first dielectric layer for electrically connecting the first test ring and the second test ring.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a memory, and a crack testing method. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits has been continuously reduced, and the device interconnection density has been continuously increased. The traditional two-dimensional packaging can no longer meet the industry's needs. Therefore, the vertical interconnection stacked packaging method based on the Through Silicon Via (TSV) technology, with its key technical advantages of short-distance interconnection and high-density integration, has gradually led the trend of the development of packaging technology.

[0003] Since the through-silicon via penetrates the entire wafer, the through-silicon via will affect the structures disposed on the wafer and near the through-silicon via, and may reduce the performance of the formed devices. Moreover, currently, there is no effective way to test the influence of the through-silicon via on the nearby structures. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a memory, and a crack testing method.

[0005] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, including:

[0006] A through-silicon via penetrating a substrate;

[0007] A protection structure, including:

[0008] A conductive first test ring and a conductive second test ring, both disposed around the through-silicon via and electrically insulated from the through-silicon via;

[0009] A first dielectric layer located between the first test ring and the second test ring for electrically isolating the first test ring and the second test ring;

[0010] A first connection layer located within the first dielectric layer for electrically connecting the first test ring and the second test ring.

[0011] In some embodiments, the protection structure further includes:

[0012] A conductive third test ring vertically penetrating the substrate, disposed around the through-silicon via, and located between the second test ring and the through-silicon via, and an end portion of the third test ring includes a third contact;

[0013] A second connection layer, located between the second test ring and the third test ring, electrically connects the second test ring and the third test ring; wherein, in a direction perpendicular to the substrate, the second connection layer is located between the third contact and the first connection layer.

[0014] In some embodiments, the protection structure includes N third test rings and N second connection layers; wherein, the first to the (N - 1)th third test rings are located between the second test ring and the Nth third test ring, and N is a positive integer greater than 1;

[0015] The first second connection layer electrically connects the second test ring and the first third test ring;

[0016] The Kth second connection layer electrically connects the Kth third test ring and the (K + 1)th third test ring; wherein, K is a positive integer less than N.

[0017] In some embodiments, the first connection layer electrically connects the first test ring, the second test ring, and the third test ring.

[0018] In some embodiments, in a direction parallel to the plane of the substrate,

[0019] The cross-sectional shape of the first test ring includes: a regular polygon or an annular shape;

[0020] The cross-sectional shape of the second test ring includes: a regular polygon or an annular shape; wherein, the symmetry center of the cross-sectional shape of the first test ring coincides with the symmetry center of the cross-sectional shape of the second test ring;

[0021] The cross-sectional center of the through-silicon via covers the symmetry center of the cross-sectional shape of the first test ring.

[0022] According to a second aspect of the embodiments of the present disclosure, there is provided a memory, including:

[0023] A semiconductor structure as described in any one of the first aspects of the embodiments of the present disclosure; wherein, the substrate includes a substrate and an insulating layer covering the substrate;

[0024] Memory elements are disposed in the insulating layer.

[0025] In some embodiments, the memory further includes:

[0026] A conductive interconnect structure electrically connected to the memory elements;

[0027] wherein, the interconnect structure and the protection structure are formed simultaneously.

[0028] In some embodiments, the memory further includes:

[0029] A transistor located on the surface of the substrate;

[0030] One end of the protection structure is electrically connected to the gate of the transistor, and the other end of the protection structure is configured to receive an external electrical signal.

[0031] In some embodiments, the other end of the protection structure is grounded.

[0032] In some embodiments, the substrate includes:

[0033] A scribe line located between two adjacent memory chip regions;

[0034] A plurality of the semiconductor structures are arranged at equal intervals within the scribe line.

[0035] According to a third aspect of the embodiments of the present disclosure, there is provided a crack testing method, which is applied to test a semiconductor structure as described in any one of the first aspects of the embodiments of the present disclosure. The crack testing method includes:

[0036] Providing the semiconductor structure;

[0037] Providing a first electrical signal to a first contact at an end of the first test ring and a second contact at an end of the second test ring, and determining a first electrical parameter of a first path in the protection structure that is electrically connected to the first contact and the second contact;

[0038] When the first electrical parameter indicates that the first path is conductive, it is determined that the through-silicon via has no crack;

[0039] When the first electrical parameter indicates that the first path is not conductive, it is determined that the through-silicon via has a crack.

[0040] In some embodiments, the protection structure further includes a conductive third test ring and a second connection layer, and the second connection layer electrically connects the second test ring and the third test ring;

[0041] The crack testing method further includes:

[0042] Providing a second electrical signal to the second contact and a third contact at an end of the third test ring, and determining a second electrical parameter of a second path in the protection structure that is electrically connected to the second contact and the third contact;

[0043] When the first electrical parameter indicates that the first path is conductive and the second electrical parameter indicates that the second path is conductive, it is determined that the through-silicon via has no crack;

[0044] When the first electrical parameter indicates that the first path is not conducting, it is determined that the through-silicon via has a crack in a first region relatively close to the first connection layer;

[0045] When the second electrical parameter indicates that the second path is not conducting, it is determined that the through-silicon via has a crack in a second region relatively close to the second connection layer.

[0046] In some embodiments, the protection structure further includes a conductive third test ring and a second connection layer, and the first connection layer is electrically connected to the first test ring, the second test ring, and the third test ring;

[0047] The crack testing method further includes:

[0048] Providing a second electrical signal to a second contact and a third contact at an end of the third test ring, and determining a second electrical parameter of a second path in the protection structure that is electrically connected to the second contact and the third contact;

[0049] When the first electrical parameter indicates that the first path is conducting and the second electrical parameter indicates that the second path is conducting, it is determined that the through-silicon via has no crack;

[0050] When the first electrical parameter indicates that the first path is not conducting and the second electrical parameter indicates that the second path is conducting, it is determined that the through-silicon via has a crack in a region close to the first connection layer between the first test ring and the second test ring;

[0051] When the first electrical parameter indicates that the first path is conducting and the second electrical parameter indicates that the second path is not conducting, it is determined that the through-silicon via has a crack in a region close to the first connection layer between the first test ring and the second test ring.

[0052] In some embodiments, the first electrical parameter and the second electrical parameter include at least one of the following: resistance; current; voltage difference.

[0053] The semiconductor structure provided by the embodiments of the present disclosure, by providing a protection structure around the through-silicon via, the protection structure can play a role in stress release for a local part of the through-silicon via. Moreover, the protection structure can also play a role in isolating stress. Specifically, the protection structure can isolate the stress transfer between the through-silicon via and the structures outside the protection structure, reduce the stress interaction between the through-silicon via and the surrounding structures, and play a certain protective role for the through-silicon via and the surrounding structures, which is beneficial to ensuring better quality of the formed device.

[0054] In addition, since the conductive first test ring and the second test ring in the protection structure are both electrically insulated from the through-silicon via, and the first connection layer in the first dielectric layer electrically connects the first test ring and the second test ring, the first electrical parameter of the first path electrically connected to the first contact and the second contact in the protection structure can be determined by providing a first electrical signal to the first contact at the end of the first test ring and the second contact at the end of the second test ring, and whether there is a crack in the through-silicon via can be determined according to the first electrical parameter, and the measurement method is simple and fast.

[0055] Furthermore, since the protection structure includes the conductive first test ring and the second test ring, when the first test ring and the second test ring are grounded, the first test ring and the second test ring can also perform electromagnetic shielding on the through-silicon via. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In the drawings (which are not necessarily drawn to scale), like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0057] Figure 1a is a top view of a semiconductor structure shown according to an exemplary embodiment;

[0058] Figure 1b is a partial cross-sectional schematic view of a semiconductor structure shown according to an exemplary embodiment;

[0059] Figure 2a is a top view of another semiconductor structure shown according to an exemplary embodiment;

[0060] Figure 2b is a partial cross-sectional schematic view of another semiconductor structure shown according to an exemplary embodiment;

[0061] Figure 3 is a schematic diagram of a memory shown according to an exemplary embodiment;

[0062] Figure 4 is a flowchart of a crack testing method shown according to an exemplary embodiment;

[0063] Figure 5 is a schematic diagram of a crack testing method shown according to an exemplary embodiment;

[0064] Figure 6a and Figure 6b is a schematic diagram of another crack testing method shown according to an exemplary embodiment;

[0065] Figure 7a and Figure 7bIt is a schematic diagram of yet another crack testing method shown according to an exemplary embodiment;

[0066] Figure 8 It is a schematic diagram of yet another crack testing method shown according to an exemplary embodiment. Detailed implementation manners

[0067] The technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0068] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present disclosure.

[0069] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intervening features or layers therebetween" (i.e., directly on something), but also includes the meaning of "on" something "with intervening features or layers therebetween".

[0070] In the embodiments of the present disclosure, the term "A is connected to B" includes the case where A and B are connected to each other in contact, or the case where A is non-contactedly connected to B with other components interposed between A and B.

[0071] In the embodiments of the present disclosure, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0072] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a range smaller than the range of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0073] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0074] In the related art, in order to achieve three-dimensional stacking of chips, through-silicon vias penetrating the substrate can be provided to realize electrical connection between two upper and lower chips. Generally, the through-silicon vias are filled with conductive metal, for example, copper or tungsten, etc. However, the stress and electric field generated by the through-silicon vias will have an adverse impact on the performance of the devices disposed near the through-silicon vias, especially when the size of the through-silicon vias is large.

[0075] For example, taking the case where the through-silicon vias are filled with copper, when the temperature of the silicon substrate changes, due to the mismatch of the thermal expansion coefficients of the silicon substrate and copper, it is easy for the through-silicon vias to generate tensile stress or compressive stress on the surrounding silicon substrate. The magnitude of the tensile stress or compressive stress is inversely proportional to the distance from the through-silicon vias. The tensile stress or compressive stress will cause the lattice constant of at least part of the structure (for example, the MOS transistor channel region) of the devices disposed around the through-silicon vias to change, thereby changing the carrier mobility and having an adverse impact on the electrical performance of the devices.

[0076] Moreover, when cracks occur in the insulating material around the through-silicon vias due to the stress, the conductive material included in the through-silicon vias may diffuse through the cracks, and even the situation where the through-silicon vias diffuse through the cracks to be electrically connected to the surrounding devices may occur, resulting in a short circuit of the memory and reducing the quality and reliability of the memory.

[0077] In view of this, an embodiment of the present disclosure provides a semiconductor structure 100. Referring to Figure 1a and Figure 1b as shown, the semiconductor structure 100 includes:

[0078] A through-silicon via 110 penetrating the substrate 120;

[0079] A protection structure 130, including:

[0080] A conductive first test ring 131 and a conductive second test ring 132, both disposed around the through-silicon via 110 and electrically insulated from the through-silicon via 110;

[0081] A first dielectric layer 133 located between the first test ring 131 and the second test ring 132 for electrically isolating the first test ring 131 and the second test ring 132;

[0082] A first connection layer 134 located in the first dielectric layer 133 for electrically connecting the first test ring 131 and the second test ring 132.

[0083] Exemplarily, the through-silicon via 110 can penetrate the substrate 120 along the first direction. Referring toFigure 1b As shown, the first direction may include a direction parallel to the Z-axis. The constituent material of the through-silicon via 110 may include a conductive material, such as copper or tungsten, etc.

[0084] In some embodiments, the constituent material of the through-silicon via 110 further includes a barrier layer disposed between the conductive material and the substrate 120 for blocking the diffusion of the conductive material into the substrate 120. The constituent material of the barrier layer may include metal nitrides, such as titanium nitride and / or tantalum nitride. The constituent material of the barrier layer may also include oxides, such as silicon oxide and / or silicon oxynitride.

[0085] The constituent material of the substrate 120 may include: a semiconductor substrate, and the constituent material of the semiconductor substrate may include: silicon, silicon-on-insulator (SOI), or stacked silicon-on-insulator (SSOI), etc. As Figure 1b shown, an active area (AA) may be defined on the semiconductor substrate.

[0086] The constituent material of the substrate 120 may also include: a dielectric material, such as silicon dioxide or tetraethyl orthosilicate (TEOS), etc.

[0087] The constituent material of the first test ring 131 may be the same as that of the second test ring 132. For example, the constituent material of the first test ring 131 and the second test ring 132 may include: copper or tungsten.

[0088] Referring to Figure 1b shown, the end of the first test ring 131 may include: a first contact 1311 for receiving an electrical signal applied to the first test ring 131. The end of the second test ring 132 may include: a second contact 1321 for receiving an electrical signal applied to the second test ring 132.

[0089] Referring to Figure 1a shown, the second test ring 132 may be disposed between the first test ring 131 and the through-silicon via 110. It should be emphasized that there is a certain gap between the second test ring 132 and the through-silicon via 110, and the gap is filled with a dielectric material to electrically isolate the second test ring 132 from the through-silicon via 110.

[0090] Combining Figure 1a and Figure 1b shown, in the semiconductor structure 100, when cracks occur between the through-silicon via 110 and the protection structure 130 due to stress or other reasons, the cracks may extend along the first direction, the second direction, or the third direction. The second direction may include a direction parallel to the X-axis, and the third direction may include a direction parallel to the Y-axis.

[0091] When the crack extends along the second direction or the third direction to the second test ring 132, since the constituent material of the second test ring 132 is different from that of the substrate 120, the second test ring 132 can block the further extension of the crack along the second direction or the third direction. Thus, the protection structure 130 can control the crack near the through-silicon via 110 within the area between the protection structure 130 and the through-silicon via 110, reducing the probability of the crack further extending to the outside of the protection structure 130 away from the through-silicon via 110. That is, for the devices located outside the protection structure 130 away from the through-silicon via 110, the protection structure 130 plays a role in stress protection.

[0092] Similarly, the protection structure 130 can also block the crack generated from the outside away from the through-silicon via 110 from extending to the through-silicon via 110. That is, the protection structure 130 also plays a role in stress protection for the through-silicon via 110.

[0093] It should be emphasized that in the plane perpendicular to the first direction, the cross-sectional shape of the protection structure 130 is a closed figure (for example, rectangle, octagon, dodecagon, ellipse or circle, etc.). The cross-sectional shapes of the first test ring 131 and the second test ring 132 are also closed figures. The through-silicon via 110 is completely surrounded by the first test ring 131, and the through-silicon via 110 is completely surrounded by the second test ring 132. Thus, the protection structure 130 can play a better stress protection role, and can detect cracks in all directions around the through-silicon via 110 in this plane, which is beneficial to improving the comprehensiveness and accuracy of crack detection.

[0094] The constituent material of the first dielectric layer 133 may include a low dielectric constant material, such as silicon dioxide or tetraethyl orthosilicate, etc.

[0095] The constituent material of the first connection layer 134 is a conductive material, which may include a conductive metal, such as copper or tungsten, etc. Refer to Figure 1b As shown, the first connection layer 134 may be substantially parallel to the plane where the substrate 120 is located. In some embodiments, the first connection layer 134 may also have a certain angle with the substrate 120.

[0096] For the semiconductor structure 100 provided by the embodiments of the present disclosure, by providing the protection structure 130 around the through-silicon via 110, the protection structure 130 can locally release stress for the through-silicon via 110. Moreover, the protection structure 130 can also play a role in isolating stress. Specifically, the protection structure 130 can isolate the stress transfer between the through-silicon via 110 and the structures outside the protection structure 130, reducing the mutual stress influence between the through-silicon via 110 and the peripheral structures, and playing a certain protection role for both the through-silicon via 110 and the peripheral structures, which is beneficial to ensuring better quality of the formed devices.

[0097] In addition, since the conductive first test loop 131 and the second test loop 132 in the protection structure 130 are electrically insulated from the through-silicon via 110 by a dielectric material respectively, and the first connection layer 134 located in the first dielectric layer 133 electrically connects the first test loop 131 and the second test loop 132, the first electrical parameter of the first path in the protection structure 130 that is electrically connected to the first contact 1311 and the second contact 1321 can be determined by providing a first electrical signal to the first contact 1311 at the end of the first test loop 131 and the second contact 1321 at the end of the second test loop 132, and whether there is a crack in the through-silicon via 110 can be determined according to the first electrical parameter, so as to achieve stress detection (i.e., crack detection), and the measurement method is simple and fast.

[0098] Furthermore, since the first test loop 131 and the second test loop 132 included in the protection structure 130 are conductive, when the first test loop 131 and the second test loop 132 are grounded, the first test loop 131 and the second test loop 132 can also perform electromagnetic shielding on the through-silicon via 110.

[0099] In some embodiments, referring to Figure 2a and Figure 2b as shown, the protection structure 130 further includes:

[0100] a conductive third test loop 135, vertically penetrating the substrate 120, disposed around the through-silicon via 110, and located between the second test loop 132 and the through-silicon via 110, and the end of the third test loop 135 includes a third contact 1351;

[0101] a second connection layer 136, located between the second test loop 132 and the third test loop 135, electrically connecting the second test loop 132 and the third test loop 135; wherein, in the direction perpendicular to the substrate 120, the second connection layer 136 is located between the third contact 1351 and the first connection layer 134.

[0102] The constituent material of the third test loop 135 may include: copper or tungsten. The third contact 1351 is used to receive the electrical signal applied to the third test loop 135. The third contact 1351, the first contact 1311, and the second contact 1221 may use the same material, such as aluminum for example.

[0103] The constituent material of the second connection layer 136 is a conductive material, and may include a conductive metal, such as copper or tungsten, etc. Referring to Figure 2b as shown, the second connection layer 136 may be substantially parallel to the plane where the substrate 120 is located. In some embodiments, the second connection layer 136 may also have a certain angle with the substrate 120. It can be understood that in the direction perpendicular to the substrate 120, the second connection layer 136 only needs to be disposed between the plane where the third contact 1351 is located and the plane where the first connection layer 134 is located.

[0104] It is understandable that a second dielectric layer (not shown in the figure) may be provided between the third test ring 135 and the second test ring 132 for electrically isolating the third test ring 135 from the second test ring 132. The composition material of the second dielectric layer may be the same as that of the first dielectric layer 133.

[0105] The second connection layer 136 is located in the second dielectric layer. It should be emphasized that the second test ring 132 and the third test ring 135 are electrically connected through the second connection layer 136.

[0106] In some embodiments, referring to Figure 2b as shown, the first connection layer 134 electrically connects the first test ring 131, the second test ring 132, and the third test ring 135.

[0107] In other embodiments, the first connection layer 134 only electrically connects the first test ring 131 and the second test ring 132, and cannot electrically connect the second test ring 132 and the third test ring 135.

[0108] It should be emphasized that when the setting mode of the first connection layer 134 is different, different conductive paths may be formed between the first contact 1311, the second contact 1321, and the third contact 1351. Therefore, when using the semiconductor structure 100 for stress detection (i.e., crack detection), specific judgment conditions may vary, and the present disclosure will be specifically described in the test methods provided in subsequent embodiments.

[0109] In the embodiments of the present disclosure, by providing the third test ring 135 and the second connection layer 136, it is beneficial to accurately locate the crack generation position and improve the accuracy of crack testing.

[0110] In some embodiments, the protection structure 130 includes N third test rings 135 and N second connection layers 136; wherein, the first third test ring 135 to the (N - 1)th third test ring 135 are located between the second test ring 132 and the Nth third test ring 135, and N is a positive integer greater than 1;

[0111] The first second connection layer 136 electrically connects the second test ring 132 and the first third test ring 135;

[0112] The Kth second connection layer 136 electrically connects the Kth third test ring 135 and the (K + 1)th third test ring 135; wherein, K is a positive integer less than N.

[0113] It can be understood that when the number of the third test rings 135 and the second connection layers 136 is larger, the area occupied by the protection structure 130 will be larger. Therefore, the number of the third test rings 135 and the number of the second connection layers 136 can be determined according to actual requirements.

[0114] In the embodiments of the present disclosure, by providing a plurality of third test rings 135 and a plurality of second connection layers 136, layer-by-layer analysis can be performed to determine between which two adjacent second connection layers 136 the crack specifically exists, and / or to determine whether the crack exists between the first connection layer 134 and the nearest second connection layer 136, which is beneficial to further accurately locate the crack generation position and further improve the accuracy of crack detection.

[0115] In some embodiments, in a direction parallel to the plane where the substrate 120 is located,

[0116] The cross-sectional shape of the first test ring 131 includes: a regular polygon or an annular shape;

[0117] The cross-sectional shape of the second test ring 132 includes: a regular polygon or an annular shape; wherein, the symmetry center of the cross-sectional shape of the first test ring 131 coincides with the symmetry center of the cross-sectional shape of the second test ring 132;

[0118] The cross-sectional center of the through-silicon via 110 covers the symmetry center of the cross-sectional shape of the first test ring 131.

[0119] Exemplarily, in a direction parallel to the plane where the substrate 120 is located, when the cross-sectional shape of the first test ring 131 is a regular polygon and the cross-sectional shape of the second test ring 132 is also a regular polygon, the cross-sectional shape of the first test ring 131 and the cross-sectional shape of the second test ring 132 may be different or the same. For example, the cross-sectional shape of the first test ring 131 may be a square, and the cross-sectional shape of the second test ring 132 may be an equilateral triangle, a square, a regular hexagon, a regular octagon, a regular dodecagon or a circle, etc.

[0120] It should be emphasized that in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the first test ring 131 and the cross-sectional shape of the second test ring 132 have no intersection points.

[0121] Preferably, in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the first test ring 131 is the same as the cross-sectional shape of the second test ring 132. Since the symmetry center of the cross-sectional shape of the first test ring 131 coincides with the symmetry center of the cross-sectional shape of the second test ring 132, in this way, the distances at various positions between the first test ring 131 and the second test ring 132 are the same.

[0122] Exemplarily, in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the through-silicon via 110 may include a circle, a square, a rectangle, etc. Preferably, the through-silicon via 110 is cylindrical, and in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the through-silicon via 110 is circular. In this way, the difficulty of etching to form the via can be reduced, and the difficulty of filling a conductive material into the via to form the through-silicon via 110 can be reduced.

[0123] In a direction parallel to the plane where the substrate 120 is located, since the center of the cross-section of the through-silicon via 110 covers the center of symmetry of the cross-sectional shape of the first test ring 131, that is, the center of the cross-section of the through-silicon via 110 overlaps with the center of symmetry of the cross-sectional shape of the first test ring 131. In this way, the layout of the protection structure 130 can be optimized, and the occupation of the area of the substrate 120 by the protection structure 130 can be reduced.

[0124] In some embodiments, in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the third test ring 135 includes: a regular polygon or an annular shape; wherein, the center of symmetry of the cross-sectional shape of the third test ring 135 coincides with the center of symmetry of the cross-sectional shape of the second test ring 132, and the center of the cross-section of the through-silicon via 110 coincides with the center of symmetry of the cross-sectional shape of the third test ring 135.

[0125] Exemplarily, in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the third test ring 135 may be different from the cross-sectional shape of the first test ring 131 and / or the cross-sectional shape of the second test ring 132. It should be emphasized that in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shape of the third test ring 135 has no intersection with the cross-sectional shape of the first test ring 131, and the cross-sectional shape of the third test ring 135 has no intersection with the cross-sectional shape of the second test ring 132.

[0126] Preferably, in a direction parallel to the plane where the substrate 120 is located, the cross-sectional shapes of the first test ring 131, the second test ring 132, and the third test ring 135 are the same, and the centers of symmetry of the first test ring 131, the second test ring 132, and the third test ring 135 coincide. In this way, the distances between various parts between the third test ring 135 and the first test ring 131 are the same, and the distances between various parts between the third test ring 135 and the second test ring 132 are the same.

[0127] Figure 3 is a schematic diagram of a memory 200 shown according to an exemplary embodiment. Refer to Figure 3 As shown, the memory 200 includes:

[0128] A semiconductor structure 100; wherein, the substrate 120 includes a substrate 121 and an insulating layer 122 covering the substrate 121;

[0129] The storage element 210 is disposed in the insulating layer 122.

[0130] Exemplarily, the memory 200 includes, but is not limited to, a Dynamic Random Access Memory (DRAM), a three-dimensional NAND memory, a phase change memory, etc.

[0131] In the memory 200, the through-silicon via 110 in the semiconductor structure 100 can be electrically connected to functional structures disposed on both sides of the substrate 120, and / or the through-silicon via 110 in the semiconductor structure 100 can be used for crack testing.

[0132] It can be understood that when the through-silicon via 110 in the semiconductor structure 100 is used for crack testing, the semiconductor structure 100 is a test structure, and the through-silicon via 110 therein does not function as an electrical connection to the functional structure.

[0133] It should be emphasized that the storage element 210 is disposed on the outer side of the protection structure 130 away from the through-silicon via 110, and the protection structure 130 is located between the storage element 210 and the through-silicon via 110.

[0134] In the memory 200 provided by the embodiments of the present disclosure, by providing the semiconductor structure 100, the protection structure 130 in the semiconductor structure 100 can play a role in locally releasing stress on the through-silicon via 110. Moreover, the protection structure 130 can also play a role in isolating stress. Specifically, the protection structure 130 can isolate the stress transmission between the through-silicon via 110 and the structures outside the protection structure 130 (for example, the storage element 210), reduce the stress interaction between the through-silicon via 110 and the surrounding structures, and play a certain protective role for the through-silicon via 110 and the surrounding structures, which is beneficial to ensuring better quality of the memory 200.

[0135] In addition, since the conductive first test ring 131 and the second test ring 132 in the protection structure 130 are both electrically insulated from the through-silicon via 110, and the first connection layer 134 in the first dielectric layer 133 electrically connects the first test ring 131 and the second test ring 132, the first electrical parameter of the first path electrically connected to the first contact 1311 and the second contact 1321 in the protection structure 130 can be determined by providing a first electrical signal to the first contact 1311 at the end of the first test ring 131 and the second contact 1321 at the end of the second test ring 132, and whether the through-silicon via 110 has cracks can be determined according to the first electrical parameter, and the measurement method is simple and fast.

[0136] It should be emphasized that when the semiconductor structure 100 is only used for crack testing, the memory 200 may further include other preset structures that have the same structure as the semiconductor structure 100 and are used to electrically connect the stacked structures. The preset structure and the semiconductor structure 100 used for testing may be formed simultaneously. Thus, the quality of the preset structure can be reflected according to the test results of the semiconductor structure 100 used for testing. Further, the manufacturing process of the preset structure can be adjusted according to the test results of the semiconductor structure 100 used for testing to improve the quality of the formed preset structure, thereby improving the quality of the memory 200.

[0137] Moreover, since the first test ring 131 and the second test ring 132 included in the protection structure 130 are conductive, when the first test ring 131 and / or the second test ring 132 is grounded, the protection structure 130 can also perform electromagnetic shielding on the through-silicon via 110.

[0138] In some embodiments, the memory 200 further includes:

[0139] A conductive interconnect structure electrically connected to the storage element 210;

[0140] Wherein, the interconnect structure is formed simultaneously with the protection structure 130.

[0141] Along the first direction, the conductive interconnect structure may include: a first conductive contact (PC), an initial metal layer (M0), a second conductive contact (CT), a first metal layer (M1), a first conductive via (V1), a second metal layer (M2), a second conductive via (V2), and a third metal layer (M3) stacked.

[0142] Refer to Figure 1b As shown, along the first direction, the first test ring 131 may include a first conductive contact, a second conductive contact, a first metal layer, a first conductive via, a second metal layer, a second conductive via, and a third metal layer (i.e., the first contact 1311) stacked in sequence, and the second test ring 132 may include a first conductive contact, a second conductive contact, a first metal layer, a first conductive via, a second metal layer, a second conductive via, and a third metal layer (i.e., the second contact 1321) stacked in sequence.

[0143] It should be emphasized that the same structures in the interconnect structure, the first test loop 131, and the second test loop 132 are formed simultaneously. For example, the first conductive contact in the interconnect structure, the first conductive contact in the first test loop 131, and the first conductive contact in the second test loop 132 are formed simultaneously; the second conductive contact in the interconnect structure, the second conductive contact in the first test loop 131, and the second conductive contact in the second test loop 132 are formed simultaneously; the first metal layer in the interconnect structure, the first metal layer in the first test loop 131, and the first metal layer in the second test loop 132 are formed simultaneously, and so on. The third metal layer in the interconnect structure, the third metal layer in the first test loop 131, and the third metal layer in the second test loop 132 are formed simultaneously. The first connection layer 134 can be formed simultaneously with the initial metal layer in the interconnect structure.

[0144] Exemplarily, as Figure 1b shown, one end of the first connection layer 134 can be disposed between the first conductive contact and the second conductive contact of the first test loop 131; the other end of the first connection layer 134 can be disposed between the first conductive contact and the second conductive contact of the second test loop 132.

[0145] In some other embodiments, the first conductive contact and the second conductive contact of the first test loop 131 are in direct contact, the first conductive contact and the second conductive contact of the second test loop 132 are in direct contact, one end of the first connection layer 134 contacts the first conductive contact and / or the second conductive contact of the first test loop 131, and the other end of the first connection layer 134 contacts the first conductive contact and / or the second conductive contact of the second test loop 132.

[0146] When the semiconductor structure 100 includes the second connection layer 136, the second connection layer 136 is formed simultaneously with the first metal layer in the interconnect structure. At this time, the second connection layer 136, the first metal layer in the first test loop 131, and the first metal layer in the second test loop 132 are formed simultaneously, and the second connection layer 136, the second connection layer 136, the first metal layer in the first test loop 131, and the first metal layer in the second test loop 132 can be an integral structure.

[0147] In this way, the protection structure 130 can be formed simultaneously while forming the interconnect structure. Compared with forming the interconnect structure and the protection structure 130 separately in terms of timing, by forming the interconnect structure and the protection structure 130 simultaneously, the process steps can be optimized and the efficiency can be improved.

[0148] In some embodiments, the memory 200 further includes:

[0149] Transistors, located on the surface of the substrate 121;

[0150] One end of the protection structure 130 is electrically connected to the gate of the transistor, and the other end of the protection structure 130 is used to receive an external electrical signal.

[0151] Referring to Figure 1b As shown, the gate (PG) of the transistor may be located on the surface of the substrate 121. An ion implantation well (Well IMP) may be formed by ion implanting the active region of the substrate 121.

[0152] It can be understood that the other end of the above protection structure 130 is the end provided with the first contact 1311 and the second contact 1321. When the protection structure 130 includes a third test ring 135, the first contact 1311, the second contact 1321, and the third contact 1351 are located at the same end of the protection structure 130. Therefore, the other end of the above protection structure 130 is also the end provided with the third contact 1351.

[0153] In some embodiments, the other end of the above protection structure 130 is grounded.

[0154] In some embodiments, the substrate 121 includes: a dicing street located between two adjacent memory chip regions; and a plurality of semiconductor structures 100 arranged at equal intervals in the dicing street.

[0155] It can be understood that when the semiconductor structure 100 is arranged in the dicing street, the semiconductor structure 100 only serves as a test structure for crack testing.

[0156] In the embodiments of the present disclosure, by arranging the semiconductor structure 100 for crack testing in the dicing street, the occupation of the effective area on the surface of the substrate 120 for arranging the memory elements 210 can be reduced, and the integration degree of the memory 200 will not be affected.

[0157] In addition, by arranging a plurality of semiconductor structures 100 at equal intervals in the dicing street, more accurate stress detection results can be obtained by testing the plurality of semiconductor structures 100.

[0158] Figure 4 is a flowchart of a crack testing method shown according to an exemplary embodiment. The crack testing method can be applied to test the semiconductor structure 100 provided in the embodiments of the present disclosure to test whether there are cracks in the semiconductor structure 100. Referring to Figure 4 As shown, the crack testing method includes the following steps:

[0159] S100: Provide a semiconductor structure;

[0160] S110: Provide a first electrical signal to the first contact at the end of the first test ring and the second contact at the end of the second test ring, and determine the first electrical parameter of the first path electrically connected to the first contact and the second contact in the protection structure;

[0161] S120: When the first electrical parameter meets the first preset condition, it is determined that there is no crack in the through-silicon via.

[0162] S130: When the first electrical parameter does not meet the first preset condition, it is determined that there is a crack in the through-silicon via.

[0163] In S110, the first path may include Figure 5 the path L1 shown in, and the first electrical signal may include a voltage signal or a current signal.

[0164] S110 may include: providing a preset voltage signal to the first contact and the second contact, and there is a voltage difference between the first contact and the second contact to provide a current signal to the path between the first contact and the second contact. Alternatively, S110 may include providing a current signal to the first contact and the second contact.

[0165] Exemplarily, the first electrical parameter may include: voltage difference, current or resistance. Hereinafter, an example in which the first electrical parameter is resistance will be described.

[0166] S110 may further include: measuring the voltage difference between the first contact and the second contact. Further, the resistance between the first contact and the second contact may be determined according to the current signal provided to the first contact and the second contact and the measured voltage difference between the first contact and the second contact. It can be understood that when the first contact and the second contact are connected only through the first path, the determined resistance is the resistance of the first path.

[0167] In S120 and S130, taking the first electrical parameter as the voltage difference as an example, the first preset condition may include: the first electrical parameter is less than or equal to the first voltage difference threshold.

[0168] Taking the first electrical parameter as resistance as an example, the first preset condition may include: the first electrical parameter is less than or equal to the first resistance threshold. In practical applications, when there is no crack around the through-silicon via 100, the resistance between the first contact and the second contact is within a certain range (for example, less than or equal to the first resistance threshold). When a crack appears in the through-silicon via 110, usually the crack will extend to the protection structure 130, resulting in at least partial fracture of at least one test loop (for example, the first test loop 131, the second test loop 132 or the third test loop 135) in the protection structure 130, resulting in an increase in the measured resistance between the first contact and the second contact (for example, greater than the first resistance threshold).

[0169] Specifically, taking Figure 1aTaking the illustrated semiconductor structure 100 as an example, when a crack appears in the through-silicon via 110, in the direction parallel to the substrate 121, the crack extends to the second test ring 132, causing the second test ring 132 to break, and part or all of the first path between the first contact 1311 and the second contact 1321 is disconnected. At this time, the resistance of the first path is very large and greater than the first resistance threshold. Exemplarily, when a positive voltage is provided to the first contact 1311 at the end of the first test ring 131 and a negative voltage is provided to the second contact 1321 at the end of the second test ring 132, and the first path is conducting, the current can flow along the direction of the first test ring 131, the first connection layer 134, and the second test ring 132. When the first path is partially disconnected, the current can still flow along the direction of the first test ring 131, the first connection layer 134, and the second test ring 132, but at this time the resistance of the first path is greater than the first resistance threshold. When the first path is completely disconnected, no current path can be formed along the first test ring 131, the first connection layer 134, and the second test ring 132.

[0170] The crack testing method provided by the embodiments of the present disclosure can determine the first electrical parameter of the first path in the protection structure 130 that is electrically connected to the first contact 1311 and the second contact 1321 by providing a first electrical signal to the first contact 1311 at the end of the first test ring 131 and the second contact 1321 at the end of the second test ring 132, and determine whether a crack appears in the through-silicon via 110 according to the first electrical parameter. The measurement method is simple and fast.

[0171] In some embodiments, the protection structure 130 further includes a conductive third test ring 135 and a second connection layer 136, and the second connection layer 136 electrically connects the second test ring 132 and the third test ring 135;

[0172] The crack testing method further includes:

[0173] Providing a second electrical signal to the second contact 1321 and the third contact 1351 at the end of the third test ring 135 to determine the second electrical parameter of the second path (for example, Figure 6a the path L2 shown in ) in the protection structure 130 that is electrically connected to the second contact 1321 and the third contact 1351;

[0174] When the first electrical parameter meets the first preset condition and the second electrical parameter meets the second preset condition, it is determined that no crack appears in the through-silicon via 110;

[0175] When the first electrical parameter does not meet the first preset condition, it is determined that a crack appears in the first region of the through-silicon via 110 relatively close to the first connection layer 134;

[0176] When the second electrical parameter does not meet the second preset condition, it is determined that a crack appears in the second region of the through-silicon via 110 relatively close to the second connection layer 136.

[0177] Exemplarily, the second electrical parameter includes at least one of the following: resistance; current; voltage difference.

[0178] Taking the second electrical parameter being resistance as an example, the second preset condition includes: the resistance is less than a second resistance threshold.

[0179] Referring to Figure 6a and Figure 6b As shown, the first region includes: the region of the semiconductor structure 100 between the first plane where the first connection layer 134 is located and the second plane where the second connection layer 136 is located.

[0180] The second region includes: the region of the semiconductor structure 100 between the second plane where the second connection layer 136 is located and the third plane where the first contact 1311 and the second contact 1321 are located.

[0181] It can be understood that in the embodiments of the present disclosure, the first connection layer 134 does not directly contact the third test ring 135. The first connection layer 134 is electrically connected to the first test ring 131 and the second test ring 132, and the second test ring 132 and the third test ring 135 are not electrically connected through the first connection layer 134. However, when the electrical connection path between the first connection layer 134 and the second connection layer 136 is not broken, the first connection layer 134 can still achieve electrical connection with the third test ring 135 through the second test ring 132 and the second connection layer 136.

[0182] Similarly, in the embodiments of the present disclosure, the second connection layer 136 does not directly contact the first test ring 131. When the electrical connection path between the first connection layer 134 and the second connection layer 136 is not broken, the second connection layer 136 can still achieve electrical connection with the first test ring 131 through the second test ring 132 and the first connection layer 134.

[0183] The testing method provided by the embodiments of the present disclosure can be analyzed layer by layer to further determine the region where the crack exists, thereby further improving the accuracy of crack detection.

[0184] In some embodiments, referring to Figure 7a and Figure 7b As shown, the protection structure 130 further includes a conductive third test ring 135 and a second connection layer 136. The first connection layer 134 is electrically connected to the first test ring 131, the second test ring 132, and the third test ring 135; the crack testing method further includes:

[0185] Providing a second electrical signal to the second contact 1321 and the third contact 1351 at the end of the third test ring 135, and determining the second electrical parameter of the second path in the protection structure 130 that is electrically connected to the second contact 1321 and the third contact 1351;

[0186] When the first electrical parameter meets the first preset condition and the second electrical parameter meets the second preset condition, it is determined that there is no crack in the through-silicon via 110;

[0187] When the first electrical parameter does not meet the first preset condition and the second electrical parameter meets the second preset condition, it is determined that there is a crack in the region of the through-silicon via 110 near the first connection layer 134 between the first test ring 131 and the second test ring 132;

[0188] When the first electrical parameter meets the first preset condition and the second electrical parameter does not meet the second preset condition, it is determined that there is a crack in the region of the through-silicon via 110 near the first connection layer 134 between the first test ring 131 and the second test ring 132.

[0189] In some embodiments, as shown in Figure 8 The crack testing method may further include:

[0190] Providing a third electrical signal to the first contact 1311 and the third contact 1351, and determining the third electrical parameter of the third path (e.g., path L3) in the protection structure 130 that is electrically connected to the first contact 1311 and the second contact 1321;

[0191] When the third electrical parameter meets the third preset condition, it is determined that there is no crack in the through-silicon via 110;

[0192] When the third electrical parameter does not meet the third preset condition, it is determined that there is a crack in the through-silicon via 110.

[0193] Taking the third electrical parameter as resistance as an example, the third preset condition includes: the resistance is less than the third resistance threshold.

[0194] It should be emphasized that the values of the first resistance threshold, the second resistance threshold, and the third resistance threshold can all be set according to the actual situation. The first resistance threshold, the second resistance threshold, and the third resistance threshold may be at least partially the same or each different.

[0195] In the embodiments provided by the present disclosure, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: Through-Silicon Via (TSV), penetrating the substrate; Protection structure, comprising: Conductive first test ring and conductive second test ring, both disposed around the Through-Silicon Via and electrically insulated from the Through-Silicon Via; First dielectric layer, located between the first test ring and the second test ring, for electrically isolating the first test ring and the second test ring; First connection layer, located within the first dielectric layer, electrically connecting the first test ring and the second test ring.

2. The semiconductor structure according to claim 1, wherein The protection structure further comprises: Conductive third test ring, vertically penetrating the substrate, disposed around the Through-Silicon Via and located between the second test ring and the Through-Silicon Via, the end of the third test ring comprising a third contact; Second connection layer, located between the second test ring and the third test ring, electrically connecting the second test ring and the third test ring; wherein, in the direction perpendicular to the substrate, the second connection layer is located between the third contact and the first connection layer.

3. The semiconductor structure according to claim 2, wherein The protection structure comprises N third test rings and N second connection layers; wherein, the 1st to the (N - 1)th third test rings are located between the second test ring and the Nth third test ring, N being a positive integer greater than 1; The 1st second connection layer electrically connects the second test ring and the 1st third test ring; The Kth second connection layer electrically connects the Kth third test ring and the (K + 1)th third test ring; wherein, K is a positive integer less than N.

4. The semiconductor structure according to claim 2, wherein The first connection layer electrically connects the first test ring, the second test ring and the third test ring.

5. The semiconductor structure according to claim 1, wherein In the direction parallel to the plane of the substrate, The cross-sectional shape of the first test ring includes: regular polygon or circular ring; The cross-sectional shape of the second test ring includes: regular polygon or circular ring; wherein, the symmetry center of the cross-sectional shape of the first test ring coincides with the symmetry center of the cross-sectional shape of the second test ring; The cross-sectional center of the Through-Silicon Via covers the symmetry center of the cross-sectional shape of the first test ring.

6. A memory, characterized in that, Comprising: The semiconductor structure according to any one of claims 1 to 5; wherein, the substrate comprises a substrate and an insulating layer covering the substrate; Memory element, disposed in the insulating layer.

7. The memory according to claim 6, wherein The memory further comprises: Conductive interconnect structure, electrically connected to the memory element; Wherein, the interconnect structure and the protection structure are formed simultaneously.

8. The memory according to claim 7, characterized in that, The memory further comprises: Transistor, located on the surface of the substrate; One end of the protection structure is electrically connected to the gate of the transistor, and the other end of the protection structure is for receiving an external electrical signal.

9. The memory according to claim 8, wherein The other end of the protection structure is grounded.

10. The memory according to claim 6, characterized in that The substrate comprises: Scribing lane, located between two adjacent memory chip regions; Multiple semiconductor structures, equally spaced in the scribing lane.

11. A crack testing method, characterized in that, Applied to test the semiconductor structure according to any one of claims 1 to 5, the crack test method comprises: Providing the semiconductor structure; A first electrical signal is provided to a first contact at an end of the first test ring and a second contact at an end of the second test ring, and a first electrical parameter of a first path electrically connected to the first contact and the second contact in the protection structure is determined; When the first electrical parameter meets a first preset condition, it is determined that no crack appears in the through-silicon via; When the first electrical parameter does not meet the first preset condition, it is determined that a crack appears in the through-silicon via.

12. The crack testing method according to claim 11, wherein The protection structure further includes a conductive third test ring and a second connection layer, and the second connection layer electrically connects the second test ring and the third test ring; The crack testing method further includes: A second electrical signal is provided to the second contact and a third contact at an end of the third test ring, and a second electrical parameter of a second path electrically connected to the second contact and the third contact in the protection structure is determined; When the first electrical parameter meets the first preset condition and the second electrical parameter meets a second preset condition, it is determined that no crack appears in the through-silicon via; When the first electrical parameter does not meet the first preset condition, it is determined that a crack appears in a first region of the through-silicon via relatively close to the first connection layer; When the second electrical parameter does not meet the second preset condition, it is determined that a crack appears in a second region of the through-silicon via relatively close to the second connection layer.

13. The crack testing method according to claim 11, wherein, The protection structure further includes a conductive third test ring and a second connection layer, and the first connection layer electrically connects the first test ring, the second test ring, and the third test ring; The crack testing method further includes: A second electrical signal is provided to the second contact and a third contact at an end of the third test ring, and a second electrical parameter of a second path electrically connected to the second contact and the third contact in the protection structure is determined; When the first electrical parameter meets the first preset condition and the second electrical parameter meets the second preset condition, it is determined that no crack appears in the through-silicon via; When the first electrical parameter does not meet the first preset condition and the second electrical parameter meets the second preset condition, it is determined that a crack appears in a region of the through-silicon via close to the first connection layer between the first test ring and the second test ring; When the first electrical parameter meets the first preset condition and the second electrical parameter does not meet the second preset condition, it is determined that a crack appears in a region of the through-silicon via close to the first connection layer between the first test ring and the second test ring.

14. The crack testing method according to claim 12 or 13, wherein The first electrical parameter and the second electrical parameter include at least one of the following: resistance; current; voltage difference.

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