Array substrate and manufacturing method thereof, and display panel

Abstract

The present application discloses an array substrate and a manufacturing method thereof, and a display panel; the array substrate comprises a substrate, a gate layer, and an active layer, the gate layer comprises a first gate sublayer and a second gate sublayer; the first gate sublayer and the second gate sublayer do not completely overlap, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, and the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer; the present application arranges the gate layer as the first gate sublayer and the second gate sublayer, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the second gate sublayer on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and since the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer, when the active layer is subjected to a high-temperature crystallization process, the high temperature will not cause the first gate sublayer to melt or break.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Low-temperature polysilicon thin-film transistors have the advantages of high mobility and good stability and are widely used in array substrates of various sizes. In large-size glass substrates such as the G10.5 generation line, BLDA (Blue Laser Diode Anneal) is used to crystallize amorphous silicon. The BLDA laser has a deeper penetration depth and can convert amorphous silicon into polysilicon with high crystallinity, large grain size, and no grain boundary protrusions, thereby achieving high mobility and excellent anti-folding performance.

[0003] In the existing manufacturing process of back-channel thin film transistors, due to the high BLDA energy, the metal wires in the laser irradiation area may be melted or broken, resulting in abnormality of the array substrate.

[0004] Therefore, an array substrate is urgently needed to solve the above technical problems. Summary of the invention

[0005] The present application provides an array substrate and a manufacturing method thereof, and a display panel, so as to improve the technical problem of gate melting or disconnection of a thin film transistor in a BLDA process.

[0006] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0007] The present application provides an array substrate, the array substrate comprising:

[0008] substrate;

[0009] A gate layer is disposed on the substrate, the gate layer comprising a first gate sublayer and a second gate sublayer which are stacked, and the second gate sublayer is located on a side of the first gate sublayer away from the substrate;

[0010] An active layer, disposed on a side of the gate layer away from the substrate;

[0011] The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the second gate sublayer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the second gate sublayer on the substrate, and the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer.

[0012] In the array substrate of the present application, the array substrate further comprises a source-drain layer disposed on a side of the active layer away from the substrate, the source-drain layer comprises a first source-drain sublayer and a second source-drain sublayer stacked, and the second source-drain sublayer is located on a side of the first source-drain sublayer away from the substrate;

[0013] Among them, the orthographic projection of the first source-drain sublayer on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the second source-drain sublayer on the substrate at least partially overlaps with the orthographic projection of the first source-drain sublayer on the substrate; the melting point of the first source-drain sublayer is higher than the melting point of the second source-drain sublayer.

[0014] In the array substrate of the present application, the resistivity of the second source-drain sub-layer is smaller than the resistivity of the first source-drain sub-layer.

[0015] In the array substrate of the present application, the array substrate further comprises a doping layer disposed between the active layer and the first source-drain sublayer, and the orthographic projection of the doping layer on the substrate is located within the orthographic projection of the first source-drain sublayer on the substrate.

[0016] In the array substrate of the present application, the array substrate further comprises a gate insulating layer disposed between the gate layer and the active layer, a passivation layer disposed on a side of the source and drain electrode layer away from the substrate, a first via hole, and a second via hole;

[0017] The first via hole penetrates the passivation layer and the gate insulating layer and exposes the second gate sublayer; the second via hole penetrates the passivation layer and exposes the second source and drain sublayer.

[0018] In the array substrate of the present application, a small portion of the second source-drain sublayer is arranged in the same layer as the active layer, and one end of the second source-drain sublayer close to the active layer contacts a surface of the first source-drain sublayer facing away from the substrate.

[0019] In the array substrate of the present application, the resistivity of the second gate sublayer is smaller than the resistivity of the first gate sublayer.

[0020] The present application also provides a method for manufacturing an array substrate, the method comprising:

[0021] A first gate material layer and a second gate material layer are sequentially formed on a substrate, and patterned so that the first gate material layer forms a first gate sublayer and the second gate material layer forms a second gate sublayer, an orthographic projection of the second gate sublayer on the substrate is located within an orthographic projection of the first gate sublayer on the substrate, and a melting point of the first gate sublayer is higher than a melting point of the second gate sublayer;

[0022] forming a gate insulating layer on the substrate, wherein the gate insulating layer covers the first gate sublayer and the second gate sublayer;

[0023] At least an active material layer is formed on the gate insulating layer, and the active material layer is patterned to form an active layer. The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, and the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the second gate sublayer on the substrate.

[0024] In the manufacturing method of the present application, at least an active material layer is formed on the gate insulating layer, and the step of forming the active layer by patterning the active material layer includes:

[0025] Sequentially forming the active material layer and the first source and drain material layer on the gate insulating layer;

[0026] Using a same photomask to pattern the active material layer and the first source-drain material layer to form the active layer and the first source-drain sublayer;

[0027] The active layer is processed by a preset process to crystallize the active layer.

[0028] The present application also provides a display panel, which includes the above-mentioned array substrate.

[0029] Beneficial effects: The present application discloses an array substrate; the array substrate comprises a substrate, a gate layer arranged on the substrate, and an active layer arranged on a side of the gate layer away from the substrate, the gate layer comprises a first gate sublayer and a second gate sublayer arranged in a stacked manner, the second gate sublayer is located on a side of the first gate sublayer away from the substrate; the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the second gate sublayer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, and the active layer is located on the substrate The orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the second gate sublayer on the substrate, and the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer; in the present application, by setting the gate layer to the first gate sublayer and the second gate sublayer, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, and the orthographic projection of the second gate sublayer on the substrate does not overlap with the orthographic projection of the active layer on the substrate. Since the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer, when the active layer is subjected to a high-temperature crystallization process, the high temperature will not cause the first gate sublayer to melt or break. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0031] Figure 1 is a structural schematic diagram of a cross-sectional view of an array substrate of the present application;

[0032] Figure 2 is a schematic structural diagram of a top view of an array substrate of the present application;

[0033] FIG. 3A to FIG. 3E Schematic diagram of the process flow of the method for manufacturing the array substrate of the present application.

[0034] Description of reference numerals:

[0035] Substrate 10, gate layer 20, first gate sublayer 21, second gate sublayer 22, active layer 30, source and drain contact area 30a, channel area 30b, source and drain layer 40, first source and drain sublayer 41, second source and drain sublayer 42, doping layer 50, gate insulation layer 60, passivation layer 70, first via 81, second via 82, first gate material layer 210, second gate material layer 220, active material layer 300, first source and drain material layer 410, doping material layer 500, photoresist PR. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0037] In the existing back channel thin film transistor manufacturing process, due to the high BLDA energy, the metal wires in the laser irradiation area may melt or break, resulting in abnormal array substrate. Based on the above technical problems, the present application proposes the following solutions.

[0038] The present application discloses an array substrate; the array substrate comprises a substrate 10, a gate layer 20 arranged on the substrate 10, and an active layer 30 arranged on a side of the gate layer 20 away from the substrate 10, the gate layer 20 comprises a first gate sublayer and a second gate sublayer 22 arranged in a stacked manner, the second gate sublayer 22 is located on a side of the first gate sublayer away from the substrate 10; the orthographic projection of the active layer 30 on the substrate 10 is located within the orthographic projection of the first gate sublayer on the substrate 10, the orthographic projection of the second gate sublayer 22 on the substrate 10 is located within the orthographic projection of the first gate sublayer on the substrate 10, the orthographic projection of the active layer 30 on the substrate 10 does not overlap with the orthographic projection of the second gate sublayer 22 on the substrate 10, and the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer 22.

[0039] In the present application, the gate layer 20 is set to the first gate sublayer 21 and the second gate sublayer 22, the orthographic projection of the active layer 30 on the substrate 10 is located within the orthographic projection of the first gate sublayer 21 on the substrate 10, and the orthographic projection of the second gate sublayer 22 on the substrate 10 does not overlap with the orthographic projection of the active layer 30 on the substrate 10. Since the melting point of the first gate sublayer 21 is higher than the melting point of the second gate sublayer 22, when the active layer 30 is subjected to a high-temperature crystallization process, the high temperature will not cause the first gate sublayer 21 to melt or break.

[0040] See also Figure 1 and Figure 2 The array substrate includes a substrate 10 and a thin film transistor array layer arranged on the substrate 10, and the thin film transistor array layer includes a gate layer 20, a gate insulating layer 60, and an active layer 30 which are stacked. In the present application, the material of the active layer 30 is amorphous silicon (a-si), and the active layer 30 is processed by the BLDA process to convert amorphous silicon into polycrystalline silicon (poly-si). Due to the high BLDA energy, the metal wires in the thin film transistor array layer are easily affected by high temperature, melting or disconnection. If the BLDA energy is reduced, the crystallization temperature of amorphous silicon will be insufficient, the grains will be small or the crystallization will fail, and the mobility of the active layer 30 will be lost.

[0041] The high temperature energy of BLDA is usually provided by laser, and the laser is vertically irradiated onto the active layer 30, so that the amorphous silicon is crystallized at high temperature. The active layer 30 includes a channel region 30b located in the middle area and source-drain contact regions 30a located at both ends of the channel region 30b, wherein the channel region 30b of the active layer 30 is converted from amorphous silicon to polycrystalline silicon under laser irradiation.

[0042] In this embodiment, the orthographic projection of the first gate sublayer 21 on the substrate 10 overlaps with the orthographic projection of the active layer 30 on the substrate 10, while the orthographic projection of the second gate sublayer 22 on the substrate 10 does not overlap with the orthographic projection of the active layer 30 on the substrate 10. Therefore, when the BLDA laser irradiates the active layer 30, the second gate sublayer 22 is outside the laser irradiation range and is less affected by the high temperature and is not prone to melting or breaking. The first gate sublayer 21 irradiated by the laser has a higher melting point and is not prone to melting or breaking.

[0043] The melting point of the first gate sublayer is higher than the melting point of the second gate sublayer 22. The material of the first gate sublayer 21 can be a high temperature resistant material, such as one or a stack of metal materials such as Mo or Si. The present application does not limit the material of the first gate sublayer 21. The material of the second gate sublayer 22 can be a material with a lower melting point than the first gate sublayer 21.

[0044] Further, the resistivity of the second gate sublayer 22 is lower than the resistivity of the first gate sublayer 21. The material of the second gate sublayer 22 can be the following materials with lower resistance, such as a stack of one or more of Al / Mo or Mo / Al / Mo or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb. The present application does not limit the material of the second gate sublayer 22. By setting the resistivity of the second gate sublayer 22 to be lower than the resistivity of the first gate sublayer 21, the contact resistance between the wiring of the array substrate and the gate layer 20 can be reduced, thereby reducing the voltage drop of the array substrate.

[0045] The technical solution of the present application is now described in conjunction with specific embodiments.

[0046] In the array substrate of the present application, the array substrate also includes a source-drain layer 40 arranged on the side of the active layer 30 away from the substrate 10, and the source-drain layer 40 includes a first source-drain sublayer 41 and a second source-drain sublayer 42 which are stacked, and the second source-drain sublayer 42 is located on the side of the first source-drain sublayer 41 away from the substrate 10; wherein the orthographic projection of the first source-drain sublayer 41 on the substrate 10 at least partially overlaps with the orthographic projection of the active layer 30 on the substrate 10, and the orthographic projection of the second source-drain sublayer 42 on the substrate 10 at least partially overlaps with the orthographic projection of the first source-drain sublayer 41 on the substrate 10; the melting point of the first source-drain sublayer 41 is higher than the melting point of the second source-drain sublayer 42.

[0047] Since the melting point of the first source-drain sublayer 41 is higher than the melting point of the second source-drain sublayer 42, when the laser of the BLDA is irradiated perpendicularly to the substrate 10 to the active layer 30, the first source-drain sublayer 41 is not easily affected by high temperature to melt or break. The material of the first source-drain sublayer 41 can be a high-temperature resistant material, such as one or a stack of metal Mo or Si. The present application does not limit the material of the first source-drain sublayer 41. The material of the second source-drain sublayer 42 can be a material with a lower melting point than the first source-drain sublayer 41.

[0048] Further, the resistivity of the second source-drain sublayer 42 is lower than the resistivity of the first source-drain sublayer 41. The material of the second source-drain sublayer 42 may be a material with a lower resistance, such as a stack of one or more of Al / Mo or Mo / Al / Mo or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb. The present application does not limit the material of the second source-drain sublayer 42. By setting the resistivity of the material of the second source-drain sublayer 42 to be lower than the resistivity of the material of the first source-drain sublayer 41, the contact resistance between the wiring in the array substrate and the source-drain layer 40 can be reduced, thereby reducing the voltage drop of the array substrate.

[0049] In the array substrate of the present application, the array substrate also includes a doping layer 50 arranged between the active layer 30 and the first source and drain sublayer 41, and the orthographic projection of the doping layer 50 on the substrate 10 is located within the orthographic projection of the first source and drain sublayer 41 on the substrate 10.

[0050] In the above embodiment, the array substrate further includes a doping layer 50, and the doping layer 50 is arranged in contact with the source-drain contact region 30a of the active layer 30. The material of the doping layer 50 can be N-type doped Si, and when the BLDA process is performed on the active layer 30, the doping layer 50 and the active layer 30 are crystallized synchronously. Since the BLDA process is arranged after the doping layer 50 is formed, the high temperature of the BLDA process can repair the defects formed in the back channel of the doping layer 50 and the active layer 30 during etching.

[0051] The orthographic projection of the doped layer 50 on the substrate 10 is within the orthographic projection of the first source-drain sublayer 41 on the substrate 10. It should be noted that the doped layer 50 and the first source-drain sublayer 41 can be patterned using the same halftone mask or grayscale mask, thereby saving masks. Since the etching process forms a cone angle during the patterning process, the orthographic projection of the first source-drain sublayer 41 on the substrate 10 is slightly larger than the orthographic projection of the doped layer 50 on the substrate 10.

[0052] In the array substrate of the present application, the array substrate also includes a gate insulating layer 60 arranged between the gate layer 20 and the active layer 30, a passivation layer 70 arranged on the side of the source and drain layer 40 away from the substrate 10, a first via hole 81 and a second via hole 82; wherein the first via hole 81 penetrates the passivation layer 70 and the gate insulating layer 60 and exposes the second gate sublayer 22; the second via hole 82 penetrates the passivation layer 70 and exposes the second source and drain sublayer 42.

[0053] In the above embodiment, the array substrate further includes a gate insulating layer 60 and a passivation layer 70, the gate insulating layer 60 is disposed in contact between the gate layer 20 and the active layer 30, and the passivation layer 70 is formed on the second source-drain sublayer 42. The first via hole 81 of the array substrate penetrates the passivation layer 70 and the gate insulating layer 60, exposing the second gate sublayer 22. In the first process, a connecting column is formed to realize the electrical connection between the wiring of the array substrate and the gate layer 20. Since the resistivity of the second gate sublayer 22 is lower than the resistivity of the first gate sublayer 21, the electrical connection between the wiring and the second gate sublayer 22 can reduce the contact resistance between the wiring of the array substrate and the gate layer 20, thereby reducing the voltage drop of the array substrate.

[0054] The second via hole 82 penetrates the passivation layer 70 and exposes the second source-drain sublayer 42. A connection column may be formed in the second via hole 82 to electrically connect the pixel electrode or wiring of the display panel to the source-drain layer 40. Since the resistivity of the second source-drain sublayer 42 is lower than that of the first source-drain sublayer 41, connecting the pixel electrode or wiring to the second source-drain sublayer 42 can reduce its contact resistance and reduce the voltage drop of the array substrate.

[0055] In the array substrate of the present application, a small portion of the second source-drain sublayer 42 is arranged in the same layer as the active layer 30 , and one end of the second source-drain sublayer 42 close to the active layer 30 contacts the surface of the first source-drain sublayer 41 facing away from the substrate 10 .

[0056] In the above embodiment, the second source-drain sublayer 42 is formed after the first source-drain sublayer 41 is patterned, and one end of the second source-drain sublayer 42 close to the channel region 30b of the active layer 30 contacts the upper surface of the first source-drain sublayer 41, and one end of the second source-drain sublayer 42 away from the channel region 30b of the active layer 30 is deposited on the gate insulating layer 60, so that at least part of the second source-drain sublayer 42 is arranged in the same layer as the active layer 30. One end of the second source-drain sublayer 42 close to the channel region 30b of the active layer 30 also contacts the side wall of the first source-drain sublayer 41, the side wall of the doping layer 50, and the side wall of the active layer 30, thereby increasing the contact area with the source-drain contact region 30a of the active layer 30 and improving the contact effect.

[0057] See also FIG. 3A to FIG. 3E The present application also provides a method for manufacturing an array substrate, the method comprising:

[0058] S10, sequentially forming a first gate material layer 210 and a second gate material layer 220 on a substrate 10, and patterning the first gate material layer 210 to form a first gate sublayer 21 and the second gate material layer 220 to form a second gate sublayer 22, an orthographic projection of the second gate sublayer 22 on the substrate 10 is located within an orthographic projection of the first gate sublayer 21 on the substrate 10, and a melting point of the first gate sublayer 21 is higher than a melting point of the second gate sublayer 22;

[0059] S20, forming a gate insulating layer 60 on the substrate 10, wherein the gate insulating layer 60 covers the first gate sublayer 21 and the second gate sublayer 22;

[0060] S30, at least an active material layer 300 is formed on the gate insulating layer 60, and the active material layer 300 is patterned to form an active layer 30, and the orthographic projection of the active layer 30 on the substrate 10 is located within the orthographic projection of the first gate sublayer on the substrate 10, and the orthographic projection of the active layer 30 on the substrate 10 does not overlap with the orthographic projection of the second gate sublayer 22 on the substrate 10.

[0061] In the manufacturing method of the present application, the method of forming the material layer includes conventional film forming processes in the art such as Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD), and the present application does not limit this.

[0062] The patterning process includes conventional processes such as photoresist coating, exposure and development, and etching. The present application does not limit the patterning process.

[0063] In step S10, refer to Figure 3AAfter forming the first gate material layer 210 and the second gate material layer 220, the step of patterning can be: coating the second gate material layer 220 with a photoresist PR, and using a halftone mask or a grayscale mask for exposure and development to form photoresists PR with different film thicknesses. Among them, the thickness of the photoresist PR in the area used to form the second gate sublayer 22 is greater than the thickness of the photoresist PR in other areas (the area of ​​the first gate sublayer 21 that does not overlap with the second gate sublayer 22). The second gate material layer 220 is etched, and the second gate material layer 220 in the area not covered by the photoresist PR is first etched to expose the first gate material layer 210 in the area not covered by the photoresist PR. Further etching is performed, and the first gate material layer 210 in the area not covered by the photoresist PR is etched, and the second gate material layer 220 in the area with a smaller photoresist PR film thickness is etched to form the first gate sublayer 21 and the second gate sublayer 22.

[0064] The material of the first gate sublayer 21 can be a high temperature resistant material, such as one or a stack of metal materials such as Mo or Si. The present application does not limit the material of the first gate sublayer 21.

[0065] The material of the second gate sublayer 22 can be a material with a lower resistance, such as a stack of one or more of Al / Mo, Mo / Al / Mo, Mo / Cu, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, Ni / Cu / Ni, MoTiNi / Cu / MoTiNi, NiCr / Cu / NiCr, or CuNb. The present application does not limit the material of the second gate sublayer 22.

[0066] In step S20, refer to Figure 3B , a gate insulating layer 60 is formed on the substrate 10 obtained in S10.

[0067] In step S30, refer to FIG. 3B to FIG. 3E , an active material layer 300 is formed on the gate insulating layer 60, and the active material layer 300 may be an amorphous silicon material. The active material layer 300 is patterned to form an active layer 30, wherein the orthographic projection of the active layer 30 on the substrate 10 is located within the orthographic projection of the first gate sublayer on the substrate 10, and the orthographic projection of the second gate sublayer 22 on the substrate 10 does not overlap with the orthographic projection of the active layer 30 on the substrate 10. Since the melting point of the first gate sublayer 21 is higher than the melting point of the second gate sublayer 22, when the active layer 30 is subjected to a high-temperature crystallization process, the high temperature will not cause the first gate sublayer 21 to melt or break.

[0068] In the preparation method of this application, please refer to FIG. 3B to FIG. 3C , step S30 comprises:

[0069] S301, sequentially forming the active material layer 300 and the first source and drain material layer 410 on the gate insulating layer 60;

[0070] S302, patterning the active material layer 300 and the first source-drain material layer 410 using the same photomask to form the active layer 30 and the first source-drain sublayer 41;

[0071] S303 , processing the active layer 30 using a preset process to crystallize the active layer 30 .

[0072] In step S301, refer to Figure 3B An active material layer 300 and a first source-drain material layer 410 are formed on the gate insulating layer 60 , and a doping material layer 500 may be formed between the active material layer 300 and the first source-drain material layer 410 . The doping material layer 500 may be N-type doped Si.

[0073] In step S302, refer to Figure 3B , the active material layer 300 and the first source-drain material layer 410 can be patterned using the same halftone mask or grayscale mask. First, a photoresist PR is coated on the first source-drain material layer 410, and a halftone mask or grayscale mask is used for exposure and development to form photoresists PR of different film thicknesses. Among them, the thickness of the photoresist PR film in the area used to form the first source-drain sublayer 41 is greater than the thickness of the photoresist PR film corresponding to the channel region 30b of the active layer 30. The first source-drain material layer 410 is etched, and the first source-drain material layer 410 in the area not covered by the photoresist PR is etched first. Further etching, the active material layer 300 in the area not covered by the photoresist PR is etched, and the first source-drain material layer 410 in the area with a smaller photoresist PR film thickness is etched to form the active layer 30 and the first source-drain sublayer 41.

[0074] When the array substrate includes the doping material layer 500 , the doping layer 50 , the active layer 30 , and the first source-drain sub-layer 41 can be manufactured using the same half-tone mask or gray-scale mask.

[0075] In step S303, refer to Figure 3C The preset process may be a BLDA process, and the present application does not limit the preset process, as long as it uses high temperature to crystallize the active layer 30. After the preset process, the channel region 30b of the active layer 30 is converted from amorphous silicon to polycrystalline silicon.

[0076] See also Figure 3D The steps after step S303 also include forming a second source-drain material layer on the first source-drain sublayer 41 , and patterning the second source-drain material layer to form a second source-drain sublayer 42 .

[0077] See also Figure 3E A passivation layer 70 is formed on the second source-drain sublayer 42, and the array substrate is patterned to form a first via hole 81 and a second via hole 82. The first via hole 81 penetrates the passivation layer 70 and the gate insulating layer 60 and exposes the second gate sublayer 22; the second via hole 82 penetrates the passivation layer 70 and exposes the second source-drain sublayer 42. Conductive materials are deposited in the first via hole 81 and the second via hole 82 to form a connecting column.

[0078] The present application also provides a display panel, which includes the above-mentioned array substrate.

[0079] In this embodiment, the display panel can be used in any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0080] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0081] The above is a detailed introduction to an array substrate and its manufacturing method, and a display panel provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A gate layer is disposed on the substrate, the gate layer comprises a first gate sublayer and a second gate sublayer which are stacked, and the second gate sublayer is located on a side of the first gate sublayer away from the substrate; An active layer, disposed on a side of the gate layer away from the substrate; The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the second gate sublayer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the second gate sublayer on the substrate, and the melting point of the first gate sublayer is higher than the melting point of the second gate sublayer; the array substrate also includes a source-drain layer arranged on the side of the active layer away from the substrate, the source-drain layer includes a first source-drain sublayer and a second source-drain sublayer stacked, and the second source-drain sublayer is located on the side of the first source-drain sublayer away from the substrate; the orthographic projection of the first source-drain sublayer on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, and the edge of the first source-drain sublayer does not exceed the edge of the active layer, and the orthographic projection of the second source-drain sublayer on the substrate at least partially overlaps with the orthographic projection of the first source-drain sublayer on the substrate; The melting point of the first source-drain sublayer is higher than the melting point of the second source-drain sublayer.

2. The array substrate according to claim 1, characterized in that: The resistivity of the second source-drain sublayer is lower than the resistivity of the first source-drain sublayer.

3. The array substrate according to claim 1, characterized in that: The array substrate further includes a doping layer disposed between the active layer and the first source-drain sublayer, and an orthographic projection of the doping layer on the substrate is located within an orthographic projection of the first source-drain sublayer on the substrate.

4. The array substrate according to claim 1, characterized in that: The array substrate further comprises a gate insulating layer disposed between the gate layer and the active layer, a passivation layer disposed on a side of the source and drain electrode layer away from the substrate, a first via hole and a second via hole; The first via hole penetrates the passivation layer and the gate insulating layer and exposes the second gate sublayer; the second via hole penetrates the passivation layer and exposes the second source and drain sublayer.

5. The array substrate according to claim 1, characterized in that: At least part of the second source-drain sublayer is arranged in the same layer as the active layer, and one end of the second source-drain sublayer close to the active layer contacts a surface of the first source-drain sublayer facing away from the substrate.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The resistivity of the second gate sublayer is less than the resistivity of the first gate sublayer.

7. A method for manufacturing an array substrate, characterized in that: include: A first gate material layer and a second gate material layer are sequentially formed on a substrate, and patterned so that the first gate material layer forms a first gate sublayer and the second gate material layer forms a second gate sublayer, an orthographic projection of the second gate sublayer on the substrate is located within an orthographic projection of the first gate sublayer on the substrate, and a melting point of the first gate sublayer is higher than a melting point of the second gate sublayer; forming a gate insulating layer on the substrate, wherein the gate insulating layer covers the first gate sublayer and the second gate sublayer; At least an active material layer is formed on the gate insulating layer, the active material layer is patterned to form an active layer, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate sublayer on the substrate, and the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the second gate sublayer on the substrate; Wherein, at least an active material layer is formed on the gate insulating layer, and the step of patterning the active material layer to form an active layer comprises: Sequentially forming the active material layer and the first source and drain material layer on the gate insulating layer; Using a same photomask to pattern the active material layer and the first source-drain material layer to form the active layer and the first source-drain sublayer; The active layer is processed by a preset process to crystallize the active layer.

8. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 6.

Images