A method for separating an SOI wafer chip

Abstract

The present invention discloses a method for separating an SOI wafer chip, comprising the following steps: preparing a strain gauge structure using an SOI wafer by a conventional method, plating an anti-corrosion protective layer on the surface of the electrodes of the strain gauge, etching the intermediate silicon oxide layer of the SOI wafer, removing the substrate silicon, and separating to obtain the chip. The method for separating an SOI wafer chip of the present invention establishes a "sidewall protective layer Si 3 N 4 -top protective layer corrosion-resistant metal-bottom protective layer SiO 2 " structure, that is, a "Si 3 N 4 -etch-resistant material-SiO 2 " structure on the chip, which can significantly improve the chip separation yield, has universality, is also applicable to other devices prepared on the SOI wafer, and has a good application prospect.

Description

Technical Field

[0001] The present invention relates to the field of MEMS semiconductor pressure sensors, and specifically, to a method for separating SOI wafer chips. Background Art

[0002] The piezoresistive effect refers to the phenomenon that the resistance of a material changes after deformation. Since the discovery of the piezoresistive effect in semiconductors, semiconductor pressure sensors have developed rapidly. Semiconductor pressure sensors have the advantages of small size, high sensitivity coefficient, and small mechanical hysteresis. The thinner the diaphragm of a semiconductor pressure sensor, the greater the deflection and the higher the detection sensitivity. The strain gauge prepared based on an SOI wafer has an ultra-thin thickness (only a few micrometers to dozens of micrometers), and the ultra-thin thickness ensures higher sensitivity. The insulation layer isolation of the SOI wafer enables it to work at higher temperatures.

[0003] After the chip is fabricated, it is necessary to separate the batch-fabricated chips. However, the ultra-thin thickness of the strain gauge makes its separation difficult. The currently commonly used separation method is as follows: A layer of adhesive (which plays the role of adhesion and chip protection) is coated on the surface of the auxiliary wafer, the front side of the wafer on which the chips have been fabricated is attached to the auxiliary silicon wafer, and then the silicon substrate is wet-etched to the silicon oxide layer of the SOI wafer. This method has a relatively complex process, and due to the high viscosity and poor fluidity of the adhesive, there are gaps between some chips and the adhesive, resulting in the etching solution corroding the aluminum electrodes during wet etching, reducing the chip yield. Summary of the Invention

[0004] Aiming at the problems existing in the above-mentioned prior art, the present invention proposes a method for separating SOI wafer chips, which can separate the chips more effectively and quickly, and improve the separation yield of the chips.

[0005] The present invention provides a method for separating SOI wafer chips, including the following steps:

[0006] S1. Strain gauge preparation: Prepare a strain gauge using the prepared SOI wafer by a conventional method;

[0007] The SOI wafer includes a substrate body silicon 1, a silicon dioxide intermediate layer 2, and a top silicon 3 that are tightly combined;

[0008] The strain gauge includes a bottom SOI wafer, a sidewall protection layer 5, a functional layer 4 filled between the SOI wafer and the sidewall protection layer 5, and an electrode 6 with good contact that penetrates the sidewall protection layer 5 and the functional layer 4. The sidewall protection layer 5 is tightly combined with the silicon dioxide intermediate layer 2 of the SOI wafer to form a closed space structure. The top silicon 3 of the SOI wafer is located inside the closed space. The functional layer 4 is located above the top silicon 3 of the SOI wafer. Both ends of the electrode 6 are connected to the functional layer 4 and the outside respectively. The height of the sidewall protection layer (5) is greater than 5um;

[0009] S2. Coat an anti-corrosion protection layer on the surface of the electrode of the strain gauge;

[0010] S3. Etch the silicon dioxide intermediate layer 2 of the SOI wafer to remove the substrate silicon 1 and separate the chip.

[0011] In some embodiments, the top silicon 3 is single-crystalline silicon or polycrystalline silicon.

[0012] In some embodiments, the sidewall protection layer 5 is silicon nitride, the thickness of the silicon nitride is not less than 10nm, and the silicon nitride is grown by an LPCVD or ALD device;

[0013] Preferably, the thickness of the silicon nitride is not less than 30 - 200nm.

[0014] In some embodiments, the electrode 6 is made of an aluminum-silicon alloy material, and the aluminum-silicon alloy forms an excellent ohmic contact with the functional layer 4 after high-temperature alloying.

[0015] In some embodiments, the specific steps of coating the anti-corrosion protection layer on the electrode surface in step S3 are as follows:

[0016] 1) Spin coating of the protection layer: Use a spin coater and developer to uniformly cover the entire wafer surface with photoresist according to the steps of "coating - standing - spin coating";

[0017] The "coating" is to use a common spin coater and developer to spray the photoresist multiple times or pour the photoresist manually to cover the entire wafer surface;

[0018] The "standing" is to place the wafer on the spin coater and developer for a period of time so that the photoresist can penetrate into each deep trench;

[0019] The "spin coating" is to rotate the device according to the program settings after standing, and at this time the photoresist can be uniformly covered on the entire surface;

[0020] 2) Perform exposure and development to remove the photoresist at the electrode;

[0021] 3) A corrosion-resistant metal layer is plated on the electrode surface, and then the excess metal outside the electrode is ultrasonically peeled off.

[0022] Preferably, the protective layer in the above step 1) is an aluminum protective layer.

[0023] At this time, the four sides of the chip are protected by the etching-resistant material "Si 3 N 4 -etching-resistant material-SiO 2 ", and the chip is comprehensively protected.

[0024] In some embodiments, the material of the corrosion-resistant metal layer is any one of Pt, Au, and Cr.

[0025] In some embodiments, the thickness of the corrosion-resistant metal layer is not less than 50 nm;

[0026] Preferably, the thickness of the corrosion-resistant metal layer is 100 nm to 1 μm.

[0027] In some embodiments, the method of spin-coating the protective layer in step 1) is to evenly spray photoresist onto the wafer surface using a spin coater.

[0028] The spin coater is more suitable for use in the case of having deep grooves.

[0029] In some embodiments, the step of separating the chip in step S3 is specifically as follows:

[0030] 1) The sample plated with the corrosion-resistant protective layer is put into a BOE solution for wet etching. The etching time t = h / v (time = maximum length of the pattern / etching rate) is determined according to the etching rate, and a certain over-etching time is added on this basis to ensure that the intermediate silicon oxide layer (2) of the SOI wafer is completely etched and the substrate silicon (1) is removed;

[0031] 2) After the etching is completed, it is washed with a large amount of pure water. After being washed clean, it can be sorted manually or by equipment for subsequent testing and packaging.

[0032] In some embodiments, the thickness of the silicon dioxide intermediate layer is 0.5 μm to 2 μm.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] 1) The SOI wafer chip separation method provided by the present invention can significantly improve the chip separation yield by establishing a "Si 3 N 4 -etching-resistant material-SiO 2 " protective layer on the chip;

[0035] 2) The chips are obtained by separating through the method of etching the silicon dioxide of the SOI wafer from the front side, and the silicon substrate can be completely retained after the chips are separated. The retained silicon substrate is ground and polished and can be used for other purposes, reducing resource waste;

[0036] 3) The product prepared by the method of the present invention has deep grooves, and the depth of the grooves is more than 5 um. The depth of the grooves is the height of the sidewall protection layer (5). Ordinary spin coating methods are not applicable to this product. The method of the present invention is not only applicable to strain gauges, but also applicable to other devices separated on the SOI wafer, having universality. Description of the Drawings

[0037] Figure 1 is a schematic structural diagram of the chip obtained by separating through the method of the present invention;

[0038] Figure 2 is a schematic structural diagram of the SOI wafer of the present invention;

[0039] Figure 3 is a schematic structural diagram of the strain gauge prepared on the SOI wafer of the present invention;

[0040] Figure 4 is a schematic structural diagram of the strain gauge after the electrodes are protected according to the present invention;

[0041] The reference numerals in the above drawings are as follows:

[0042] 1 - bulk silicon substrate; 2 - silicon dioxide intermediate layer; 3 - top silicon; 4 - functional layer; 5 - sidewall protection layer; 6 - electrode; 7 - anti-corrosion protection layer. Detailed Embodiments

[0043] The following further describes the specific embodiments of the technical solution of this specification in combination with the drawings through specific examples. These examples are for a detailed description of the technical solution and not for limiting the technical solution. Based on the examples in this specification, all other examples obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this specification.

[0044] Embodiment 1

[0045] The present invention provides a method for separating SOI wafer chips, including the following steps:

[0046] S1. Prepare the strain gauge structure, and prepare the strain gauge structure using the SOI wafer described in S1 according to the conventional method; the specific preparation method of the strain gauge structure is prepared by the generally known methods in the art, and the specific processes, parameters, etc. will not be specifically described. The structure of the SOI wafer adopted in this solution is as Figure 2As shown, the SOI wafer includes a tightly bonded substrate bulk silicon 1, a silicon dioxide intermediate layer 2, and a top silicon layer 3, and the top silicon layer 3 is single-crystalline silicon;

[0047] The strain gauge structure is as Figure 3 shown, and includes a bottom SOI wafer, an outer silicon nitride layer with a thickness of 20nm5, a functional layer 4 filled between the SOI wafer and the silicon nitride layer 5, and an electrode 6 that penetrates the silicon nitride layer 5 and has good contact with the functional layer 4. The electrode 6 is made of an aluminum-silicon alloy material, and the aluminum-silicon alloy forms an excellent ohmic contact with the functional layer 4 after high-temperature alloying. The silicon nitride layer 5 is tightly bonded to the silicon dioxide intermediate layer 2 of the SOI wafer to form a closed space structure. The top silicon of the SOI wafer is located inside the closed space. The functional layer 4 is above the top silicon 3 of the SOI wafer. Both ends of the electrode 6 are connected to the functional layer 4 and the outside respectively. The height of the sidewall protection layer 5 is 10um;

[0048] S2. Coat the surface of the electrode 6 with an anti-corrosion protection layer:

[0049] 1) Aluminum protection layer lithography: Use a spin coater and developer equipment to evenly cover the entire wafer surface with photoresist according to the steps of "coating - standing - spin coating".

[0050] "Coating" is to use a common spin coater and developer to coat the photoresist multiple times or to pour the photoresist manually to cover the entire wafer surface;

[0051] "Standing" is to place the wafer on the spin coater and developer for a period of time so that the photoresist can penetrate into each trench;

[0052] "Spin coating" is after the standing is completed, the equipment runs according to the program settings, and at this time the photoresist can be evenly covered on the entire surface;

[0053] 2) Perform exposure and development to remove the photoresist on the electrode 6;

[0054] 3) Coat an anti-corrosion metal layer on the surface of the electrode 6. The material of the anti-corrosion metal layer is Pt and the thickness is 100nm. Then ultrasonically peel off the excess metal outside the electrode.

[0055] At this time, the four sides of the chip are protected by an etching-resistant material "Si 3 N 4 -Pt-SiO 2 ", and the chip is fully protected, as Figure 4 shown.

[0056] S3. Etch the silicon dioxide layer of the SOI wafer to separate the chip:

[0057] 1) Place the sample with the anti-corrosion protective layer into the BOE solution for wet etching. Determine the etching time \(t = h / v\) (time = maximum length of the pattern / etching rate), and based on this, add a certain over-etching time to ensure that the underlying silicon is completely etched;

[0058] 2) After etching is completed, clean it thoroughly with a large amount of pure water to obtain a chip, and the chip structure is as Figure 1 shown.

[0059] Example 2

[0060] The present invention provides a method for separating an SOI wafer chip, including the following steps:

[0061] S1. Prepare a strain gauge structure, and use an SOI wafer to prepare a strain gauge structure by a conventional method;

[0062] The structure of the SOI wafer is as Figure 2 shown. The SOI wafer includes a tightly bonded substrate body silicon (1), a silicon dioxide intermediate layer 2, and a top silicon layer 3. The top silicon layer 3 is single-crystalline silicon or polycrystalline silicon;

[0063] The strain gauge structure is as Figure 3 shown, including an underlying SOI wafer, an outer silicon nitride layer with a thickness of 50nm5, a functional layer 4 filled between the SOI wafer and the silicon nitride layer 5, and an electrode 6 that penetrates the silicon nitride layer 5 and is in good contact with the functional layer 4. The electrode 6 is made of an aluminum-silicon alloy material, and after high-temperature alloying, the aluminum-silicon alloy forms an excellent ohmic contact with the functional layer 4. The silicon nitride layer 5 is tightly bonded to the silicon dioxide intermediate layer 2 of the SOI wafer to form a closed space structure. The top silicon of the SOI wafer is located inside the closed space. The functional layer 4 is above the top silicon layer 3 of the SOI wafer. Both ends of the electrode 6 are connected to the functional layer 4 and the outside respectively. The height of the sidewall protective layer 5 is 20um;

[0064] S2. Deposit an anti-corrosion protective layer on the surface of the electrode 6:

[0065] 1) Aluminum protective layer lithography: Use a spin coater to evenly spray photoresist on the wafer surface. The spin coater is more suitable for cases with deep grooves

[0066] 2) Perform exposure and development to remove the photoresist on the electrode 6;

[0067] 3) Deposit an anti-corrosion metal layer on the surface of the electrode 6. The material of the anti-corrosion metal layer is Au, and the thickness is 150nm. Then ultrasonically strip off the excess metal outside the electrode.

[0068] At this time, the four sides of the chip are made of an etching-resistant material "Si 3 N 4-Au - SiO 2 ” Protection, the chip has obtained comprehensive protection, such as Figure 4 shown.

[0069] S3. Etch the silicon oxide layer of the SOI wafer to separate the chip:

[0070] 1) Put the sample with the anti - corrosion protection layer into the BOE solution for wet etching. Determine the etching time t = h / v (time = maximum length of the pattern / etching rate), and add a certain over - etching time on this basis to ensure that the underlying silicon is completely etched;

[0071] 2) After etching, wash it clean with a large amount of pure water to obtain the chip. The chip structure is as Figure 1 shown.

[0072] Grind and polish the remaining silicon substrate. The polished substrate can be used for other purposes, reducing resource waste.

[0073] The yield of the strain gauge prepared by the present invention is increased from 60% to over 90%, greatly improving the production yield.

[0074] The preparation method and separation method of the chip protection layer (Si 3 N 4 - etching - resistant material - SiO 2 ) provided by the present invention are not only applicable to the strain gauge mentioned in the text, but also applicable to other devices separated by a similar method on the SOI wafer.

[0075] Although the embodiments of the present specification have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present specification. The scope of the present specification is defined by the appended claims and their equivalents.

Claims

1. A method for separating an SOI wafer chip, characterized in that, it includes the following steps: S1. Strain gauge preparation, using an SOI wafer to prepare a strain gauge; The SOI wafer includes a substrate bulk silicon (1), a silicon dioxide intermediate layer (2) and a top silicon layer (3) that are tightly bonded; The strain gauge includes a bottom SOI wafer, a sidewall protection layer (5), a functional layer (4) filled between the SOI wafer and the sidewall protection layer (5), and an electrode (6) with good contact that penetrates the sidewall protection layer (5) and the functional layer (4). The sidewall protection layer (5) is tightly bonded to the silicon dioxide intermediate layer (2) of the SOI wafer to form a closed space structure. The top silicon layer (3) of the SOI wafer is located inside the closed space. The functional layer (4) is located above the top silicon layer (3) of the SOI wafer. Both ends of the electrode (6) are connected to the functional layer (4) and the outside respectively. The height of the sidewall protection layer (5) is greater than 5um; S2. Deposit an anti-corrosion protection layer (7) on the surface of the electrode (6) of the strain gauge; S3. Corrode the silicon dioxide intermediate layer (2) of the SOI wafer to remove the substrate silicon (1) and separate the chip.

2. The method for separating an SOI wafer chip according to claim 1, characterized in that, the top silicon layer (3) is single crystal silicon or polycrystalline silicon.

3. The method for separating an SOI wafer chip according to claim 1, characterized in that, the sidewall protection layer (5) is silicon nitride, the thickness of the silicon nitride is not less than 10nm, and the silicon nitride is grown by an LPCVD or ALD device.

4. The method for separating an SOI wafer chip according to claim 1, characterized in that, the electrode (6) is made of an aluminum-silicon alloy material, and the aluminum-silicon alloy forms an ohmic contact with the functional layer (4) after high-temperature alloying.

5. The method for separating an SOI wafer chip according to claim 1, characterized in that, the step of depositing an anti-corrosion protection layer on the surface of the electrode (6) in step S3 specifically includes the following steps: 1) Protective layer spin coating: Use a spin coater and developer to make the photoresist uniformly cover the entire wafer surface according to the steps of "coating - standing - spin coating"; The "coating" is to use a common spin coater and developer to spray the photoresist multiple times or pour the photoresist manually to cover the entire wafer surface; The "standing" is to place the wafer on the spin coater and developer for a period of time so that the photoresist can penetrate into each deep trench; The "spin coating" is after the standing is completed, the device rotates according to the program setting, and at this time the photoresist can uniformly cover the entire surface; 2) Perform exposure and development to remove the photoresist at the electrode (6); 3) Deposit an anti-corrosion metal layer on the surface of the electrode (6), and then ultrasonically strip off the excess metal outside the electrode.

6. The method for separating an SOI wafer chip according to claim 5, characterized in that, the protective layer in step 1) is an aluminum protective layer.

7. The method for separating an SOI wafer chip according to claim 5, characterized in that, the material of the anti-corrosion metal layer in step 3) is any one of Pt, Au and Cr. ​ 8. The separation method of the SOI wafer chip according to claim 7, characterized in that, the thickness of the anti-corrosion metal layer is not less than 50 nm.

9. The separation method of the SOI wafer chip according to claim 1, characterized in that, the method for separating the chip in step S3 is as follows: 1) Put the sample coated with the anti-corrosion protection layer into the BOE solution for wet etching, so that the intermediate layer silicon oxide of the SOI wafer is completely etched; 2) After the etching is completed, clean it with a large amount of pure water and sort to obtain the chip.

10. The separation method of the SOI wafer chip according to claim 1, characterized in that, the thickness of the silicon oxide intermediate layer is 0.5 um to 2 um.

11. The separation method of the SOI wafer chip according to claim 3, characterized in that, the thickness of the silicon nitride is 30 nm - 200 nm.

12. The separation method of the SOI wafer chip according to claim 8, characterized in that, the thickness of the anti-corrosion metal layer is 100 nm - 1 um.

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