Method for improving the ability of a PCB to resist near-field interference

Abstract

The application discloses a method for improving the anti-near electric field interference capability of a PCB, and respectively calculates the induced interference voltage of a first scheme and a second scheme, wherein the positive overlapping area of the power layer and the ground layer is different in different schemes; the method for calculating the induced interference voltage comprises the following steps: directly measuring the impedance between the power layer and the ground layer, selecting the parasitic capacitance impedance between the power layer and the adjacent copper plate or the parasitic capacitance impedance between the ground layer and the adjacent copper plate as the reference parasitic capacitance impedance, calculating the ratio of each parasitic capacitance impedance to the reference parasitic capacitance impedance based on an equivalent circuit; calculating the induced interference voltage based on the equivalent circuit and the ratio of the parasitic capacitance impedance; calculating the induced voltage amplitude ratio H of the first scheme and the second scheme, determining whether the ratio is true, if yes, the second scheme is adopted, and if not, the first scheme is adopted. The application proposes adjusting the layout scheme of the PCB power / ground layer to improve the anti-interference capability of the PCB, and quickly determines the best scheme through the above comparison method.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of PCB design, and more particularly to a method for improving the anti-near electric field interference capability of a PCB. BACKGROUND

[0002] When the power electronic system is working normally, the power switch tube inside the system will frequently turn on and off, generating extremely steep voltage rising or falling edges, forming a common-mode interference source with rich frequency components. The common-mode current generated by the common-mode interference source will flow through the parasitic capacitance in the form of displacement current in space, forming near electric field interference. If the PCB in the system is on the main transmission path of the displacement current, a larger interference voltage will be induced between the power supply layer and the ground layer in a large area, affecting the normal function of various devices on the PCB, and in severe cases, even causing permanent failure of the devices. Therefore, improving the anti-interference capability of the PCB itself to the near electric field is helpful to improve the reliability of the power electronic system, reduce the probability of safety accidents, and has important research significance and practical value.

[0003] Considering that three basic elements are needed for electromagnetic interference to occur: interference source, interference path, and sensitive equipment, most current researches mainly focus on the modeling and suppression of interference sources and interference paths, and lack in-depth research on sensitive equipment. Among them, the PCB near the interference source and its core chip are the main disturbed objects of electromagnetic interference of the main circuit commutation, and are one of the most vulnerable sensitive devices. The current means to solve electromagnetic interference generally considers the characteristics of the interference source or interference path in the system, and does not consider the disturbance size of the sensitive equipment itself. From the perspective of the disturbance of the sensitive equipment, improving the electromagnetic anti-interference capability of the PCB is still in a relatively new field and needs to be further researched. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a method for improving the anti-near electric field interference capability of a PCB, which aims to improve the electromagnetic anti-interference capability of the PCB from the perspective of the disturbance of the sensitive equipment itself.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present application, a method for improving the anti-near electric field interference capability of a PCB is provided, the PCB is placed between a copper plate A and a copper plate B and includes a power supply layer P near the copper plate A and a ground layer G near the copper plate B, and the method comprises:

[0006] Under the condition of a specific load impedance and an interference source U S , the induced interference voltage U PG of the first scheme and the induced interference voltage U PG ' of the second scheme are calculated respectively, and the positive overlap area of the power supply layer P and the ground layer G is different in the first scheme and the second scheme.

[0007] The method for calculating the induced interference voltage comprises:

[0008] constructing an equivalent circuit of the disturbed PCB;

[0009] directly measuring the impedance between the power layer P and the ground layer G, selecting the parasitic capacitance impedance between the power layer P and the copper plate A or the parasitic capacitance impedance between the ground layer G and the copper plate B as the reference parasitic capacitance impedance, calculating the ratio of each parasitic capacitance impedance to the reference parasitic capacitance impedance based on the equivalent circuit, and obtaining the relationship coefficient between the parasitic capacitance impedances;

[0010] calculating the induced interference voltage based on the equivalent circuit and the relationship coefficient between the parasitic capacitance impedances;

[0011] calculating the amplitude ratio determining whether the following equation is true within the frequency domain range [f L ,f H ] and, if yes, adopting the second scheme, and if no, adopting the first scheme. The relationship coefficient between the parasitic capacitance impedances is obtained by the following process in one of the embodiments.

[0012] The process for obtaining the relationship coefficient between the parasitic capacitance impedances comprises:

[0013] defining that the copper plate A and the ground layer G constitute port 1, and the copper plate B and the power layer P constitute port 2, measuring the reflection coefficient S 11 of port 1, the reverse transmission coefficient S 12 of port 2 to port 1, the forward transmission coefficient S 21 of port 1 to port 2, and the reflection coefficient S 22 of port 2;

[0014] calculating the input admittance Y 11 of port 1 when port 2 is short-circuited, the transfer admittance Y 12 of port 1 to port 2 when port 1 is short-circuited, the transfer admittance Y 21 of port 2 to port 1 when port 2 is short-circuited, and the input admittance Y 22 of port 2 when port 1 is short-circuited based on the equivalent circuit and the coefficients S 11 , S 12 , S 21 , and S 22 ;

[0015] constructing the parasitic capacitance admittance based on the equivalent circuit and the admittances Y 11 , Y 12 , Y 21 , and Y 22 ;

[0016] constructing the relationship coefficient between the parasitic capacitance impedances based on the parasitic capacitance admittance.

[0017] In one of the embodiments, in the PCB disturbed equivalent circuit, it includes:

[0018] The interference source U between copper plate A and copper plate B S ;

[0019] The parallel parasitic capacitance C0 and load impedance Z between the power layer P and the ground layer G L ;

[0020] The parasitic capacitance C1 between the power layer P and the copper plate A;

[0021] The parasitic capacitance C2 between the power layer P and the copper plate B;

[0022] The parasitic capacitance C3 between the ground layer G and the copper plate A;

[0023] The parasitic capacitance C4 between the ground layer G and the copper plate B.

[0024] In one of the embodiments, based on the equivalent circuit and the coefficients S 11 , S 12 , S 21 , S 22 The formula for calculating the admittance Y 11 , Y 12 , Y 21 and Y 22 is:

[0025]

[0026] Wherein, Z0 is the impedance of the parasitic capacitance C0;

[0027] Based on the equivalent circuit and the admittance Y 11 , Y 12 , Y 21 and Y 22 The relationship coefficient between the parasitic capacitance impedance is calculated, including,

[0028] First, calculate the admittance Y1, Y2, Y3 and Y4 of the parasitic capacitances C1~C4, and the calculation formula is:

[0029]

[0030] Wherein, Y L is the inverse of the impedance Z0 / / Z L ;

[0031] According to the corresponding relationship between the admittance and the impedance Y i =1 / Z i , based on the admittance Y1, Y2, Y3 and Y4, the relationship coefficient between the parasitic capacitance impedance is constructed, wherein Z1, Z2, Z3 and Z4 are the impedances of the parasitic capacitances C1, C2, C3 and C4 respectively.

[0032] In one embodiment, the coefficient S 11 S 12 S 21 S 22 The measurements were obtained using a vector network analyzer.

[0033] In one embodiment,

[0034] The amplitude expression for each scheme is constructed based on the induced interference voltage, where the amplitude |U PG |=|m|·|n|·|U S |Amplitude|U PG '|=|m'|·|n'|·|U S |, m and m' are linearly related to the impedance between the power layer P and the ground layer G measured in the first and second schemes, respectively, and n and n' are inverse proportional functions of the reference parasitic capacitance impedance constructed based on the relationship coefficient in the first and second schemes, respectively.

[0035] determination Whether it is valid or not, specifically, is determined by judgment. Whether it is valid or not.

[0036] In one embodiment, f L =150kHz, f H =30MHz.

[0037] In one embodiment, the length of the copper plate is greater than or equal to three times the length of the PCB, and the width of the copper plate is greater than or equal to three times the width of the PCB.

[0038] In one embodiment, the near-electric field interference source U is obtained by simulating or measuring the voltage between the two terminals of the power current flowing through the lower switch in the electronic device. s .

[0039] In one embodiment, the first option is that the power layer and ground layer of the PCB are arranged in a completely non-overlapping manner, and the second option is that the power layer and ground layer of the PCB are arranged in a completely overlapping or partially overlapping manner.

[0040] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0041] The general principle of the present application is to design a PCB with the purpose of reducing electromagnetic interference suffered by the PCB, and specifically to determine the preferred design scheme by comparing the induced interference voltages of different schemes. However, there are many parasitic capacitances inside the PCB, and the impedances corresponding to many spatial parasitic capacitances cannot be measured, so it is difficult to directly calculate the induced interference voltages of each scheme by using traditional formulas. Therefore, for the design of a PCB, it is currently not possible to directly determine the anti-interference performance by calculating the induced interference voltage, which is also the main obstacle that has not been proposed by anyone to enhance the anti-interference ability from the design of the PCB itself.

[0042] Based on this, the innovation of the present application is to find that changing the layout of the power / ground layer can adjust the anti-interference ability of the PCB and propose a comparison method for the anti-interference ability of the PCB after changing the layout of the power / ground layer. On the one hand, for the impedance between the power layer P and the ground layer G that can be directly measured, the impedance is directly measured by using existing tools, and for the spatial parasitic capacitance impedance that cannot be measured, the problem of not being able to directly measure is avoided, and a suitable reference parasitic capacitance impedance is first determined, and the ratio of other parasitic capacitance impedances to the reference parasitic capacitance impedance is calculated as the parasitic capacitance impedance relationship coefficient. Then, the induced interference voltage can be expressed as a function only related to the reference parasitic capacitance impedance, at this time, the induced interference voltage amplitudes in different schemes can be expressed as |U PG |=|m|·|n|·|U S |and |U PG ’|=|m’|·|n’|·|U S |,the amplitude ratio H is calculated where m and m' are linearly related to the impedance between the power layer P and the ground layer G measured in the first scheme and the second scheme, respectively, so the ratio |m| / |m'| is related to the impedance between the power layer and the ground layer and can be directly calculated, n and n' are inverse proportional functions of the reference parasitic capacitance impedance constructed based on the relationship coefficient in the first scheme and the second scheme, respectively, so |n'| / |n| eliminates the reference parasitic capacitance impedance, and its size is only related to the relationship coefficient between the spatial parasitic capacitance impedance, and is independent of the frequency f, so the amplitude ratio H of the two schemes can be expressed as a function only related to the frequency, and thus U s The amplitude and the amplitude ratio are combined, and then the frequency integral comparison is performed, so that it can be determined which scheme has a smaller induced interference voltage, and thus the smaller one is selected as the design scheme of the PCB to enhance the electromagnetic anti-interference ability of the PCB. The present application can compare the electromagnetic anti-interference abilities of different schemes without directly measuring the spatial parasitic capacitance impedances, so that the electromagnetic anti-interference ability of the PCB can be improved from the perspective of the interference suffered by the sensitive device. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1Copper plate and PCB swing diagram for spatial parasitic capacitance impedance measurement of an embodiment;

[0044] Figure 2 Flow chart of steps of a method for improving the ability of a PCB to resist near field interference of an embodiment;

[0045] Figure 3 Flow chart of steps of calculating the relationship coefficient between parasitic capacitance impedances of an embodiment;

[0046] Figure 4 Spatial parasitic capacitance diagram of a copper plate to a PCB of an embodiment;

[0047] Figure 5 PCB disturbed equivalent circuit diagram of an embodiment considering the characteristics of the interference source;

[0048] Figure 6 PCB power / ground layer arrangement diagram of a new scheme of an embodiment;

[0049] Figure 7 PCB power / ground layer arrangement diagram of a conventional scheme of an embodiment;

[0050] Figure 8(a) is a frequency domain variation trend diagram of and of an embodiment;

[0051] Figure 8(b) is a variation trend diagram of the induced interference voltage of an interference source U S with frequency of an embodiment;

[0052] Figure 8(c) is a schematic diagram of a comparison of the induced interference voltage magnitude in the frequency domain of an embodiment;

[0053] Figure 9 Waveform diagram of the induced interference voltage measured using a conventional layout scheme of an embodiment;

[0054] Figure 10 Waveform diagram of the induced interference voltage measured after using a new scheme layout of an embodiment. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0056] As Figure 1As shown is a copper plate and a PCB swing diagram in an embodiment, the PCB is placed in the middle of two copper plates, the distance between the copper plate and the PCB should be much greater than the thickness of the PCB or the copper plate, but less than the length or width of the copper plate, the two copper plates are opposite to the plane of the power layer of the PCB, the length and width of the copper plate should be greater than or equal to three times the length and width of the PCB respectively, and the thickness of the copper plate should be much smaller than the length and width of the copper plate, the purpose of this arrangement is to reduce the influence of edge effect as much as possible under the premise of considering the simple and easy-to-operate scheme.

[0057] The present application finds that adjusting the opposite overlap area between the power layer P and the ground layer G in the PCB can change the anti-interference ability of the PCB, and further provides a comparison method for the anti-interference ability of PCBs with different opposite overlap areas, through which a more preferred power layer / ground layer layout scheme can be selected to reduce electromagnetic interference.

[0058] As shown in the figure, Figure 2 As shown is a step flow chart of the method for improving the anti-near electric field interference ability of the PCB in an embodiment, mainly including the following steps:

[0059] Step S100: Under the condition of a specific load impedance and an interference source U S , the induced interference voltage U PG of the first scheme and the induced interference voltage U PG ' of the second scheme are calculated respectively.

[0060] Specifically, for each scheme, the method for calculating the induced interference voltage includes:

[0061] Step S110: Construct an equivalent circuit of the disturbed PCB.

[0062] As shown in the figure, Figure 4 As shown is the space parasitic capacitance distribution between the copper plate and the power / ground layer of the PCB in an embodiment, which mainly includes the interference source U S between the copper plate A and the copper plate B; the parallel parasitic capacitance C0 and the load impedance Z L between the power layer P and the ground layer G; the parasitic capacitance C1 between the power layer P and the copper plate A; the parasitic capacitance C2 between the power layer P and the copper plate B; the parasitic capacitance C3 between the ground layer G and the copper plate A; the parasitic capacitance C4 between the ground layer G and the copper plate B, according to the analysis of the capacitance distribution, the disturbed equivalent circuit can be constructed, as shown in the figure. Figure 5

[0063] ​Step S120: Directly measure the impedance between the power layer P and the ground layer G, select the parasitic capacitance impedance between the power layer P and the copper plate A or the parasitic capacitance impedance between the ground layer G and the copper plate B as the reference parasitic capacitance impedance, calculate the ratio of each other parasitic capacitance impedance to the reference parasitic capacitance impedance based on the equivalent circuit, and obtain the relationship coefficient between the parasitic capacitance impedances.

[0064] Step S120 mainly consists of two steps:

[0065] Step S121: Directly measure the impedance between the power layer P and the ground layer G.

[0066] like Figure 4 As shown, a load and parasitic capacitance C0 are connected in parallel between power layer P and ground layer G. The impedance between power layer P and ground layer G is the parallel load impedance Z. L The induced impedance Z0 corresponding to the parasitic capacitance C0, that is, the impedance between the power layer P and the ground layer G, can be expressed as Z. L ||Z0, this part of the impedance can be directly measured, for example, by using an impedance analyzer.

[0067] Step S122: Select the parasitic capacitance impedance between the power layer P and the copper plate A or the parasitic capacitance impedance between the ground layer G and the copper plate B as the reference parasitic capacitance impedance. Calculate the ratio of each other parasitic capacitance impedance to the reference parasitic capacitance impedance based on the equivalent circuit to obtain the relationship coefficient between the parasitic capacitance impedances.

[0068] Among them, besides impedance Z L While Z0 can be directly measured, the impedances of other parasitic capacitances are generally not directly measurable, including Z1 corresponding to parasitic capacitance C1, Z2 corresponding to parasitic capacitance C2, Z3 corresponding to parasitic capacitance C3, and Z4 corresponding to parasitic capacitance C4. By analyzing the PCB spatial structure, impedance Z1 or Z4 can be selected as the reference parasitic capacitance impedance. The ratio of other parasitic capacitance impedances to the reference parasitic capacitance impedance can then be calculated as the relationship coefficient between the corresponding parasitic capacitance impedances.

[0069] For example, when impedance Z1 is chosen as the reference parasitic capacitance impedance, the relationship coefficients between Z2 to Z4 and Z1 are calculated as follows:

[0070] For example, when Z4 is selected as the reference parasitic capacitance impedance, the relationship coefficients between Z1 to Z3 and Z4 are calculated respectively.

[0071] In one embodiment, the scattering parameters of the PCB can be measured first. Relevant admittance parameters can be calculated using the scattering parameters and the equivalent circuit. Then, a relationship between the admittance parameters and impedance can be constructed based on the equivalent circuit. The relationship coefficient between the parasitic capacitance and impedance can be calculated based on this relationship. Specifically, as shown... Figure 3 As shown, the process includes the following steps:

[0072] Step A: Define copper plate A and ground plane G as port 1, and copper plate B and power plane P as port 2. Measure the reflection coefficient S of port 1. 11 The reverse transmission coefficient S from port 2 to port 1 12 Forward transmission coefficient S from port 1 to port 2 21 and the reflection coefficient S of port 2 22 .

[0073] Specifically, a vector network analyzer can be used to measure the two-port scattering parameter S between the two copper plates and the PCB. 11 S 12 S 21 and S 22 All four scattering parameters were measured with the two ports matched, meaning the port impedance equals the transmission line impedance. Among them, S... 11 It is the reflection coefficient of port 1, that is, when there is no input voltage at port 2, the reflected voltage of port 1 divided by the incident voltage of port 1; S 12 It is the reverse transfer coefficient from port 2 to port 1, that is, when there is no input voltage at port 1, the output voltage of port 1 divided by the input voltage of port 2; S 21 It is the forward transfer coefficient from port 1 to port 2, that is, the input voltage of port 2 divided by the input voltage of port 1 when there is no input voltage at port 2; S 22 It is the reflection coefficient of port 2, that is, when there is no input voltage at port 1, the reflected voltage of port 2 divided by the incident voltage of port 2.

[0074] Step B: Based on the equivalent circuit and coefficient S 11 S 12 S 21 S 22 Calculate the input admittance Y of port 1 when port 2 is short-circuited. 11 When port 1 is short-circuited, the transfer admittance Y of port 1 to port 2 12 When port 2 is short-circuited, the transfer admittance Y of port 2 to port 1 21 The input admittance Y of port 2 is short-circuited with port 1. 22 .

[0075] Based on the equivalent circuit, the relationship between scattering parameters and admittance is analyzed, and the admittance parameter Y is calculated from the scattering parameters. 11 Y 12 Y21 and Y 22 .

[0076] For example, based on the equivalent circuit of Figure 5 , the scattering parameters S 11 , S 12 , S 21 , S 22 are calculated respectively, and the formulas of Y 11 , Y 12 , Y 21 and Y 22 are as follows:

[0077]

[0078] Step C: Calculate the relationship coefficient between the impedances of the parasitic capacitances based on the equivalent circuit and the admittances Y 11 , Y 12 , Y 21 and Y 22 .

[0079] Through analysis of the equivalent circuit, when port 2 is short-circuited, Y 11 is equal to the current of port 1 divided by the voltage of port 1, Y 21 is equal to the current of port 2 divided by the voltage of port 1; when port 1 is short-circuited, Y 12 is equal to the current of port 1 divided by the voltage of port 2, Y 22 is equal to the current of port 2 divided by the voltage of port 2. Since the relationship formulas of the parasitic capacitance admittances and the admittances Y 11 , Y 12 , Y 21 and Y 22 can be obtained, they are as follows:

[0080]

[0081] wherein Y L is the admittance between the power layer and the ground layer, Y1, Y2, Y3 and Y4 are the admittances of the parasitic capacitances C1, C2, C3 and C4 respectively.

[0082] Combining formula (1) and formula (2), since the internal circuit is a passive network, the transfer admittance is equal, i.e. Y 12 = Y 21 , therefore only three groups of equations in formula (2) are independent, and the specific values of the four parasitic capacitance admittances cannot be solved, but the relationship formula between the parasitic capacitance admittances can be obtained.

[0083] Step D: Construct the relationship coefficient between the impedances of the parasitic capacitances based on the parasitic capacitance admittances.

[0084] According to the corresponding relationship between the parasitic capacitance admittances and the impedances, Yi = 1 / Z i (i = 1, 2, 3, 4), into equation (2), based on the relationship between the parasitic capacitance admittance, the relationship between Z1, Z2, Z3 and Z4 in the parasitic capacitance impedance can be obtained.

[0085] At this time, after obtaining the relationship between Z1, Z2, Z3 and Z4 in the parasitic capacitance impedance, the reference parasitic capacitance impedance is selected, and the ratio of other parasitic capacitance impedance to the reference parasitic capacitance impedance can be calculated, that is, the relationship coefficient between the parasitic capacitance impedances is obtained.

[0086] In this embodiment, when Z4 is taken as the reference capacitance impedance, the relationship coefficients k1, k2 and k3 of other parasitic capacitance impedances to the reference capacitance impedance are as follows:

[0087]

[0088] In this embodiment, the reference parasitic capacitance impedance Z4 is selected, because the impedance of the parasitic capacitance is inversely proportional to the capacitance, and the distance and the overlapping area between the ground layer G and the B copper plate remain unchanged under different schemes, so the size of the parasitic capacitance C4 remains unchanged, that is, the impedance Z4 remains unchanged. k1, k2 and k3 represent the impedance size relationship between the spatial parasitic capacitances, and are all frequency-independent constants, the values of which are only related to the spatial positions of the two copper plates and the PCB, which is conducive to the comparison of the induced voltage amplitudes. Similarly, Z1 can also be selected as the reference capacitance impedance, and Z1 has the same performance as Z4.

[0089] After obtaining the relationship coefficient between the parasitic capacitance impedances, the following is also included:

[0090] Step S130: calculating the induced interference voltage based on the equivalent circuit and the relationship coefficient between the parasitic capacitance impedances.

[0091] Based on the equivalent circuit as shown in Figure 5 , the formula of the induced interference voltage is:

[0092]

[0093] The relationship coefficient between the parasitic capacitance impedances in equation (3) is brought into equation (4), which is converted into:

[0094]

[0095] wherein, for example,

[0096]

[0097] Therefore, equation (6) can be converted into the following equation:

[0098]

[0099] where Z0 / / Z L The value of K can be calculated by the above method and is independent of frequency. Thus, the transformation is beneficial for the comparison of the amplitude of the induced voltage.

[0100] where m = Z0 / / Z L n = K / Z4, the amplitude expression of the induced interference voltage U PG is obtained as follows:

[0101] |U PG | = |m·n·U s | = |m|·|n|·|U s | (8)

[0102] By the same method, the amplitude expression of the induced interference voltage U PG of the second scheme is obtained as follows:

[0103] |U PG ′| = |m′|·|n′|·|U s | (9)

[0104] where the electric field interference source U s can be obtained by simulation or measurement. The interference source refers to the voltage between the collector and the emitter of the insulated gate bipolar transistor (IGBT) in the lower bridge arm of the power electronic converter (for other types of transistors, such as metal oxide semiconductor field effect transistor MOSFET, it refers to the voltage between the drain and the source).

[0105] Step S200: Calculate the amplitude ratio Determine whether the following condition is met in the frequency domain range [f L , f H ]: if yes, the second scheme is adopted, and if no, the first scheme is adopted.

[0106] After obtaining the induced interference voltage of each scheme by step S100, calculate the amplitude ratio

[0107]

[0108] As can be seen from the decomposition of the amplitude expressions of formula (8) and formula (9), the interference source U S is the same in different schemes, and formula (10) can be transformed into:

[0109]

[0110] As analyzed in the foregoing, the reference parasitic capacitance impedance in different schemes is unchanged, ​Wherein, K and K' in each scheme can be calculated by the above step S100 and only related to the size relationship between the spatial parasitic capacitance impedance and the frequency, and m and m' in each scheme can be measured and related to the area of the PCB power / ground layer, the load impedance and the frequency variation, thus, for two schemes, the area of the PCB power / ground layer and the load impedance of each scheme are determined, and the amplitude ratio H can be regarded as a function related to the frequency.

[0111] Then, by multiplying the amplitude ratio with the current interference source U s , and integrating the calculation, the strength of the anti-interference ability of different schemes can be obtained, which is specifically:

[0112] Determine whether the following formula is true in the frequency domain range [f L , f H ], if yes, the second scheme is adopted, and if not, the first scheme is adopted:

[0113]

[0114] In an embodiment, f L = 150 kHz, f H = 30 MHz. The range covers the working frequency range of the PCB.

[0115] In an embodiment, the first scheme can be designed as the power layer and the ground layer of the PCB arranged in a completely non-overlapping manner, as shown in Figure 6 ; and the second scheme can be designed as the power layer and the ground layer of the PCB arranged in a completely overlapping or partially overlapping manner, as shown in Figure 7 . Among them, the second scheme is the current conventional design, and the first scheme is the new design proposed by the present application. At present, there is no design that the power layer and the ground layer are completely staggered, and therefore, through the method of the present application, it can also be determined whether the new scheme is applicable, that is, when the above inequality is true, it means that the new scheme proposed by the present application is applicable under the current scenario, which can further enhance the anti-interference ability of the PCB.

[0116] In an embodiment, for the convenience of comparison, formula (12) can be transformed into formula (13) to determine whether it is true, if yes, the second scheme is adopted, and if not, the first scheme is adopted:

[0117]

[0118] Among them, is only related to the frequency, and is a fixed value. As shown in FIG. 8(a), is a curve varying with the frequency, and is a constant unrelated to the frequency, thus, in the frequency domain, it is a straight line. When the interference source U SThe trend with frequency is shown in Fig. 8(b), and The integral result is shown in Fig. 8(c), when the area of the shaded part ② in the figure is greater than the sum of the areas ① and ③, formula (13) is established, that is, it is considered that the second scheme meets the applicable condition, and the anti-near electric field interference ability of the PCB can be improved by adopting the second scheme; otherwise, it is considered that the second scheme does not meet the applicable condition, and the anti-near electric field interference ability of the PCB cannot be improved by adopting the second scheme, and the first scheme is preferred.

[0119] Hereinafter, a specific embodiment is described.

[0120] It is assumed that the length and width of the PCB are both 10 cm, the thickness is about 0.1 cm, the length and width of the power / ground layer of the PCB are 10 cm and 5 cm respectively, and the load device connected between the power / ground layers is a resistor with a nominal resistance of 10Ω; the length and width of the two copper plates are both 30 cm, and the two copper plates are placed opposite to each other with a distance of 20 cm between them, and the PCB is placed at the middle position between the two copper plates; the near electric field interference is generated by a sub-module of a modular multilevel converter, the lower limit frequency f L = 150 kHz, and the upper limit frequency f H = 30 MHz.

[0121] The anti-interference abilities of the first scheme (such as the Figure 7 design) and the second scheme (such as the Figure 6 design) are compared through the above scheme comparison, and in a specific scenario, it is concluded through the above scheme comparison that the second scheme (the new scheme) is better. It is verified that Figure 9 is the induced interference voltage waveform diagram measured when the first scheme (the conventional scheme) is adopted, and the peak-to-peak value of the interference voltage is about 400 mV; Figure 10 is the induced interference voltage waveform diagram measured after the new scheme is adopted under the condition that the applicable condition is met, and the peak-to-peak value of the interference voltage is about 240 mV. The induced interference voltage after the new scheme is adopted is reduced to some extent compared with the conventional scheme, proving that the new scheme proposed in the application can effectively improve the anti-near electric field interference ability of the PCB, and the determination result of the applicable condition of the new scheme is more accurate.

[0122] The application proposes to improve the anti-interference ability of the PCB by adjusting the layout scheme of the power / ground layer of the PCB, and provides a comparison method for different layout schemes. Through the setting of a simple test environment, it can be quickly judged which scheme is more suitable in a specific power electronic system. At the same time, without considering the edge effect, the determination method is irrelevant to the specific structure of the actual power electronic system, and is only related to the characteristics of the near electric field interference source, the area of the power / ground layer of the PCB and the impedance characteristics of the load, and in addition to the measurement of the interference source, other related tests are performed in another Figure 1The simple test environment shown was performed.

[0123] It is to be understood that the above-described embodiments are merely illustrative of the principles of the application, and that numerous and various modifications can be made by those skilled in the art without departing from the spirit and scope of the application, and that such modifications are intended to fall within the scope of the application.

Claims

1. A method for improving the ability of a PCB to resist near field interference, the PCB being disposed between a copper plate A and a copper plate B and including a power layer P proximate to the copper plate A and a ground layer G proximate to the copper plate B, the method comprising: The method comprises: ​ In the case of a specific load impedance and interference source , the induced interference voltage of the first scheme and the induced interference voltage of the second scheme are calculated respectively, and the positive overlap areas of the power layer P and the ground layer G are different in the first scheme and the second scheme; The method for calculating the induced interference voltage comprises: constructing a disturbed equivalent circuit of the PCB; directly measuring the impedance between the power layer P and the ground layer G, selecting the parasitic capacitance impedance between the power layer P and the copper plate A or the parasitic capacitance impedance between the ground layer G and the copper plate B as the reference parasitic capacitance impedance, calculating the ratio of each parasitic capacitance impedance to the reference parasitic capacitance impedance based on the equivalent circuit, and obtaining the relationship coefficient between the parasitic capacitance impedances; calculating the induced interference voltage based on the equivalent circuit and the relationship coefficient between the parasitic capacitance impedances; Computing the amplitude ratio deciding within a frequency domain range ] whether or not is valid, and if so, adopting the second scheme, and if not, adopting the first scheme; The process for obtaining the relationship coefficient between the parasitic capacitance impedances comprises: define copper plate A and ground layer G to form port 1, copper plate B and power layer P to form port 2, measure the reflection coefficient of port 1 S 11 , the reverse transmission coefficient of port 2 to port 1 S 12 , the forward transmission coefficient of port 1 to port 2 S 21 , and the reflection coefficient of port 2 S 22 ; Based on equivalent circuit and coefficients S 11 , S 12 , S 21 , S 22 Port 1 input admittance with port 2 shorted Y 11 Port 1 to port 2 transfer admittance with port 1 shorted Y 12 Port 2 to port 1 transfer admittance with port 2 shorted Y 21 Port 2 input admittance with port 1 shorted Y 22 ; Based on equivalent circuit and admittance Y 11 , Y 12 , Y 21 and Y 22 constructing the parasitic capacitance admittance; constructing the relationship coefficient between the parasitic capacitance impedances based on the parasitic capacitance admittance.

2. The method of claim 1, wherein the PCB is a multilayer PCB. In the disturbed equivalent circuit of the PCB, it comprises: Interference source between copper plate A and copper plate B ; Parasitic capacitance in parallel between the power layer P and the ground layer G and the load impedance ; Parasitic capacitance between power layer P and copper plate A ; Parasitic capacitance between power layer P and copper plate B ; Stratum G and the parasitic capacitance between copper plate A ; Parasitic capacitance between the ground G and the copper plate B .

3. The method of claim 2, wherein the PCB is a multilayer PCB. Based on equivalent circuit and coefficients S 11 , S 12 , S 21 , S 22 Impedance calculation Y 11 , Y 12 , Y 21 and Y 22 The formula is: ； wherein is the impedance of the parasitic capacitance Cp is the impedance of the parasitic capacitance Based on equivalent circuit and admittance Y 11 , Y 12 , Y 21 and Y 22 calculating a relationship coefficient between the parasitic capacitance impedance, including, First, the admittance of the parasitic capacitances C1-C4 is calculated Y 1、 Y 2、 Y 3 and Y 4, the calculation formula is: ； wherein Y L is the impedance Z 0 / / Z L the inverse; According to the correspondence between admittance and impedance Y i =1 / Z i , the relationship coefficient between the impedances of the parasitic capacitances is constructed based on the admittances Y 1、 Y 2、 Y 3 and Y 4, wherein Z 1、 Z 2、 Z 3 and Z 4 are the impedances of the parasitic capacitances C 1、 C 2、 C 3 and C 4, respectively.

4. The method of claim 1, wherein the PCB is a multilayer PCB. coefficient S 11 , S 12 , S 21 , S 22 were measured using a vector network analyzer.

5. The method for improving the anti-near electric field interference capability of a PCB according to claim 1, characterized in that, The amplitude expression of each scheme is constructed based on the induced interference voltage, wherein the amplitude , the amplitude , and are linearly related to the impedance between the power layer P and the ground layer G measured in the first scheme and the second scheme, respectively, and are the inverse proportional functions of the reference parasitic capacitance impedance constructed based on the relationship coefficient in the first scheme and the second scheme, respectively. determining whether or not the condition is satisfied, specifically, determining whether or not the condition is satisfied.

6. The method of claim 1, wherein the PCB is a multi-layer PCB. f L = 150 kHz ， f H = 30 MHz 。 7. The method of claim 1, wherein the PCB is a multi-layer PCB. The length of the copper plate is greater than or equal to three times the length of the PCB, and the width of the copper plate is greater than or equal to three times the width of the PCB.

8. The method of claim 1, wherein the PCB is a multi-layer PCB. Obtaining near field interference sources by simulating or measuring the voltage between the two poles of the power current flowing through the lower switch tube in electronic devices U s .

9. The method of improving the near field coupling of a PCB of any one of claims 1 to 8, wherein, The first scheme is that the power layer and the ground layer of the PCB are arranged in a completely non-overlapping manner, and the second scheme is that the power layer and the ground layer of the PCB are arranged in a completely overlapping or partially overlapping manner.

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