An interlayer coupler and a method for fabricating an interlayer coupler.

Abstract

This specification discloses an interlayer coupler and a method for fabricating an interlayer coupler. First, the interlayer coupler includes: a silicon substrate, a silicon dioxide cladding, a silicon waveguide layer, and a silicon nitride layer. A silicon cuboid is located at one end of the interlayer coupler. A hybrid structure is connected to the silicon cuboid. The hybrid structure consists of silicon cones and silicon waveguide blocks of the same size arranged together. A subwavelength grating structure is connected to the hybrid structure. The subwavelength grating structure consists of silicon waveguide blocks of different sizes arranged together, with the size of the silicon waveguide blocks farther from the silicon cuboid smaller than that closer to the silicon cuboid. The silicon nitride layer includes a silicon nitride cuboid and a silicon nitride structure. The silicon nitride cuboid is located at the other end of the interlayer coupler. The silicon nitride structure is connected to the silicon nitride cuboid. The cross-sectional area of ​​the silicon nitride structure farther from the silicon nitride cuboid is smaller than that closer to the silicon nitride cuboid. This method can reduce power leakage, thereby improving coupling efficiency.

Description

Technical Field

[0001] This specification relates to the field of packaged integrated circuits, and in particular to an interlayer coupler and a method for fabricating an interlayer coupler. Background Technology

[0002] The mode size of a waveguide is 0.4-0.5 micrometers, while that of an optical fiber is 9-10 micrometers. The difference in mode size between the two is significant, making a perfect match impossible. Direct coupling would result in substantial coupling loss.

[0003] Typically, structural design is required to match the waveguide mode pattern with the optical fiber mode pattern to achieve high coupling efficiency. However, existing structures suffer from significant power leakage, resulting in low coupling efficiency.

[0004] Therefore, how to improve coupling efficiency is an urgent problem to be solved. Summary of the Invention

[0005] This specification provides an interlayer coupler and a method for fabricating an interlayer coupler to partially solve the aforementioned problems existing in the prior art.

[0006] The following technical solution is adopted in this specification:

[0007] This specification provides an interlayer coupler, comprising: a silicon substrate, a silicon dioxide cladding disposed on the silicon substrate, a silicon waveguide layer located in the lower half of the silicon dioxide cladding, and a silicon nitride layer located in the upper half of the silicon dioxide cladding;

[0008] The silicon waveguide layer includes a silicon cuboid, a subwavelength grating structure, and a hybrid structure. The silicon cuboid is located at one end of the interlayer coupler. The hybrid structure is connected to the silicon cuboid and is composed of silicon cones and silicon waveguide blocks of the same size. The subwavelength grating structure is connected to the hybrid structure and is composed of silicon waveguide blocks of different sizes. The size of the silicon waveguide block farther from the silicon cuboid is smaller than the size of the silicon waveguide block closer to the silicon cuboid.

[0009] The silicon nitride layer includes a silicon nitride cuboid and a silicon nitride structure. The silicon nitride cuboid is located at the other end of the interlayer coupler. The silicon nitride structure is connected to the silicon nitride cuboid. The cross-sectional area of ​​the silicon nitride structure that is away from the silicon nitride cuboid is smaller than the cross-sectional area that is close to the silicon nitride cuboid.

[0010] Optionally, the hybrid structure consists of silicon cones and silicon waveguide blocks of the same size arranged at equal intervals.

[0011] Optionally, the subwavelength grating structure consists of silicon waveguide blocks of different sizes arranged at the same interval.

[0012] Optionally, the thickness of the silicon waveguide layer is 220 nanometers.

[0013] Optionally, the thickness of the silicon nitride layer is 300 nanometers.

[0014] Optionally, the interlayer spacing between the silicon waveguide layer and the silicon nitride layer is 300 nanometers.

[0015] Optionally, the spacing between the silicon waveguide blocks is 300 nanometers, and the width of the silicon waveguide blocks ranges from 170 nanometers to 300 nanometers.

[0016] Optionally, the width of the silicon cone ranges from 120 nanometers to 500 nanometers.

[0017] This specification provides a method for fabricating an interlayer coupler, including:

[0018] Obtaining a silicon substrate;

[0019] Silicon waveguide layer patterns were constructed using an electron beam exposure system;

[0020] The silicon waveguide layer pattern is developed to obtain a developed silicon waveguide layer pattern, and the developed silicon waveguide layer pattern is etched using an inductively coupled plasma spectroscopy generator to generate a silicon waveguide layer.

[0021] A first silicon dioxide layer is formed on the surface of the silicon substrate by plasma-enhanced chemical vapor deposition to encapsulate the silicon waveguide layer. After forming a silicon nitride layer on the surface of the first silicon dioxide layer, a second silicon dioxide layer is formed on the surface of the silicon nitride layer to complete the fabrication of the interlayer coupler.

[0022] Optionally, before constructing the silicon waveguide layer pattern using an electron beam exposure system, the method further includes:

[0023] The silicon substrate is cleaned and dried by setting a solution.

[0024] Optionally, the set solution includes at least one of acetone solution, isoacetone solution, and water.

[0025] Optionally, the developed silicon waveguide layer pattern is etched using an inductively coupled plasma spectroscopy (ICP-PSG) generator to generate the silicon waveguide layer, specifically including:

[0026] The developed silicon waveguide layer pattern was etched using an inductively coupled plasma spectroscopy generator to generate a silicon waveguide layer with a thickness of 220 nanometers.

[0027] Optionally, a silicon nitride layer is formed on the surface of the first silicon dioxide layer, specifically including:

[0028] The deposition rate of silicon nitride was controlled by plasma-enhanced chemical vapor deposition to generate a silicon nitride layer with a thickness of 300 nanometers on the surface of the first silicon dioxide layer.

[0029] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects:

[0030] As can be seen from the above, the interlayer coupler includes: a silicon substrate, a silicon dioxide cladding layer disposed on the silicon substrate, a silicon waveguide layer located in the lower half of the silicon dioxide cladding layer, and a silicon nitride layer located in the upper half of the silicon dioxide cladding layer. The silicon waveguide layer includes a silicon cuboid, a subwavelength grating structure, and a hybrid structure. The silicon cuboid is located at one end of the interlayer coupler. The hybrid structure is connected to the silicon cuboid and consists of silicon cones and silicon waveguide blocks of the same size arranged together. The subwavelength grating structure is connected to the hybrid structure and consists of silicon waveguide blocks of different sizes arranged together, with the size of the silicon waveguide blocks farther from the silicon cuboid being smaller than the size of the silicon waveguide blocks closer to the silicon cuboid. The silicon nitride layer includes a silicon nitride cuboid and a silicon nitride structure. The silicon nitride cuboid is located at the other end of the interlayer coupler, and the silicon nitride structure is connected to the silicon nitride cuboid. The cross-sectional area of ​​the silicon nitride structure farther from the silicon nitride cuboid is smaller than the cross-sectional area closer to the silicon nitride cuboid. This method can reduce power leakage, thereby improving coupling efficiency. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and are used to explain this specification, but do not constitute an undue limitation thereof. In the drawings:

[0032] Figure 1 This is a schematic diagram showing the positional relationship between the silicon substrate, silicon waveguide layer, and silicon nitride layer from a side view, provided in an embodiment of this specification.

[0033] Figure 2 A schematic diagram of the positional relationship between the silicon waveguide layer and the silicon nitride layer from a top-down view, provided for embodiments of this specification;

[0034] Figure 3 This is a schematic flowchart illustrating a method for fabricating an interlayer coupler as provided in an embodiment of this specification. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0036] The technical solutions provided in the various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0037] In practical applications, the mode size of optical fiber is 9-10 micrometers, while the mode size of optical waveguide on silicon-based chip is 0.4-0.5 micrometers. The mode sizes of the two are quite different, making direct coupling impossible.

[0038] Existing structures suffer from significant power leakage, resulting in low coupling efficiency. Therefore, this solution provides an interlayer coupler to match the mode pattern of the optical waveguide on the silicon-based chip with that of the optical fiber, thereby improving coupling efficiency. Specifically... Figure 1 As shown.

[0039] Figure 1 This is a schematic diagram showing the positional relationship between the silicon substrate, silicon waveguide layer, and silicon nitride layer from a side view, as provided in the embodiments of this specification.

[0040] like Figure 1 As shown, an interlayer coupler provided in this specification includes: a silicon substrate 100, a silicon dioxide cladding 101 disposed on the silicon substrate, a silicon waveguide layer 102 located in the lower half of the silicon dioxide cladding, and a silicon nitride layer 103 located in the upper half of the silicon dioxide cladding.

[0041] exist Figure 1 As can be seen, the silicon substrate 100 is located at the bottom, the silicon waveguide layer 102 is located above the silicon substrate, the silicon nitride layer 103 is located above the silicon waveguide layer 102, and the silicon dioxide cladding layer 101 fills the remaining part.

[0042] The thickness of the silicon waveguide layer can be designed according to business requirements. For example, the thickness of the silicon waveguide layer can be 220 nanometers. The thickness of the silicon nitride layer can also be designed according to business requirements. For example, the thickness of the silicon nitride layer can be 300 nanometers. The thickness of the interlayer coupler can also be designed according to business requirements. For example, the thickness of the interlayer coupler can be 3 to 5 micrometers.

[0043] Similarly, the spacing between the silicon waveguide layer and the silicon nitride layer can be designed according to business requirements. For example, the spacing can be 300 nanometers.

[0044] Furthermore, this specification also provides interlayer couplers from a top-down view. Specifically, as follows... Figure 2 As shown.

[0045] Figure 2 This is a schematic diagram of the positional relationship between the silicon waveguide layer and the silicon nitride layer from a top-down view, provided for embodiments of this specification.

[0046] like Figure 2 As shown, the silicon waveguide layer 102 includes a silicon cuboid 200, a subwavelength grating structure 201, and a hybrid structure 202. The silicon cuboid 200 is located at one end of the interlayer coupler. The hybrid structure 202 is connected to the silicon cuboid 200 and is composed of silicon cones and silicon waveguide blocks of the same size. The subwavelength grating structure 201 is connected to the hybrid structure 202 and is composed of silicon waveguide blocks of different sizes. The size of the silicon waveguide blocks farther away from the silicon cuboid 200 is smaller than the size of the silicon waveguide blocks closer to the silicon cuboid 200.

[0047] Specifically, the hybrid structure 202 consists of silicon cones and silicon waveguide blocks of the same size arranged at equal intervals.

[0048] The subwavelength grating structure 201 consists of silicon waveguide blocks of different sizes arranged at the same interval.

[0049] As can be seen, the silicon waveguide blocks in the subwavelength grating structure 201 are arranged from the end closest to the silicon cuboid 200 to the end furthest from the silicon cuboid 200, with the same intervals from largest to smallest. The width of the silicon waveguide blocks can be designed according to business requirements. For example, the largest silicon waveguide block can have a width of 300 nanometers, and the smallest waveguide block can have a width of 170 nanometers.

[0050] By introducing a subwavelength grating structure, the equivalent refractive index of the waveguide is reduced, resulting in a smaller mode field size, which in turn allows the mode spot size of the waveguide to match the mode spot size of the optical fiber.

[0051] The silicon nitride layer 103 includes a silicon nitride cuboid 203 and a silicon nitride structure 204. The silicon nitride cuboid 203 is located at the other end of the interlayer coupler. The silicon nitride structure 204 is connected to the silicon nitride cuboid 203. The cross-sectional area of ​​the silicon nitride structure 204 away from the silicon nitride cuboid 203 is smaller than the cross-sectional area close to the silicon nitride cuboid 203.

[0052] The silicon nitride structure 204 has trapezoidal top and bottom surfaces, and its left and front sides are rectangles of different sizes. The rectangle on the left side is larger than the rectangle on the right side, while the front and rear sides are rectangles of the same size.

[0053] Furthermore, in Figure 2 In the process, when light enters the fiber core and enters the linearly narrowing silicon nitride structure 204, according to the principle of optical mode coupling, as the width of the silicon nitride structure 204 narrows, the size of the optical mode field will decrease. The optical mode field is gradually compressed as the width of the silicon nitride structure 204 narrows, reducing its ability to confine light. Light leaks from the silicon nitride structure 204 into the lower subwavelength grating structure 201, which has a stronger ability to confine light, and then propagates into the hybrid structure 202, and is output from the silicon cuboid 200. This avoids light leakage to the silicon substrate and improves the coupling efficiency.

[0054] The spacing between the silicon waveguide blocks can be designed according to business requirements. For example, the spacing can be 300 nanometers.

[0055] The width of a silicon cone can be designed according to business requirements. For example, the width of a silicon cone can range from 120 nanometers to 500 nanometers. That is, the minimum width of a silicon cone is 120 nanometers, and the maximum width of a silicon cone is 500 nanometers.

[0056] The above describes one type of interlayer coupler provided in this specification. This specification also provides a method for fabricating an interlayer coupler. Specifically, as follows... Figure 3 As shown.

[0057] Figure 3 This is a schematic flowchart illustrating a method for fabricating an interlayer coupler as provided in an embodiment of this specification.

[0058] S300: Obtain silicon substrate.

[0059] S302: The silicon waveguide layer pattern is constructed using an electron beam exposure system.

[0060] S304: The silicon waveguide layer pattern is developed to obtain a developed silicon waveguide layer pattern, and the developed silicon waveguide layer pattern is etched by an inductively coupled plasma spectroscopy generator to generate a silicon waveguide layer.

[0061] S306: A first silicon dioxide layer is formed on the surface of the silicon substrate by plasma-enhanced chemical vapor deposition to encapsulate the silicon waveguide layer. After forming a silicon nitride layer on the surface of the first silicon dioxide layer, a second silicon dioxide layer is formed on the surface of the silicon nitride layer to complete the fabrication of the interlayer coupler.

[0062] In the embodiments of this specification, a silicon substrate is obtained and placed in a fabrication apparatus to perform subsequent fabrication methods.

[0063] Secondly, the fabrication equipment can construct silicon waveguide layer patterns using an electron beam exposure system. Electron beam exposure, mentioned here, refers to the process of creating patterns on a surface using an electron beam, an extension of photolithography. Photolithography is a crucial step in semiconductor device manufacturing. This step uses exposure and development to etch geometric structures onto a photoresist layer, and then transfers the pattern from the photomask to the substrate through an etching process. The substrate referred to here includes not only silicon wafers but also other metal layers and dielectric layers, such as glass and sapphire in SOS.

[0064] The fabrication equipment then develops the silicon waveguide layer pattern, obtaining a developed silicon waveguide layer pattern. This developed pattern is then etched using an inductively coupled plasma (ICP) spectroscopy generator to generate the silicon waveguide layer. The ICP spectroscopy generator can be used for ICP etching, a widely used technique that offers high-rate, high-selectivity, and low-damage etching. Plasma remains stable under low pressure, thus allowing for better control of the etched morphology.

[0065] Finally, the fabrication equipment can use plasma-enhanced chemical vapor deposition (PECVD) to generate a first silicon dioxide layer on the silicon substrate surface, a silicon nitride layer on the first silicon dioxide layer surface, and a second silicon dioxide layer on the silicon nitride layer surface, thus completing the fabrication of the interlayer coupler. PECVD refers to a method in chemical vapor deposition where an excited gas is used to generate a low-temperature plasma, enhancing the chemical activity of the reactants and thus performing epitaxy. This method can form solid films at relatively low temperatures. For example, in a reaction chamber, the substrate material is placed on a cathode, and a reactive gas is introduced to a low pressure (1–600 Pa). The substrate is maintained at a certain temperature, and glow discharge is generated in a certain way. The gas near the substrate surface is ionized, the reactive gas is activated, and cathode sputtering occurs on the substrate surface, thereby improving surface activity. Not only are there conventional thermochemical reactions on the surface, but also complex plasma chemical reactions. The deposited film is formed under the combined action of these two chemical reactions.

[0066] Specifically, the preparation equipment can clean and dry the silicon substrate using a pre-defined solution. For example, acetone or isoacetone solutions can be used to clean oil and other organic substances from the silicon substrate. Water can be used to remove impurities from the silicon substrate.

[0067] Furthermore, the fabrication equipment can use an inductively coupled plasma spectroscopy generator to etch the pattern of the developed silicon waveguide layer, generating a silicon waveguide layer with a thickness of 220 nanometers.

[0068] The fabrication equipment can control the deposition rate of silicon nitride using plasma-enhanced chemical vapor deposition to generate a silicon nitride layer with a thickness of 300 nanometers on the surface of the first silicon dioxide layer.

[0069] As can be seen from the above process, the interlayer coupler includes: a silicon substrate, a silicon dioxide cladding layer disposed on the silicon substrate, a silicon waveguide layer located in the lower half of the silicon dioxide cladding layer, and a silicon nitride layer located in the upper half of the silicon dioxide cladding layer. The silicon waveguide layer includes a silicon cuboid, a subwavelength grating structure, and a hybrid structure. The silicon cuboid is located at one end of the interlayer coupler. The hybrid structure is connected to the silicon cuboid and consists of silicon cones and silicon waveguide blocks of the same size arranged together. The subwavelength grating structure is connected to the hybrid structure and consists of silicon waveguide blocks of different sizes arranged together, with the size of the silicon waveguide blocks farther from the silicon cuboid being smaller than the size of the silicon waveguide blocks closer to the silicon cuboid. The silicon nitride layer includes a silicon nitride cuboid and a silicon nitride structure. The silicon nitride cuboid is located at the other end of the interlayer coupler, and the silicon nitride structure is connected to the silicon nitride cuboid. The cross-sectional area of ​​the silicon nitride structure farther from the silicon nitride cuboid is smaller than the cross-sectional area closer to the silicon nitride cuboid. This method can reduce power leakage, thereby improving coupling efficiency.

[0070] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0071] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0072] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0073] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0074] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0075] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0076] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0077] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0079] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0080] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0081] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0082] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0083] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0084] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0085] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0086] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. An interlayer coupler, characterized in that, include: A silicon substrate, a silicon dioxide cladding layer disposed on the silicon substrate, a silicon waveguide layer located in the lower half of the silicon dioxide cladding layer, and a silicon nitride layer located in the upper half of the silicon dioxide cladding layer; The silicon waveguide layer includes a silicon cuboid, a subwavelength grating structure, and a hybrid structure. The silicon cuboid is located at one end of the interlayer coupler. The hybrid structure is connected to the silicon cuboid and consists of silicon cones and silicon waveguide blocks of the same size arranged together. The apex of the silicon cones faces away from the silicon cuboid. The subwavelength grating structure is connected to the end of the hybrid structure away from the silicon cuboid and consists of silicon waveguide blocks of different sizes arranged together. The size of the silicon waveguide block away from the silicon cuboid is smaller than the size of the silicon waveguide block closer to the silicon cuboid. The silicon nitride layer includes a silicon nitride cuboid and a silicon nitride structure. The silicon nitride cuboid is located at the other end of the interlayer coupler. The silicon nitride structure is connected to the silicon nitride cuboid. The cross-sectional area of ​​the silicon nitride structure that is away from the silicon nitride cuboid is smaller than the cross-sectional area that is close to the silicon nitride cuboid.

2. The interlayer coupler as described in claim 1, characterized in that, The hybrid structure consists of silicon cones and silicon waveguide blocks of the same size arranged at equal intervals.

3. The interlayer coupler as described in claim 1, characterized in that, The subwavelength grating structure consists of silicon waveguide blocks of different sizes arranged at equal intervals.

4. The interlayer coupler as described in claim 1, characterized in that, The thickness of the silicon waveguide layer is 220 nanometers.

5. The interlayer coupler as described in claim 1, characterized in that, The thickness of the silicon nitride layer is 300 nanometers.

6. The interlayer coupler as described in claim 1, characterized in that, The interlayer spacing between the silicon waveguide layer and the silicon nitride layer is 300 nanometers.

7. The interlayer coupler as described in claim 1, characterized in that, The spacing between each silicon waveguide block is 300 nanometers, and the width of the silicon waveguide block ranges from 170 nanometers to 300 nanometers.

8. The interlayer coupler as described in claim 1, characterized in that, The width of the silicon cone ranges from 120 nanometers to 500 nanometers.

9. A method for fabricating an interlayer coupler, characterized in that, The method for preparing the interlayer coupler as described in any one of claims 1 to 8 comprises: Obtaining a silicon substrate; Silicon waveguide layer patterns were constructed using an electron beam exposure system; The silicon waveguide layer pattern is developed to obtain a developed silicon waveguide layer pattern, and the developed silicon waveguide layer pattern is etched using an inductively coupled plasma spectroscopy generator to generate a silicon waveguide layer. A first silicon dioxide layer is formed on the surface of the silicon substrate by plasma-enhanced chemical vapor deposition to encapsulate the silicon waveguide layer. After forming a silicon nitride layer on the surface of the first silicon dioxide layer, a second silicon dioxide layer is formed on the surface of the silicon nitride layer to complete the fabrication of the interlayer coupler.

10. The method as described in claim 9, characterized in that, Before constructing the silicon waveguide layer pattern using an electron beam exposure system, the method further includes: The silicon substrate is cleaned and dried by setting a solution.

11. The method as described in claim 10, characterized in that, The set solution includes at least one of the following: acetone solution, isoacetone solution, and water.

12. The method as described in claim 9, characterized in that, The silicon waveguide layer is generated by etching the developed silicon waveguide layer pattern using an inductively coupled plasma spectroscopy (ICP-PSA) generator, specifically including: The developed silicon waveguide layer pattern was etched using an inductively coupled plasma spectroscopy generator to generate a silicon waveguide layer with a thickness of 220 nanometers.

13. The method as described in claim 9, characterized in that, Forming a silicon nitride layer on the surface of the first silicon dioxide layer specifically includes: The deposition rate of silicon nitride was controlled by plasma-enhanced chemical vapor deposition to generate a silicon nitride layer with a thickness of 300 nanometers on the surface of the first silicon dioxide layer.

Images