Control circuit for constant effective value control and electronic device

Abstract

The application provides a control circuit and electronic equipment for constant effective value control, wherein the control circuit comprises a first transconductance amplifier, a first charge-discharge capacitor, a first operational amplifier, a second transconductance amplifier, a second charge-discharge capacitor, a second operational amplifier and an SR latch; the first transconductance amplifier is used for charging the first charge-discharge capacitor; the output end of the first operational amplifier is connected with the first input end of the SR latch; the second transconductance amplifier is used for charging the second charge-discharge capacitor; the output end of the second operational amplifier is connected with the second input end of the SR latch; and the output end of the SR latch outputs a PWM signal for realizing constant effective value control. The control circuit and electronic equipment provided by the embodiment of the application have simple circuit structure, can realize constant effective value output with extremely low cost, and the output power is irrelevant to parameters such as temperature and power supply voltage.

Description

Technical Field

[0001] This invention relates to the field of output control technology, and more specifically, to a control circuit and electronic device for constant effective value control. Background Technology

[0002] With the improvement of people's living standards and the rapid development of electronic information technology, the market demand and development of portable electronic devices are increasing day by day. At the same time, people have put forward higher requirements for the completeness of functions and consistency of use of electronic devices. This is reflected in product parameters, namely, that the output voltage and power do not change with the external environment. Due to the portable and lightweight nature of consumer electronic devices, the control circuit cannot be too complex and must be simple and reliable. For battery-powered DC closed-loop control systems, such as electronic cigarettes, electric fans, cigarette lighters, electric shavers, and electric toothbrushes, three control methods can generally be used: constant voltage output control, constant power control, and constant RMS control.

[0003] Constant voltage output mode refers to maintaining a constant average voltage during the output process. Constant voltage control has the following problems: battery voltage gradually decreases over time, leading to a decrease in output power. For example, if the desired battery voltage is 2.1V, when the battery voltage is higher than 2.1V, the chip internally controls the output voltage to be 2.1V. When the battery voltage is lower than this value, because the duty cycle has reached 100%, the output voltage will decrease along with the battery voltage. According to the power formula, the output power also decreases due to the decrease in battery voltage. Taking e-cigarettes as an example, the decrease in output power will change the taste for the user, resulting in inconsistent taste and a poor user experience.

[0004] Constant power output mode refers to maintaining a constant output power during the output process, achieving the design target by detecting load voltage and current. During use, battery voltage will continuously decrease due to discharge, and the load may also decrease. Constant power control obtains a PWM signal by detecting the power supply voltage and output current, ensuring that the output power does not change with variations in power supply voltage or load. In other words, once the power is set, it cannot be changed, making it unsuitable for certain applications. Furthermore, generating this control signal requires analog-to-digital conversion of the output current, resulting in complex circuitry, and the power setting is difficult to alter.

[0005] Constant effective voltage (CEPS) output control mode refers to maintaining a constant effective voltage during the output process. Compared to constant voltage output, this method offers the advantage of consistent output power when the load resistance remains unchanged. Different power settings can be achieved simply by altering the load. CEPS control ensures a constant output power and allows for different power settings by varying the load; different loads can correspond to different power levels. CEPS control utilizes a PWM signal generated by detecting the output voltage and a reference voltage. However, implementing CEPS typically requires controller components, ADCs (analog-to-digital converters), etc., resulting in complex circuitry, implementation difficulties, and high costs. Summary of the Invention

[0006] To address the complexity of existing constant RMS control methods, the present invention aims to provide a control circuit and electronic device for constant RMS control.

[0007] In a first aspect, embodiments of the present invention provide a control circuit for constant effective value control, comprising: a first transconductance amplifier, a first charging / discharging capacitor, a first operational amplifier, a second transconductance amplifier, a second charging / discharging capacitor, a second operational amplifier, and an SR latch;

[0008] The input terminal of the first transconductance amplifier is used to connect to a preset reference voltage, and the output terminal of the first transconductance amplifier is connected to one end of the first charging and discharging capacitor for charging the first charging and discharging capacitor; one end of the first charging and discharging capacitor is also connected to the positive input terminal of the first operational amplifier, and the other end of the first charging and discharging capacitor is grounded.

[0009] The negative input terminal of the first operational amplifier is used to connect to the target voltage, which is a voltage that has a linear relationship with the acquired supply voltage; the output terminal of the first operational amplifier is connected to the first input terminal of the SR latch.

[0010] The input terminal of the second transconductance amplifier is used to connect to the target voltage, and the output terminal of the second transconductance amplifier is connected to one end of the second charging and discharging capacitor for charging the second charging and discharging capacitor; one end of the second charging and discharging capacitor is also connected to the positive input terminal of the second operational amplifier, and the other end of the second charging and discharging capacitor is grounded;

[0011] The negative input terminal of the second operational amplifier is used to connect to the reference voltage; the output terminal of the second operational amplifier is connected to the second input terminal of the SR latch.

[0012] The first charge-discharge capacitor is also used to fully discharge when the voltage is charged to the target voltage;

[0013] The second charging and discharging capacitor is also used to fully discharge when the voltage is charged to the reference voltage or when the first input terminal of the SR latch is high.

[0014] The output terminal of the SR latch outputs a PWM signal for achieving constant effective value control.

[0015] In one possible implementation, the first charging time is greater than the second charging time; the first charging time is the charging time for the voltage of the first charge / discharge capacitor to reach the target voltage, and the second charging time is the charging time for the voltage of the second charge / discharge capacitor to reach the reference voltage.

[0016] In one possible implementation, the first input of the SR latch is a set input, and the second input of the SR latch is a reset input.

[0017] In one possible implementation, the duty cycle D of the PWM signal satisfies:

[0018]

[0019] Wherein, C1 is the capacitance value of the first charging / discharging capacitor, C2 is the capacitance value of the second charging / discharging capacitor, 1 / R1 is the transconductance of the first transconductance amplifier, 1 / R2 is the transconductance of the second transconductance amplifier, VREF is the reference voltage, and VT is the target voltage.

[0020] In one possible implementation, the SR latch is a NOR gate SR latch, and the positive output of the SR latch is used to output the PWM signal.

[0021] In one possible implementation, the target voltage satisfies:

[0022] VT = K1 × BAT;

[0023] Wherein, VT is the target voltage, BAT is the power supply voltage, and K1 is a preset fixed coefficient.

[0024] In one possible implementation, the control circuit also includes at least four inverters;

[0025] The output of the first operational amplifier is connected in series with an even number of inverters and then connected to the first input of the SR latch.

[0026] The output of the second operational amplifier is connected in series with an even number of the inverters and then connected to the second input of the SR latch.

[0027] In one possible implementation, the control circuit further includes a first frequency divider circuit and a second frequency divider circuit;

[0028] The output of the first operational amplifier is connected in series with the first frequency divider circuit and then connected to the first input of the SR latch.

[0029] The output of the second operational amplifier is connected in series with the second frequency divider circuit and then connected to the second input of the SR latch.

[0030] In one possible implementation, the first frequency divider circuit and the second frequency divider circuit have different frequency division coefficients.

[0031] Secondly, embodiments of the present invention also provide an electronic device, including: a control circuit for constant effective value control as described above.

[0032] In the solution provided by the first aspect of the present invention, the charging and discharging states of two charging and discharging capacitors are used to control the two input terminals of the SR latch respectively. The first charging and discharging capacitor controls the period T of the PWM signal, and the second charging and discharging capacitor controls the on-time Ton of the PWM signal, thereby controlling the duty cycle D of the PWM signal and enabling the PWM signal to achieve constant effective value control. This control circuit does not require components such as a controller and analog-to-digital converter, has a simple circuit structure, and can achieve constant effective value output at extremely low cost. By setting different constant parameters and selecting components of appropriate specifications (e.g., selecting the first and second charging and discharging capacitors of appropriate specifications), the expected power constant effective value output can be achieved, and the output power is independent of parameters such as temperature and supply voltage.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This invention provides a schematic diagram of a control circuit for constant effective value control according to an embodiment of the present invention.

[0036] Figure 2 A timing diagram of a control circuit provided in an embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram of another circuit structure of the control circuit for constant effective value control provided in an embodiment of the present invention is shown;

[0038] Figure 4 This diagram illustrates another circuit structure of the control circuit for constant effective value control provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10. First transconductance amplifier; C1. First charging / discharging capacitor; A1. First operational amplifier; 20. Second transconductance amplifier; C2. Second charging / discharging capacitor; A2. Second operational amplifier; 30. SR latch; 40. First frequency divider circuit; 50. Second frequency divider circuit. Detailed Implementation

[0041] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] This invention provides a control circuit for constant RMS control, see [link to relevant documentation]. Figure 1 As shown, the control circuit includes: a first transconductance amplifier 10, a first charging / discharging capacitor C1, a first operational amplifier A1, a second transconductance amplifier 20, a second charging / discharging capacitor C2, a second operational amplifier A2, and an SR latch 30.

[0045] like Figure 1 As shown, the input terminal Vin of the first transconductance amplifier 10 is used to connect to a preset reference voltage VREF. The output terminal Io of the first transconductance amplifier 10 is connected to one end of the first charging / discharging capacitor C1 to charge the first charging / discharging capacitor C1. One end of the first charging / discharging capacitor C1 is also connected to the positive input terminal of the first operational amplifier A1, and the other end of the first charging / discharging capacitor C1 is grounded. The negative input terminal of the first operational amplifier A1 is used to connect to the target voltage VT, which is a voltage that has a linear relationship with the acquired supply voltage (hereinafter referred to as BAT). The output terminal of the first operational amplifier A1 is connected to the first input terminal of the SR latch 30.

[0046] The input terminal Vin of the second transconductance amplifier 20 is used to connect to the target voltage VT. The output terminal Io of the second transconductance amplifier 20 is connected to one end of the second charging / discharging capacitor C2 to charge the second charging / discharging capacitor C2. One end of the second charging / discharging capacitor C2 is also connected to the positive input terminal of the second operational amplifier A2, and the other end of the second charging / discharging capacitor C2 is grounded. The negative input terminal of the second operational amplifier A2 is used to connect to the reference voltage VREF. The output terminal of the second operational amplifier A2 is connected to the second input terminal of the SR latch 30.

[0047] The first charging / discharging capacitor C1 is also used to fully discharge when the voltage is charged to the target voltage VT; the second charging / discharging capacitor C2 is also used to fully discharge when the voltage is charged to the reference voltage VREF, or when the first input terminal of the SR latch 30 is at a high level. The output terminal of the SR latch 30 outputs a PWM signal for implementing constant effective value control. Those skilled in the art will understand that the "high level" and the "low level" mentioned below in the embodiments of the present invention are relative levels, that is, the level of the "high level" is greater than the level of the "low level", and are not used to indicate how high or low a certain level is.

[0048] In this embodiment of the invention, the input of the transconductance amplifier is voltage, and the output is current; for example... Figure 1As shown, the voltage input to the input terminal Vin of the first transconductance amplifier 10 is the reference voltage VREF. Correspondingly, the output terminal Io of the first transconductance amplifier 10 will output a corresponding current, and the magnitude of this current is related to the transconductance of the first transconductance amplifier 10. In this embodiment of the invention, transconductance is expressed as the reciprocal of resistance. If the transconductance of the first transconductance amplifier 10 is 1 / R1, then the relationship between the input terminal and the output terminal of the first transconductance amplifier 10 satisfies Io = Vin / R1, that is, the current output by the first transconductance amplifier 10 is VREF / R1. Similarly, if the transconductance of the second transconductance amplifier 20 is 1 / R2, the relationship between its input terminal and its output terminal satisfies Io = Vin / R2; and the voltage at the input terminal of the second transconductance amplifier 20 is the target voltage VT, and the current at its output terminal is VT / R2.

[0049] The target voltage VT is a voltage related to the acquired supply voltage. Specifically, the target voltage VT has a linear relationship with the acquired supply voltage, which can be expressed as: VT = K1 × BAT; where VT is the target voltage, BAT is the acquired supply voltage, and K1 is a preset fixed coefficient. The supply voltage BAT is the voltage of the battery that powers the circuit to operate normally; as the battery discharges, the supply voltage BAT gradually decreases.

[0050] In this embodiment of the invention, a capacitor is provided at the output terminal of each transconductance amplifier, and the capacitor is charged using the current output by the transconductance amplifier. For example... Figure 1 As shown, the output terminal Io of the first transconductance amplifier 10 is connected to a first charging / discharging capacitor C1, and charges the first charging / discharging capacitor C1. The charging current of the first charging / discharging capacitor C1 is VREF / R1. Similarly, the output terminal Io of the second transconductance amplifier 20 is connected to a second charging / discharging capacitor C2, and charges the second charging / discharging capacitor C2. The charging current of the second charging / discharging capacitor C2 is VT / R2.

[0051] The positive input terminal of the first operational amplifier A1 is connected to one end of the first charging / discharging capacitor C1. The voltage at its positive input terminal is the voltage of the first charging / discharging capacitor C1. As the first transconductance amplifier 10 charges the first charging / discharging capacitor C1, its voltage gradually increases. The negative input terminal of the first operational amplifier A1 is connected to the target voltage VT. When the voltage at the positive input terminal of the first operational amplifier A1 is less than the voltage at the negative input terminal, that is, when the voltage of the first charging / discharging capacitor C1 is less than the target voltage VT, the output terminal of the first operational amplifier A1 is at a low level. As the voltage of the first charging / discharging capacitor C1 gradually increases, until it equals and exceeds the target voltage VT, that is, when the voltage at the positive input terminal of the first operational amplifier A1 is greater than the voltage at the negative input terminal, the output terminal of the first operational amplifier A1 is at a high level.

[0052] Furthermore, the first charging / discharging capacitor C1 can be charged under the action of the output current of the first transconductance amplifier 10. In addition, the first charging / discharging capacitor C1 also needs to be discharged. In this embodiment of the invention, the first charging / discharging capacitor C1 is also used to fully discharge when its voltage reaches the target voltage VT. That is, when the voltage of the first charging / discharging capacitor C1 reaches the target voltage VT, the first charging / discharging capacitor C1 will be discharged, and it needs to be completely discharged, i.e., the voltage of the first charging / discharging capacitor C1 drops to zero. Figure 1 The circuit structure for charging the first charging / discharging capacitor C1 is shown, but the circuit structure for discharging the first charging / discharging capacitor C1 is not shown. Those skilled in the art can implement the discharge based on any circuit structure capable of fulfilling this discharge requirement; this embodiment does not limit this. For example, when the voltage of the first charging / discharging capacitor C1 is charged to the target voltage VT, the output of the first operational amplifier A1 is at a high level. The discharge of the first charging / discharging capacitor C1 is achieved using the level state of the output of the first operational amplifier A1.

[0053] Similarly, the positive input terminal of the second operational amplifier A2 is connected to one end of the second charging / discharging capacitor C2, and the voltage at its positive input terminal is the voltage of the second charging / discharging capacitor C2. As the second transconductance amplifier 20 charges the second charging / discharging capacitor C2, its voltage gradually increases. The negative input terminal of the second operational amplifier A2 is connected to the reference voltage VREF. When the voltage at the positive input terminal of the second operational amplifier A2 is less than the voltage at the negative input terminal, that is, when the voltage of the second charging / discharging capacitor C2 is less than the reference voltage VREF, the output terminal of the second operational amplifier A2 is at a low level. As the voltage of the second charging / discharging capacitor C2 gradually increases, making its voltage equal to and exceeding the reference voltage VREF, that is, when the voltage at the positive input terminal of the second operational amplifier A2 is greater than the voltage at the negative input terminal, the output terminal of the second operational amplifier A2 is at a high level.

[0054] Furthermore, the second charging / discharging capacitor C2 can be charged under the action of the output current of the second transconductance amplifier 20. In addition, the second charging / discharging capacitor C2 also needs to be discharged. In this embodiment of the invention, the second charging / discharging capacitor C2 is also used to fully discharge when its voltage reaches the reference voltage VREF. That is, when the voltage of the second charging / discharging capacitor C2 reaches the reference voltage VREF, it will discharge completely, i.e., the voltage of the second charging / discharging capacitor C2 drops to zero. Similarly, Figure 1The circuit structure for charging the second charging / discharging capacitor C2 is shown, but the circuit structure for discharging the second charging / discharging capacitor C2 is not shown. Those skilled in the art can implement the discharge based on any circuit structure that can achieve this discharge requirement, and this embodiment does not limit this. Furthermore, when the first input terminal of the SR latch 30 is at a high level, the second charging / discharging capacitor C2 also needs to be discharged, and the discharge process at this time will be described in detail later.

[0055] In this embodiment of the invention, since the voltage of the first charging / discharging capacitor C1 discharges when it reaches the target voltage VT, and the voltage of the second charging / discharging capacitor C2 discharges when it reaches the reference voltage VREF, the outputs of the first operational amplifier A1 and the second operational amplifier A2 are only at a high level for a brief moment, and the signals they output are similar to pulse signals. The two pulse signals are respectively connected to the two input terminals of the SR latch 30, namely the first input terminal and the second input terminal. The input terminals of the SR latch 30 include a set terminal S. D and reset terminal R D For example, such as Figure 1 As shown, the first input terminal of the SR latch 30 is the set terminal S. D The signal output by the first operational amplifier A1 is used to connect to the set terminal S. D The second input terminal of SR latch 30 is the reset terminal R. D The signal output by the second operational amplifier A2 is used to connect to the reset terminal R. D .

[0056] In this embodiment of the invention, when both inputs of the SR latch 30 are low, it is in a latched state. For example, the SR latch 30 is a NOR gate SR latch. Furthermore, as... Figure 1 As shown, the first input terminal of the SR latch 30 is the set terminal S. D The second input terminal is the reset terminal R. D In this case, the positive output terminal of the SR latch 30 outputs a PWM signal; the first input terminal of the SR latch 30 is the reset terminal R. D The second input terminal is the set terminal S. D In this case, the negative output terminal of the SR latch 30 outputs a PWM signal. In this embodiment of the invention, the duty cycle of the PWM signal output by the SR latch 30 is related to the acquired power supply voltage BAT. By adjusting the power supply voltage BAT based on the PWM signal, an output power independent of the power supply voltage BAT can be obtained.

[0057] Specifically, with Figure 1 Taking the control circuit structure shown as an example, the output terminal of the first operational amplifier A1 and the set terminal S of the SR latch 30 are connected. DThe output of the second operational amplifier A2 is connected to the reset terminal R of the SR latch 30. D Connected, the positive output terminal Q of SR latch 30 is used to output the PWM signal. The specific operation process of this control circuit is as follows:

[0058] Figure 2 The waveform diagram of the control circuit is shown, in which, Figure 2 From top to bottom: the voltage waveform of the first charging / discharging capacitor C1, the voltage waveform of the second charging / discharging capacitor C2, and the set terminal S. D The voltage waveform (also the voltage waveform at the output of the first operational amplifier A1), and the reset terminal R D The voltage waveform (also the voltage waveform at the output of the second operational amplifier A2) and the waveform of the PWM signal (also the voltage waveform at the positive output of the SR latch 30) are shown. Since the operation of this control circuit is periodic, this embodiment of the invention will be described using one cycle as an example.

[0059] like Figure 2 As shown, at time t1, the voltage of the first charging / discharging capacitor C1 is charged to the target voltage VT. The voltage at the positive input terminal of the first operational amplifier A1 is greater than the voltage at the negative input terminal, and the first operational amplifier A1 outputs a high level, i.e., the set terminal S. D The voltage level changes to high. Since the first charging / discharging capacitor C1 is fully discharged when it reaches the target voltage VT, the voltage of C1 drops to 0. After this voltage drop, the voltage at the positive input terminal of the first operational amplifier A1 is again less than the voltage at the negative input terminal, resulting in a low output level, i.e., the set terminal S. D When the signal goes low, the set pin S D It is high for only a brief moment. Furthermore, due to the set pin S... D When the output goes high, the second charging / discharging capacitor C2 is also fully discharged, and the second operational amplifier A2 maintains a low output level, i.e., the reset terminal R... D Keep it low. At the set input S D High level, reset terminal R D When the signal is low, SR latch 30 is set, and its positive output is high, meaning the PWM signal is high.

[0060] In this embodiment of the invention, when the voltage of the first charging / discharging capacitor C1 is charged to the target voltage VT, the voltage of the second charging / discharging capacitor C2 cannot be the reference voltage VREF (in this control circuit, the voltage of the second charging / discharging capacitor C2 must be less than the reference voltage VREF). This can be easily achieved by selecting a capacitor of appropriate size.

[0061] After time t1, both the first charging / discharging capacitor C1 and the second charging / discharging capacitor C2 are in a charging state, and the outputs of both the first operational amplifier A1 and the second operational amplifier A2 are also at a low level, i.e., the set terminal S. D Reset terminal R D Both are at low level. At this time, SR latch 30 is in latch state, that is, the positive output terminal of SR latch 30 is kept at high level.

[0062] At time t2, the voltage of the second charging / discharging capacitor C2 is charged to the reference voltage VREF (which can be a fixed value). The voltage at the positive input terminal of the second operational amplifier A2 is greater than the voltage at the negative input terminal, and the second operational amplifier A2 outputs a high level, i.e., the reset terminal R... D The voltage drops to high. Since the second charging / discharging capacitor C2 is fully discharged when it reaches the reference voltage VREF, its voltage drops to 0. After this voltage drop, the voltage at the positive input terminal of the second operational amplifier A2 is again less than the voltage at the negative input terminal, resulting in a low output level, i.e., the reset terminal R... D When the signal goes low, the reset pin R... D The voltage level is high for only a brief moment. At this time, the voltage of the first charging / discharging capacitor C1 has not yet reached the target voltage VT, and the first operational amplifier A1 outputs a low level, i.e., the set terminal S. D Keep it low. At the set input S D Low level, reset terminal R D When the signal is high, the SR latch 30 is in a reset state, and its positive output is low, meaning the PWM signal becomes low.

[0063] After time t2, both the first charging / discharging capacitor C1 and the second charging / discharging capacitor C2 are in a charging state (the second charging / discharging capacitor C2 is recharged from zero), and the outputs of both the first operational amplifier A1 and the second operational amplifier A2 are also at a low level, i.e., the set terminal S. D Reset terminal R D Both are at low level. At this time, SR latch 30 is in latch state, that is, the positive output terminal of SR latch 30 remains at the original low level.

[0064] At time t3, which is similar to the previous time t2, we will not elaborate further. The difference lies in the setting terminal S. D Low level, reset terminal R D When the output is high, since the previous output of SR latch 30 was low, its output remains unchanged.

[0065] After time t3, the process is the same as after time t2, so it will not be repeated here.

[0066] At time t4, similar to time t1 above, the voltage of the first charging / discharging capacitor C1 is charged again to the target voltage VT, and the set terminal S... D The voltage level changes to high; the second charging / discharging capacitor C2 is fully discharged, and the reset terminal R... D It remains at a low level. At this time, SR latch 30 is in the set state, and its positive output is at a high level, that is, the PWM signal becomes high again.

[0067] In this embodiment of the invention, time t1 to time t4 is one working cycle of the control circuit. The working principle after time t4 is the same as that from time t1 to time t4, and will not be described in detail here.

[0068] based on Figure 2 It can be seen that from time t1 to time t4, the voltage of the first charging / discharging capacitor C1 charges from zero to the target voltage VT. This time period is the period of the PWM signal, which is denoted by T in this embodiment. From time t1 to time t2, the voltage of the second charging / discharging capacitor C2 charges from zero to the reference voltage VREF. This time period is the time when the PWM signal is at a high level, which is denoted by Ton in this embodiment. Therefore, the duty cycle of the PWM signal is D = Ton / T.

[0069] Since the reference voltage VREF is a fixed value (e.g., the reference voltage is the bandgap reference voltage), and the battery supply voltage BAT is also fixed for a short time, i.e., the target voltage VT is also a fixed value, the charging current of the first charging and discharging capacitor C1 is a fixed VREF / R1, and the charging current of the second charging and discharging capacitor C2 is a fixed VT / R2. The relationship between the charging time t of the first charging and discharging capacitor C1 and the charging voltage V satisfies: C1×V=t×VREF / R1; therefore, the time for the voltage of the first charging and discharging capacitor C1 to reach the target voltage VT, i.e., the period T of the PWM signal, satisfies the following equation (1):

[0070]

[0071] Correspondingly, the relationship between the charging time t of the second charging and discharging capacitor C2 and the charging voltage V satisfies: C2×V=t×VT / R2; therefore, the time it takes for the voltage of the second charging and discharging capacitor C2 to charge to the reference voltage VREF, that is, the time when the PWM signal is high, Ton satisfies the following equation (2):

[0072]

[0073] From equations (1) and (2) above, we can obtain that the duty cycle D of the PWM signal satisfies:

[0074]

[0075] Wherein, C1 is the capacitance value of the first charging / discharging capacitor C1, C2 is the capacitance value of the second charging / discharging capacitor C2, 1 / R1 is the transconductance of the first transconductance amplifier 10, 1 / R2 is the transconductance of the second transconductance amplifier 20, VREF is the reference voltage, and VT is the target voltage.

[0076] Since the target voltage VT and the supply voltage BAT have a linear relationship, i.e., VT=K1×BAT, the above equation (3) can also be expressed as:

[0077]

[0078] Furthermore, the power output formula for achieving constant RMS control is Po=D×BAT 2 / R load Where Po represents output power, D represents duty cycle, BAT represents supply voltage, and R... load This represents the load resistance. Substituting the duty cycle represented by equation (4) into this equation, we get:

[0079]

[0080] Based on the above equation (5), it can be seen that the output power Po is independent of the supply voltage BAT, and the load resistance R... load (The remaining parameters are constants in the circuit design, independent of the supply voltage BAT, and are all fixed values); therefore, the PWM signal generated by the control circuit in this embodiment of the invention can be used to achieve constant effective value control. For example, this control circuit can be subsequently connected to a logic circuit, and the power Po output by the logic circuit satisfies Po = D × BAT. 2 / R load ; at load resistance R load Under constant conditions, it can output constant power, and the output power can be adjusted by setting different load resistors R. load To set different output power Po.

[0081] The control circuit for constant effective value (RMS) control provided in this embodiment of the invention utilizes the charging and discharging states of two charging and discharging capacitors to control the two input terminals of an SR latch. The first charging and discharging capacitor C1 controls the period T of the PWM signal, and the second charging and discharging capacitor C2 controls the on-time Ton of the PWM signal, thereby controlling the duty cycle D of the PWM signal and enabling constant RMS control. This control circuit eliminates the need for a controller, analog-to-digital converter, and other components, resulting in a simple circuit structure and achieving constant RMS output at extremely low cost. By setting different constant parameters and selecting components of appropriate specifications (e.g., selecting the first charging and discharging capacitor C1 and the second charging and discharging capacitor C2 of appropriate specifications), the desired constant RMS power output can be achieved, and the output power is independent of parameters such as temperature and supply voltage.

[0082] Optionally, the first charging time is longer than the second charging time; the first charging time is the charging time for the voltage of the first charging / discharging capacitor C1 to reach the target voltage, and the second charging time is the charging time for the voltage of the second charging / discharging capacitor C2 to reach the reference voltage. That is, if both capacitors start charging simultaneously, when the voltage of the second charging / discharging capacitor C2 reaches the reference voltage VREF, the voltage of the first charging / discharging capacitor C1 has not yet reached the target voltage VT. In this embodiment of the invention, the first charging time being longer than the second charging time can, to a certain extent, ensure that at the set terminal S... D Within one cycle (i.e., the time interval between two consecutive high-level transitions), the reset terminal R... D There is a high-level state.

[0083] Optionally, see Figure 3 As shown, the control circuit also includes at least four inverters. Specifically, the output of the first operational amplifier A1 is connected in series with an even number of inverters and then connected to the first input of the SR latch 30; the output of the second operational amplifier A2 is connected in series with an even number of inverters and then connected to the second input of the SR latch 30.

[0084] Figure 3 In the circuit, the output of the first operational amplifier A1 is connected in series with two inverters, namely inverter N1 and inverter N2, and then connected to the first input of the SR latch 30, such as the set input S. D The output of the second operational amplifier A2 is also connected in series with two inverters, namely inverter N3 and inverter N4, and then connected to the second input of the SR latch 30, such as the reset terminal R. D Using an even number of inverters connected in series can improve the driving capability.

[0085] Optionally, see Figure 3 As shown, the control circuit also includes a first frequency divider circuit 40 and a second frequency divider circuit 50; the output terminal of the first operational amplifier A1 is connected in series with the first frequency divider circuit 40 and then connected to the first input terminal of the SR latch 30; the output terminal of the second operational amplifier A2 is connected in series with the second frequency divider circuit 50 and then connected to the second input terminal of the SR latch 30. Figure 3 As shown, the output of the first operational amplifier A1 is connected in series with two inverters and a first frequency divider circuit 40, and then connected to the first input of the SR latch 30; the output of the second operational amplifier A2 is connected in series with two inverters and a second frequency divider circuit 50, and then connected to the second input of the SR latch 30.

[0086] In this embodiment of the invention, the control circuit can be applied to an integrated circuit. The capacitance values ​​of the first charging / discharging capacitor C1 and the second charging / discharging capacitor C2 are generally small, and the charging time is also short. If it is necessary to increase the period T of the PWM signal, the first charging / discharging capacitor C1 needs to have a larger capacitance value, which is not easily achieved in engineering. This embodiment of the invention reduces the frequency through a frequency divider circuit, thereby increasing the period of the PWM signal. For example, frequency division can be implemented using a D flip-flop; such as... Figure 4 As shown, both the first frequency divider circuit 40 and the second frequency divider circuit 50 include two D flip-flops, and both implement a four-fold frequency divider.

[0087] Optionally, the first frequency divider circuit 40 and the second frequency divider circuit 50 can have different division coefficients. Using frequency divider circuits with different division coefficients, it is also possible to achieve [something] at the set terminal S. D Within one cycle (i.e., the time interval between two consecutive high-level transitions), the reset terminal R... D A high-level state exists. Furthermore, by selecting a suitable frequency divider circuit, the set input S can also be made to... D and reset terminal R D The signal has the same period.

[0088] This invention also provides an electronic device, comprising: any of the control circuits for constant effective value control provided in the above embodiments, wherein the control circuit is used to achieve constant effective value control and ensure the stability of the output voltage of the electronic device. For example, the electronic device can be an electric toothbrush, an electric shaver, an electric fan, a cigarette lighter, etc.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A control circuit for constant effective value control, characterized in that The application relates to a constant effective value control circuit. The input end of the first trans-impedance amplifier (10) is used for being connected to a preset reference voltage, the output end of the first trans-impedance amplifier (10) is connected to one end of the first charge-discharge capacitor (C1) and is used for charging the first charge-discharge capacitor (C1); one end of the first charge-discharge capacitor (C1) is also connected to the positive input end of the first operational amplifier (A1), and the other end of the first charge-discharge capacitor (C1) is grounded. The negative input end of the first operational amplifier (A1) is used for being connected to a target voltage, the target voltage is a voltage having a linear relationship with a collected power supply voltage; the output end of the first operational amplifier (A1) is connected to the first input end of the SR latch (30); The input end of the second trans-impedance amplifier (20) is used for being connected to the target voltage, the output end of the second trans-impedance amplifier (20) is connected to one end of the second charge-discharge capacitor (C2) and is used for charging the second charge-discharge capacitor (C2); one end of the second charge-discharge capacitor (C2) is also connected to the positive input end of the second operational amplifier (A2), and the other end of the second charge-discharge capacitor (C2) is grounded; The negative input end of the second operational amplifier (A2) is used for being connected to the reference voltage; the output end of the second operational amplifier (A2) is connected to the second input end of the SR latch (30); The first charge-discharge capacitor (C1) is also used for being completely discharged when the voltage is charged to the target voltage; The second charge-discharge capacitor (C2) is also used for being completely discharged when the voltage is charged to the reference voltage or the first input end of the SR latch (30) is high; The output end of the SR latch (30) outputs a PWM signal used for realizing constant effective value control. The first charging time is greater than the second charging time; the first charging time is the charging time of the voltage of the first charge-discharge capacitor (C1) charged to the target voltage, and the second charging time is the charging time of the voltage of the second charge-discharge capacitor (C2) charged to the reference voltage.

2. The control circuit of claim 1, wherein, The first input end of the SR latch (30) is a setting end, and the second input end of the SR latch (30) is a resetting end.

3. The control circuit of claim 1, wherein, The duty cycle D of the PWM signal satisfies:

4. The control circuit of claim 3, wherein, Wherein, C1 is the capacitance value of the first charge-discharge capacitor (C1), C2 is the capacitance value of the second charge-discharge capacitor (C2), 1 / R1 is the trans-impedance of the first trans-impedance amplifier (10), 1 / R2 is the trans-impedance of the second trans-impedance amplifier (20), VREF is the reference voltage, and VT is the target voltage. The SR latch (30) is an SR latch of an NOR gate, and the positive output end of the SR latch (30) is used for outputting the PWM signal.

5. The control circuit of claim 3, wherein, The target voltage satisfies:

6. The control circuit of claim 1, wherein, VT=K1*BAT ​ Wherein, VT is the target voltage, BAT is the power supply voltage, K1 is a preset fixed coefficient.

7. The control circuit of claim 1, wherein, Further comprising at least four inverters; The output of the first operational amplifier (A1) is connected to the first input of the SR latch (30) after being connected to an even number of inverters in series; The output of the second operational amplifier (A2) is connected to the second input of the SR latch (30) after being connected to an even number of inverters in series.

8. The control circuit of claim 1, wherein, Further comprising a first frequency dividing circuit (40) and a second frequency dividing circuit (50); The output of the first operational amplifier (A1) is connected to the first input of the SR latch (30) after being connected to the first frequency dividing circuit (40) in series; The output of the second operational amplifier (A2) is connected to the second input of the SR latch (30) after being connected to the second frequency dividing circuit (50) in series.

9. The control circuit of claim 8, wherein, The first frequency dividing circuit (40) and the second frequency dividing circuit (50) have different frequency dividing coefficients.

10. An electronic device, comprising: Comprising: A control circuit for constant effective value control as claimed in any one of claims 1 to 9.

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