A low-voltage high-order compensated bandgap reference voltage source

Abstract

The present invention discloses a low-voltage high-order compensated bandgap reference voltage source, belonging to the technical field of analog integrated circuits. The low-voltage high-order compensated bandgap reference voltage source includes a first-order multi-stage adjustable temperature compensation circuit, a high-order temperature compensation circuit, a step-down circuit, and a current-voltage conversion circuit. The first-order multi-stage adjustable temperature compensation circuit is used to generate a current with a relatively large temperature drift coefficient; the high-order temperature compensation circuit is used to compensate the current with a relatively large temperature drift coefficient generated by the first-order multi-stage adjustable temperature compensation circuit; the step-down circuit is used to extract the current flowing through the BJT in the first-order multi-stage adjustable temperature compensation circuit; and the voltage conversion circuit is used to convert the first-order compensation circuit and the high-order temperature compensation circuit into the required voltage. The present invention introduces a high-order temperature compensation circuit and a step-down circuit for the temperature drift characteristic curve and the voltage characteristic of the BJT, which can not only achieve the characteristic of low temperature drift under a low power supply voltage, but also ensure the stability of the overall circuit.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and mainly relates to a low-voltage high-order compensated bandgap reference voltage source. Background Art

[0002] Chips in different electronic products are composed of different modules, each with specific functions, and together they meet the requirements of the product. The bandgap reference circuit module is one of the most important basic modules in the chip, and its main function is to generate a constant DC voltage. Ideally, the reference circuit module is not affected by the operating voltage, load current, temperature, time, or other interferences. However, in essence, the passive and active components in the circuit are affected by external factors such as current, temperature, and voltage, and their device parameters will change, affecting the performance of the reference circuit and ultimately the performance of the entire chip. Therefore, it is of great significance to study high-performance bandgap reference circuits.

[0003] Research on bandgap references at home and abroad is diverse. With the development of Moore's law, the feature size of devices has shrunk, the threshold voltage has decreased, and the power supply voltage of the circuit has also gradually decreased. In order to meet the requirements of different electronic devices, a large number of improvement technologies for different performance indicators such as temperature coefficient, power supply rejection ratio, and power consumption have been proposed.

[0004] Currently, the structures of bandgap references are mainly divided into four types. The first is the Widlar bandgap reference structure, which is difficult to ensure the stability of the BJT collector current, is greatly affected by temperature, and at the same time, the power supply voltage will also have a great disturbance on the output voltage, affecting the output accuracy. The second is the Kujik bandgap reference structure, which introduces an operational amplifier, and the input terminal of the asymmetric operational amplifier will introduce a non-ideal factor of offset voltage, and the offset voltage usually increases the error of the output voltage. The third is the Brokaw bandgap reference structure, which also has the existence of offset voltage. The fourth is the CMOS bandgap reference structure, which uses multiple branches, increasing the area consumption of the chip. Summary of the Invention

[0005] Aiming at some problems of the existing bandgap reference voltage source, such as high voltage, low accuracy, and large offset, the present invention designs a low-voltage high-order compensated bandgap reference voltage source, which uses the design of NPN transistors to reduce the offset and noise amplification of the amplifier, and at the same time avoids the influence of the amplifier offset on the output accuracy. The virtual short characteristic of the amplifier is used to improve the matching of the circuit and reduce the source-drain mismatch of the transistors. In addition, the voltage across the BJT is reduced by reducing the current flowing through the BJT through a buck circuit, so as to realize the normal operation of the circuit under low power supply voltage and achieve the purpose of low power consumption.

[0006] To achieve the above object, the solution of the present invention is:

[0007] A low-voltage high-order compensated bandgap reference voltage source includes a first-order multi-stage adjustable temperature compensation circuit, a high-order temperature compensation circuit, a step-down circuit, and a current-voltage conversion circuit; where:

[0008] The first-order multi-stage adjustable temperature compensation circuit is used to generate a positive temperature coefficient current I PTAT1 and a first negative temperature coefficient current I CTAT1 ;

[0009] The high-order temperature compensation circuit is used to generate a second negative temperature coefficient current I CTAT2 to compensate for the temperature coefficients of I PTAT1 and I CTAT1 generated by the first-order multi-stage adjustable temperature compensation circuit;

[0010] The step-down circuit is used to reduce the voltage of the transistor BJT in the first-order multi-stage adjustable temperature compensation circuit and ensure its stability;

[0011] The voltage conversion circuit is used to combine the I PTAT1 and I CTAT1 generated by the first-order multi-stage adjustable temperature compensation circuit and the I CTAT2 generated by the high-order temperature compensation circuit, and then convert it into the required reference voltage V REF for output.

[0012] As a preferred technical solution of the present invention: The first-order multi-stage adjustable temperature compensation circuit includes an amplifier A1, an amplifier A2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a bipolar PNP transistor Q1, a bipolar PNP transistor Q2, a bipolar PNP transistor Q3, a bipolar PNP transistor Q4, a bipolar PNP transistor Q5, a unipolar PMOS transistor MP3, a unipolar PMOS transistor MP4, a unipolar PMOS transistor MP5, a unipolar PMOS transistor MP6, and a unipolar PMOS transistor MP7, where;

[0013] The positive input terminal of A1 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP6, and the output terminal is connected to the base of Q3 and one end of R1;

[0014] The positive input terminal of A2 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP3, and the output terminal is connected to the bases of Q5 and Q3;

[0015] The base of Q1 is connected to the other end of R1, the emitter is connected to one end of R2, and the collector is connected to the drain of MP6;

[0016] The base of Q2 is connected to the other end of R2, the emitter is connected to one end of R3, and the collector is connected to the drain of MP7;

[0017] The base of Q3 is connected to the output terminal of A1, the emitter is connected to one end of the base of Q4, and the collector is connected to the drain of MP5;

[0018] The emitter of Q4 is grounded to GND, and the collector is connected to the drain of MP4;

[0019] The base of Q5 is connected to the base of Q3, the emitter is connected to one end of R4, and the collector is connected to the drain of MP3;

[0020] The source of MP3 is connected to VDD;

[0021] The source of MP4 is connected to VDD, and the gate is connected to the gate of the unipolar PMOS transistor MP5;

[0022] The source of MP5 is connected to VDD, and the gate is connected to the gate of MP6;

[0023] The source of MP6 is connected to VDD, and the gate is connected to the gate of MP7;

[0024] The source of MP7 is connected to VDD;

[0025] The other end of resistor R3 is connected to GND; the other end of resistor R4 is connected to GND.

[0026] As a preferred technical solution of the present invention: the high-order temperature compensation circuit includes an amplifier A5 and a resistor R5, wherein:

[0027] The positive input terminal of A5 is connected to the drain of MP5, the negative input terminal is connected to the output terminal of A5, and the output terminal is connected to one end of R5;

[0028] The other end of R5 is used as the output of the high-order temperature compensation circuit. As a preferred technical solution of the present invention: the current-voltage conversion circuit includes a unipolar PMOS transistor MP10, a unipolar PMOS transistor MP11, a resistor R6, and a resistor R7, wherein:

[0029] The source of MP10 is connected to VDD, the drain is connected to the drain of MP11, and the gate is connected to the gate of MP3;

[0030] The source of MP11 is connected to VDD, the drain is connected to the other end of R5 and one end of R6, and the gate is connected to the gate of MP8;

[0031] The other end of R6 is connected to one end of R7; the other end of R7 is connected to GND; the common end of R6 and R7 is the reference voltage output terminal.

[0032] As a preferred technical solution of the present invention: the step-down circuit includes amplifier A3, amplifier A4, unipolar PMOS transistor MP1, unipolar PMOS transistor MP2, unipolar PMOS transistor MP8, unipolar PMOS transistor MP9, unipolar NMOS transistor MN1, unipolar NMOS transistor MN2, unipolar NMOS transistor MN3, unipolar NMOS transistor MN4, unipolar NMOS transistor MN5, where:

[0033] The positive input terminal of A3 is connected to the source of MP2, and the negative input terminal is connected to the drain of MP3;

[0034] The source of MP1 is connected to VDD, the drain is connected to the source of MP2, and the gate is connected to the gate of MP3;

[0035] The drain of MP2 is connected to the drain of MN1, and the gate is connected to the output terminal of A3;

[0036] The source of MP8 is connected to VDD, the drain is connected to the source of MP9, and the gate is connected to the gate of MP7;

[0037] The drain of MP9 is connected to the drain of MN5, and the gate is connected to the output terminal of A4;

[0038] The source of MN1 is connected to ground GND, and the drain and gate are connected;

[0039] The source of MN2 is connected to ground GND, the drain is connected to the collector of Q5 and the negative input terminal of A3, and the gate is connected to the gate of MN1;

[0040] The source of MN3 is connected to ground GND, the drain is connected to the collectors of Q3 and Q4, and the gate is connected to the gate of MN4;

[0041] The source of MN4 is connected to ground GND, the drain is connected to the collectors of Q1 and Q2, and the gate is connected to the gate of MN5;

[0042] The source of MN5 is connected to ground GND, the drain is connected to the drain of MP9, and the gate is connected to the drain.

[0043] Compared with the prior art, the significant advantages of the present invention are:

[0044] The present invention designs and implements a low-voltage high-order compensated bandgap reference voltage source, which adopts a first-order multi-stage adjustable temperature compensation circuit, a high-order temperature compensation circuit, a step-down circuit, and a current-voltage conversion circuit; first, the first-order multi-stage adjustable temperature compensation circuit is used to generate a positive temperature coefficient current I PTAT1 and a negative temperature coefficient current I CTAT1 ; then, a negative temperature coefficient current I CTAT2To compensate the temperature coefficient of the current generated by the first-order multi-stage adjustable temperature compensation circuit; at the same time, a buck circuit is used to extract the current flowing through the transistor BJT in the first-order multi-stage adjustable temperature compensation circuit, so that the BJT operates at a very low V be voltage and realizes stable and normal operation under low power supply voltage. The present invention effectively solves the problems of high power supply voltage, large temperature drift coefficient, and low output accuracy of the traditional bandgap reference circuit, avoids the use of the offset cancellation module circuit, simplifies the circuit structure, and realizes normal operation under a 0.9V power supply voltage, achieving the purpose of low power consumption. Brief Description of the Drawings

[0045] Figure 1 is the main block diagram of a low-voltage high-order compensation bandgap reference voltage source of the present invention;

[0046] Figure 2 is the structural schematic diagram of a low-voltage high-order compensation bandgap reference voltage source of the present invention;

[0047] Figure 3 is the simulation diagram of the circuit temperature drift coefficient;

[0048] Figure 4 is the simulation diagram of the power supply rejection ratio;

[0049] Figure 5 is the simulation diagram of the circuit offset voltage. Detailed Embodiment

[0050] The following further details the specific embodiments of the present invention in conjunction with the accompanying drawings of the specification.

[0051] As Figure 1 shown, a low-voltage high-order compensation bandgap reference voltage source designed by the present invention includes a first-order multi-stage adjustable temperature compensation circuit, a high-order temperature compensation circuit, a buck circuit, and a current-voltage conversion circuit. The first-order multi-stage adjustable temperature compensation circuit is used to generate a positive temperature coefficient current I PTAT1 and a negative temperature coefficient current I CTAT1 ; the high-order temperature compensation circuit generates a negative temperature coefficient current I CTAT2 , which is used to compensate the temperature coefficient of the current generated by the first-order multi-stage adjustable temperature compensation circuit; the buck circuit is used to extract the current flowing through the transistor BJT in the first-order multi-stage adjustable temperature compensation circuit, so that the BJT operates at a very low V be voltage and ensures its stability; the voltage conversion circuit is used to combine the current generated by the first-order multi-stage adjustable temperature compensation circuit and the current generated by the high-order temperature compensation circuit, and then convert it into the required reference voltage V REF for output.

[0052] As Figure 2As shown, in the actual application process of a low-voltage high-order compensated bandgap reference voltage source designed by the present invention, a specific design is carried out on a first-order multi-stage adjustable temperature compensation circuit, including amplifier A1, amplifier A2, resistor R1, resistor R2, resistor R3, resistor R4, bipolar PNP transistor Q1, bipolar PNP transistor Q2, bipolar PNP transistor Q3, bipolar PNP transistor Q4, bipolar PNP transistor Q5, unipolar PMOS transistor MP3, unipolar PMOS transistor MP4, unipolar PMOS transistor MP5, unipolar PMOS transistor MP6, unipolar PMOS transistor MP7, where;

[0053] The positive input terminal of amplifier A1 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP6, and the output terminal is connected to the base of Q3 and one end of resistor R1;

[0054] The positive input terminal of amplifier A2 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP3, and the output terminal is connected to the bases of Q5 and Q3;

[0055] The base of bipolar PNP transistor Q1 is connected to one end of resistor R1, the emitter is connected to one end of resistor R2, and the collector is connected to the drain of MP6;

[0056] The base of bipolar PNP transistor Q2 is connected to one end of resistor R2, the emitter is connected to one end of resistor R3, and the collector is connected to the drain of MP7;

[0057] The base of bipolar PNP transistor Q3 is connected to one end of resistor R1, the emitter is connected to one end of resistor R2, and the collector is connected to the drain of MP5;

[0058] The base of bipolar PNP transistor Q4 is connected to the emitter of Q3, the emitter is grounded to GND, and the collector is connected to the emitter of MP4;

[0059] The base of bipolar PNP transistor Q5 is connected to the base of Q3, the emitter is connected to one end of resistor R4, and the collector is connected to the drain of MP3;

[0060] The source of unipolar PMOS transistor MP3 is connected to VDD, the drain is connected to the collector of Q5, and the gate is connected to the gate of MP11;

[0061] The source of unipolar PMOS transistor MP4 is connected to VDD, the drain is connected to the collector of Q4, and the gate is connected to the gate of unipolar PMOS transistor MP5;

[0062] The source of unipolar PMOS transistor MP5 is connected to VDD, the drain is connected to the collector of Q3, and the gate is connected to the gate of MP6;

[0063] The source of the unipolar PMOS transistor MP6 is connected to VDD, the drain is connected to the collector of Q1, and the gate is connected to the gate of MP7;

[0064] The source of the unipolar PMOS transistor MP7 is connected to VDD, the drain is connected to the collector of Q2, and the gate is connected to the gate of MP8;

[0065] One end of the resistor R1 is connected to the output terminal of the amplifier A1, and the other end is connected to the base of Q1; one end of the resistor R2 is connected to the emitter of Q1, and the other end is connected to the base of Q2; one end of the resistor R3 is connected to the emitter of Q2, and the other end is connected to GND; one end of the resistor R4 is connected to the emitter of Q5, and the other end is connected to GND.

[0066] As Figure 2 shown, the present invention not only proposes a specific design for the first-order multi-stage adjustable temperature compensation circuit, but also designs a specific circuit structure for the buck circuit. The buck circuit includes an amplifier A3, an amplifier A4, a unipolar PMOS transistor MP1, a unipolar PMOS transistor MP2, a unipolar PMOS transistor MP8, a unipolar PMOS transistor MP9, a unipolar NMOS transistor MN1, a unipolar NMOS transistor MN2, a unipolar NMOS transistor MN3, a unipolar NMOS transistor MN4, and a unipolar NMOS transistor MN5, where:

[0067] The positive input terminal of the amplifier A3 is connected to the source of MP2, and the negative input terminal is connected to the drain of MP3 and the negative input terminal of the amplifier A2;

[0068] The source of the unipolar PMOS transistor MP1 is connected to VDD, the drain is connected to the source of MP2, and the gate is connected to the gate of MP3;

[0069] The source of the unipolar PMOS transistor MP2 is connected to the drain of MP1, the drain is connected to the drain of MN1, and the gate is connected to the output terminal of A3;

[0070] The source of the unipolar PMOS transistor MP8 is connected to VDD, the drain is connected to the source of MP9, and the gate is connected to the gate of MP7;

[0071] The source of the unipolar PMOS transistor MP9 is connected to the drain of MP8, the drain is connected to the drain of MN5, and the gate is connected to the output terminal of A4;

[0072] The source of the unipolar NMOS transistor MN1 is connected to the ground GND, and the drain and the gate are connected together and connected to the gate of MN2;

[0073] The source of the unipolar NMOS transistor MN2 is connected to the ground GND, the drain is connected to the collector of Q5 and the negative input terminal of the amplifier A3, and the gate is connected to the gate of MN1;

[0074] The source of the unipolar NMOS transistor MN3 is connected to the ground GND, the drain is connected to the collectors of Q3 and Q4, and the gate is connected to the gate of MN4;

[0075] The source of the unipolar NMOS transistor MN4 is connected to the ground GND, the drain is connected to the collectors of Q1 and Q2, and the gate is connected to the gate of MN5;

[0076] The source of the unipolar NMOS transistor MN5 is connected to the ground GND, the drain is connected to the drain of MP9, and the gate is connected to the drain.

[0077] As Figure 2 shown, in the actual application process of the low-voltage high-order compensated bandgap reference voltage source designed by the present invention, specific designs are carried out for the high-order temperature compensation circuit and the current-voltage conversion circuit.

[0078] The high-order temperature compensation circuit includes an amplifier A5 and a resistor R5, where:

[0079] The positive input terminal of the amplifier A5 is connected to the drain of MP5, the negative input terminal is connected to the output terminal of A5, and the output terminal is connected to one end of R5;

[0080] The other end of the resistor R5 is connected to the drain of MP11.

[0081] The current-voltage conversion circuit includes a unipolar PMOS transistor MP10, a unipolar PMOS transistor MP11, a resistor R6, and a resistor R7, where:

[0082] The source of the unipolar PMOS transistor MP10 is connected to VDD, the drain is connected to the drain of MP11, and the gate is connected to the gate of MP3;

[0083] The source of the unipolar PMOS transistor MP11 is connected to VDD, the drain is connected to one end of R6, and the gate is connected to the gate of MP8;

[0084] The other end of the resistor R6 is connected to one end of R7; the other end of R7 is connected to GND; the common end of R6 and R7 is the reference voltage output terminal.

[0085] The main innovation points of the present invention are: (1) By adjusting the resistors R1, R2, and R3 in the first-order multi-stage adjustable temperature compensation circuit, the positive temperature coefficient current I is trimmed PTAT1;(2) The virtual short characteristics of amplifiers A1 and A2 and the design of NPN transistors in the first-order multi-stage adjustable temperature compensation circuit can increase the matching between current mirrors and reduce the mismatch between the source and drain of MOS transistors; (3) Through the buck circuit, the current flowing through the BJT is extracted according to a certain current ratio, and finally the current flowing through the BJT is only (1 - a)I PTAT1 and (1 - b)I CTAT1 , all the triodes in the circuit achieve a very low V be , and the overall circuit can operate normally at a relatively low power supply voltage.

[0086] As Figure 3 shown is the simulation diagram of the temperature drift coefficient of the circuit. In the temperature range of -45°C to 125°C, when the output voltage is 541mv, the output voltage fluctuates by 546μV, and the corresponding temperature drift coefficient is 5.9PPM / °C.

[0087] As Figure 4 shown is the simulation diagram of the power supply rejection ratio of the overall circuit. It can be seen that at 1KHz, the corresponding power supply rejection ratio is 56dB, and at 100KHz, the power supply rejection ratio is 53dB.

[0088] As Figure 5 shown is the simulation diagram of the offset voltage of the circuit. It can be seen that the offset voltage at the output end of the circuit is 8.9mv under one sigma.

[0089] In the case of a power supply voltage of 0.9V, a temperature range of -45°C to 125°C, and an output voltage VREF = 541mv, the temperature drift coefficient of the present invention can reach 5.9PPM / °C. Compared with the case without the buck circuit, the overall circuit needs to operate normally at a power supply voltage of 1.3V. This circuit only needs to add two branches to achieve normal operation at a power supply voltage of 0.9V, greatly reducing the power consumption of the circuit; when the power supply voltage is 0.9V, the power consumption is 26.324μW. When the buck circuit is not added, at a power supply voltage of 1.3V, the required power consumption is 37.492μW. In summary, the present invention effectively solves the problems of high power supply voltage, large temperature drift coefficient, and low output accuracy of traditional bandgap reference circuits, avoids the use of offset cancellation module circuits, simplifies the circuit structure, and achieves normal operation at a power supply voltage of 0.9V, achieving the purpose of low power consumption.

[0090] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A low-voltage high-order compensated bandgap reference voltage source, characterized in that, The bandgap reference voltage source includes a first-order multi-stage adjustable temperature compensation circuit, a high-order temperature compensation circuit, a step-down circuit, and a current-voltage conversion circuit; where: The first-order multi-stage adjustable temperature compensation circuit is used to generate a positive temperature coefficient current I PTAT1 and a first negative temperature coefficient current I CTAT1 ; The high-order temperature compensation circuit is used to generate a second negative temperature coefficient current I CTAT2 , so as to compensate the temperature coefficients of I PTAT1 and I CTAT1 generated by the first-order multi-stage adjustable temperature compensation circuit; The step-down circuit is used to reduce the voltage of the transistor BJT in the first-order multi-stage adjustable temperature compensation circuit and ensure its stability; The voltage conversion circuit is used to combine I generated by the first-order multi-stage adjustable temperature compensation circuit PTAT1 , I CTAT1 and I generated by the high-order temperature compensation circuit CTAT2 , and then convert them into the required reference voltage V REF for output; The first-order multi-stage adjustable temperature compensation circuit includes amplifier A1, amplifier A2, resistor R1, resistor R2, resistor R3, resistor R4, bipolar PNP transistors Q1, Q2, Q3, Q4, Q5, unipolar PMOS transistors MP3, MP4, MP5, MP6, MP7, where; The positive input terminal of A1 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP6, and the output terminal is connected to the base of Q3 and one end of R1; The positive input terminal of A2 is connected to the drain of MP5, the negative input terminal is connected to the gate and drain of MP3, and the output terminal is connected to the bases of Q5 and Q3; The base of Q1 is connected to the other end of R1, the emitter is connected to one end of R2, and the collector is connected to the drain of MP6; The base of Q2 is connected to the other end of R2, the emitter is connected to one end of R3, and the collector is connected to the drain of MP7; The base of Q3 is connected to the output terminal of A1, the emitter is connected to one end of the base of Q4, and the collector is connected to the drain of MP5; The emitter of Q4 is grounded to GND, and the collector is connected to the drain of MP4; The base of Q5 is connected to the base of Q3, the emitter is connected to one end of R4, and the collector is connected to the drain of MP3; The source of MP3 is connected to VDD; The source of MP4 is connected to VDD, and the gate is connected to the gate of unipolar PMOS transistor MP5; The source of MP5 is connected to VDD, and the gate is connected to the gate of MP6; The source of MP6 is connected to VDD, and the gate is connected to the gate of MP7; The source of MP7 is connected to VDD; The other end of resistor R3 is connected to GND; the other end of resistor R4 is connected to GND; The high-order temperature compensation circuit includes amplifier A5 and resistor R5, where: The positive input terminal of A5 is connected to the drain of MP5, the negative input terminal is connected to the output terminal of A5, and the output terminal is connected to one end of R5; The other end of R5 is used as the output of the high-order temperature compensation circuit.

2. A low-voltage high-order compensated bandgap reference voltage source according to claim 1, characterized in that, The current-voltage conversion circuit includes unipolar PMOS transistors MP10, MP11, resistor R6, resistor R7, where: The source of MP10 is connected to VDD, the drain is connected to the drain of MP11, and the gate is connected to the gate of MP3; The source of MP11 is connected to VDD, the drain is connected to the other end of R5 and one end of R6, and the gate is connected to the gate of MP8; The other end of R6 is connected to one end of R7; the other end of R7 is connected to GND; the common terminal of R6 and R7 is the reference voltage output terminal.

3. A low-voltage high-order compensated bandgap reference voltage source according to claim 2, characterized in that, The step-down circuit includes amplifier A3, amplifier A4, unipolar PMOS transistor MP1, unipolar PMOS transistor MP2, unipolar PMOS transistor MP8, unipolar PMOS transistor MP9, unipolar NMOS transistor MN1, unipolar NMOS transistor MN2, unipolar NMOS transistor MN3, unipolar NMOS transistor MN4, and unipolar NMOS transistor MN5, where: The positive input terminal of A3 is connected to the source of MP2, and the negative input terminal is connected to the drain of MP3; The source of MP1 is connected to VDD, the drain is connected to the source of MP2, and the gate is connected to the gate of MP3; The drain of MP2 is connected to the drain of MN1, and the gate is connected to the output terminal of A3; The source of MP8 is connected to VDD, the drain is connected to the source of MP9, and the gate is connected to the gate of MP7; The drain of MP9 is connected to the drain of MN5, and the gate is connected to the output terminal of A4; The source of MN1 is connected to ground GND, and the drain and gate are connected; The source of MN2 is connected to ground GND, the drain is connected to the collector of Q5 and the negative input terminal of A3, and the gate is connected to the gate of MN1; The source of MN3 is connected to ground GND, the drain is connected to the collectors of Q3 and Q4, and the gate is connected to the gate of MN4; The source of MN4 is connected to ground GND, the drain is connected to the collectors of Q1 and Q2, and the gate is connected to the gate of MN5; The source of MN5 is connected to ground GND, the drain is connected to the drain of MP9, and the gate is connected to the drain.

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