An apparatus and method for accelerating computing with a memory-compute integrated architecture

Abstract

The present invention relates to a device and method for accelerating calculations using a memory-computation integrated structure. The memory-computation integrated structure calculation acceleration device includes: an adjustable delay unit, a first sample-and-hold channel, a second sample-and-hold channel, a first comparison channel, a second comparison channel, and a logic processing unit. The input ends of the first sample-and-hold channel and the second sample-and-hold channel are both connected to the output end of the addition circuit; the first comparison channel and the second comparison channel are respectively connected to the first sample-and-hold channel and the second sample-and-hold channel; the logic processing unit is connected to the first comparison channel and the second comparison channel. By detecting the calculation result signal, it is determined whether the circuit has reached a steady state, and the calculation period is adaptively controlled to achieve the purpose of accelerating calculations.

Description

Technical Field

[0001] The present invention relates to an artificial intelligence computing dedicated integrated circuit based on a memory - in - computing structure, and particularly to a device and method for accelerating computing with a memory - in - computing structure. Background Art

[0002] An artificial intelligence computing dedicated integrated circuit based on a memory - in - computing structure is an important technology in the field of artificial intelligence hardware computing and has a wide range of application backgrounds. There is an analog peripheral auxiliary circuit in the arithmetic circuit of the memory - in - computing structure. The parasitic effects in the analog circuit limit the operation speed of the arithmetic circuit. The greater the change in the input signal of the arithmetic circuit, the longer the response time of the arithmetic circuit, and vice versa. The response time directly determines the operation speed of the circuit.

[0003] Generally, a clock signal with a fixed period is set as the reference signal for the arithmetic circuit. The period depends on the response time of the arithmetic circuit when the input signal changes maximally. When the input signal changes little, the computing circuit wastes time during the computing period, and increasing the computing frequency will seriously reduce the accuracy of the computing result. Summary of the Invention

[0004] Based on this, in view of the above problems, it is necessary to propose a device and method for accelerating computing with a memory - in - computing structure to improve the computing speed of the computing circuit while ensuring accuracy.

[0005] A device for accelerating computing with a memory - in - computing structure includes:

[0006] An adjustable delay unit for delaying the clock signal, including a first clock signal input terminal and a first delayed clock signal output terminal. The first clock signal input terminal is used to receive the clock signal; the first delayed clock signal output terminal is used to output the delayed clock signal.

[0007] A signal feature extraction unit includes a plurality of signal input terminals and a signal output terminal. The plurality of signal input terminals are used to receive a plurality of operation result signals of the arithmetic circuit; the output terminal of the signal feature extraction unit is used to output an output signal containing the response features of the plurality of operation result signals of the memory - in - computing arithmetic circuit.

[0008] A first sample - and - hold channel includes a second clock signal input terminal, a first signal input terminal, and a first sample - and - hold output terminal. The second clock signal input terminal is used to receive the clock signal; the first signal input terminal is used to receive a first input signal; the first sample - and - hold output terminal is used to output the first input signal when the clock signal is at a high (low) level, and output the instantaneous value of the first input signal at the moment when the clock signal is at the falling (rising) edge when the clock signal is at a low (high) level.

[0009] The second sample-and-hold channel includes a third clock signal input terminal, a second signal input terminal, and a second sample-and-hold output terminal. The third clock signal input terminal is connected to the adjustable delay unit to receive the delayed clock signal from the output terminal of the first delayed clock signal; the second signal input terminal is used to receive a second input signal; the second sample-and-hold output terminal is used to output the second input signal when the clock signal is at a high (low) level, and output the instantaneous value of the second input signal at the moment when the clock signal is at the falling (rising) edge when the clock signal is at a low (high) level.

[0010] The first comparison channel includes a first comparison input terminal, a second comparison input terminal, and a first comparison output terminal. The first comparison input terminal is connected to the first sample-and-hold output terminal, the second comparison input terminal is connected to the second sample-and-hold output terminal, and the first comparison output terminal is used to output the comparison result of the input signals at the first comparison input terminal and the second comparison input terminal.

[0011] The second comparison channel includes a third comparison input terminal, a fourth comparison input terminal, and a second comparison output terminal. The third comparison input terminal is connected to the first sample-and-hold output terminal, the fourth comparison input terminal is connected to the second sample-and-hold output terminal, and the second comparison output terminal is used to output the comparison result of the input signals at the second comparison input terminal and the first comparison input terminal.

[0012] The logic processing unit includes a first logic input terminal, a second logic input terminal, a fourth clock signal input terminal, a fifth clock signal input terminal, and a first logic processing output terminal. The first logic input terminal and the second logic input terminal are respectively connected to the first comparison output terminal and the second comparison output terminal; the fourth clock signal input terminal is used to receive the clock signal; the fifth clock signal input terminal is connected to the output terminal of the first delayed clock signal; the first logic output terminal is connected to the output terminal; the output signal of the first logic output terminal will be saved for one clock cycle.

[0013] When the clock signal and the output signal of the first delayed clock output terminal are at a low (high) level and the output signal of the first comparison output terminal or the second comparison output terminal is at a high (low) level at the same time, the output of the first logic output terminal is at a high level.

[0014] When the clock signal or the output signal of the first delayed clock output terminal is at a high level and the output signal of the first logic output terminal was at a high level in the previous clock cycle, the output of the first logic output terminal is at a high level.

[0015] Output terminal.

[0016] In one embodiment, the output signal of the signal feature extraction unit can unify the response time of each output signal link of the arithmetic circuit, and the unified response time is determined by the signal link with the longest response time; the signal feature extraction unit can superimpose and amplify the voltage signal amplitude during the steady-state establishment process to facilitate the comparison between the first comparison channel and the second comparison channel.

[0017] In one embodiment, the first sample-and-hold channel consists of a first gate voltage bootstrap switch and a first sampling capacitor;

[0018] The second sample-and-hold channel consists of a second gate voltage bootstrap switch and a second sampling capacitor.

[0019] When both the clock signal and the delayed clock signal are at a low level, the sample-and-hold channel enters the hold state, and the hold value is the output value of the calculation unit at the falling edge of the clock signal and the delayed clock signal;

[0020] In one embodiment, the first comparison channel includes a first comparator and a second comparator, and the output terminal of the first comparator is connected to the input terminal of the second comparator;

[0021] The second comparison channel includes a third comparator and a fourth comparator, and the output terminal of the third comparator is connected to the input terminal of the fourth comparator.

[0022] Judge whether the output signal of the calculation unit is in a steady state according to the signal after the output value of the sample-and-hold channel passes through the comparison channel;

[0023] In one embodiment, the logic processing unit includes:

[0024] A combinational logic unit, including basic logic gate circuits, is connected to the first comparison output terminal, the second comparison output terminal, the first delayed clock signal output terminal and the clock signal;

[0025] The clock signal and the delayed clock signal pass through the combinational logic unit to obtain a first hold flag signal. The first hold flag signal is at a high level only when both the first sample-and-hold channel and the second sample-and-hold channel are in the hold state. The first hold flag signal is ANDed with the output signal of the comparison channel to filter out the invalid information of the sample-and-hold channel during the sampling stage to obtain a first output signal;

[0026] A sequential logic unit, including basic flip-flop circuits, stores the value of the first output signal in a cycle of the clock signal to obtain a second output signal; the first output signal is ANDed with the second output signal to obtain the output signal of the first logic output terminal.

[0027] This application also provides a memory-computation integrated structure, including:

[0028] The device for accelerating calculation with the in-memory computing structure as described above;

[0029] The ADC circuit includes a sampling pulse input terminal, a sampling completion signal output terminal, and a signal acquisition terminal.

[0030] The sampling pulse input terminal is connected to the output terminal of the above-mentioned device for accelerating calculation with the in-memory computing structure, and is used to receive the sampling pulse signal;

[0031] The sampling completion signal output terminal is connected to the DAC circuit, and is used to output a sampling completion pulse signal after the sampling ends;

[0032] The signal acquisition terminal is connected to the signal feature extraction unit, and is used to acquire the output result signal of the arithmetic circuit;

[0033] The DAC circuit includes a conversion pulse input terminal and a multi-channel analog voltage output terminal.

[0034] The conversion pulse input terminal is used to receive the acquisition completion pulse signal, and the multi-channel analog voltage output terminal is used to output analog signals corresponding to multi-channel digital signals;

[0035] The arithmetic circuit includes multiple analog signal input terminals and multiple result output terminals. The multiple analog signal input terminals are connected to the DAC circuit and are used to receive the analog signals after digital signal conversion; the multiple result output terminals are connected to the ADC circuit and are used for ADC sampling output;

[0036] In one embodiment, the sampling clock signal of the ADC circuit is provided by the above-mentioned device for accelerating calculation with the in-memory computing structure.

[0037] In one embodiment, the sampling clock signal of the DAC circuit is provided by the sampling completion signal output terminal of the ADC circuit. It is further characterized in that the DAC circuit includes a main conversion circuit and a data cache unit, and the data cache unit can store the input digital signals of multiple arithmetic circuits.

[0038] This design also provides a method for accelerating calculation with the in-memory computing structure. The acceleration method is applied to the device for accelerating calculation with the in-memory computing structure. The device for accelerating calculation with the in-memory computing structure includes an adjustable delay unit, a signal feature extraction unit, a first sample-and-hold channel, a second sample-and-hold channel, a first comparison channel, a second comparison channel, and a logic processing unit. The input terminals of the first sample-and-hold channel and the second sample-and-hold channel are both connected to the output terminal of the signal feature extraction unit; the first comparison channel and the second comparison channel are respectively connected to the first sample-and-hold channel and the second sample-and-hold channel; the logic processing unit is connected to the first comparison channel and the second comparison channel; wherein, the method includes:

[0039] Set the delay value of the delay unit and the period of the clock signal according to the average response time of the arithmetic circuit, and control the adjustable delay unit to delay the clock signal according to the preset delay value;

[0040] Store a series of binary codes for storing the input signal of the arithmetic circuit in the data buffer unit of the DAC circuit;

[0041] Send a collection completion pulse to the DAC circuit to start the entire circuit and update the data in the data buffer unit at the same time;

[0042] Record the output pulse signal at the output terminal of the sampling completion signal of the ADC circuit;

[0043] Obtain the result of the adaptive calculation of the arithmetic circuit according to the above-recorded signal. Description of the Drawings

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0045] Figure 1 It is a schematic diagram of the memory-computation integrated structure acceleration device in an embodiment;

[0046] Figure 2 It is a timing diagram related to the memory-computation integrated structure acceleration device in an embodiment;

[0047] Figure 3 It is a schematic diagram of the circuit of the sample-and-hold channel in an embodiment;

[0048] Figure 4 It is a schematic diagram of the circuit of the comparison channel in an embodiment;

[0049] Figure 5 It is a schematic diagram of the circuit of the comparison channel in another embodiment;

[0050] Figure 6 It is a schematic diagram of the circuit of the logic processing unit in an embodiment;

[0051] Figure 7 It is a schematic diagram of the overall memory-computation integrated structure and the device of the present invention in an embodiment;

[0052] Figure 8 It is a schematic diagram of the flow of the calculation method of the memory-computation integrated structure in an embodiment. Detailed Embodiments

[0053] The present invention will be further described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0054] To facilitate the understanding of the present invention, in order to make the above objects, features and advantages of the present invention more obvious and understandable. A detailed description of the specific embodiments of the present invention will be made in conjunction with the accompanying drawings. Many details are set forth in the following description in order to fully understand the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. The present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the named technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0056] As Figure 1 shown, an embodiment of the present application provides a device for accelerating calculations with a memory-computation integrated structure. In one embodiment, the device for accelerating calculations with a memory-computation integrated structure includes: an adjustable delay unit 110, a first sample-and-hold channel 120, a second sample-and-hold channel 130, a first comparison channel 140, a second comparison channel 150, a logic processing unit 160, and a signal feature extraction unit 170.

[0057] Among them, the input end of the adjustable delay unit 110 is used to receive the clock signal 1A, and the delay value Dt is set according to the requirements of the actual calculation circuit speed. The output end of the adjustable delay unit 110 is used to output the delayed clock signal 1B after delaying the clock signal by Dt.

[0058] In one embodiment, the delay unit 110 includes a resistor-capacitor inverting delay circuit, a counter, a register, etc. In the embodiment of the present application, the delay unit 110 is a resistor-capacitor inverting delay circuit. According to the actual requirement Dt of the circuit, the resistance values of the resistor and the capacitor are set to obtain a charge-discharge delay time Dt that matches the actual requirement, and then the inverter is used to apply this delay time Dt to the input clock signal 1A to obtain the delayed clock signal 1B. As Figure 2 shown is the relationship between the clock signal 1A and the delayed clock signal 1B.

[0059] The first sample-and-hold channel 120 includes a second clock signal input terminal, a first signal input terminal, and a first sample-and-hold output terminal. The second sample-and-hold channel 130 includes a third clock signal input terminal, a second signal input terminal, and a second sample-and-hold output terminal. The first signal input terminal of the first sample-and-hold channel 120 is connected to the second signal input terminal of the second sample-and-hold channel 130, and both are used to receive the calculation result signal 1C. The second clock signal input terminal of the first sample-and-hold channel 120 is used to receive the clock signal 1A, and samples and holds the calculation result signal 1C according to the logic state of the clock signal 1A. In this embodiment, when the clock signal 1A is at a high level, the first sample-and-hold channel 120 samples the calculation result signal 1C. When the clock signal 1A is at a low level, the second sample-and-hold channel 130 holds the calculation result signal 1C, and the held voltage value is the voltage value of the calculation result signal 1C at the moment when the clock signal 1A is at the falling edge. The sample-and-hold signal 1D is output through the first sample-and-hold output terminal of the first sample-and-hold channel 120.

[0060] The third clock signal input terminal of the second sample-and-hold channel 130 is used to receive the delayed clock signal 1B, and samples and holds the calculation result signal 1C according to the logic state of the clock signal 1B. In this embodiment, when the clock signal 1B is at a high level, the first sample-and-hold channel 130 samples the calculation result signal 1C. When the clock signal 1B is at a low level, the second sample-and-hold channel 130 holds the calculation result signal 1C, and the held voltage value is the voltage value of the calculation result signal 1C at the moment when the clock signal 1B is at the falling edge. The sample-and-hold signal 1E is output through the second sample-and-hold output terminal of the second sample-and-hold channel.

[0061] The delay difference between the clock signal 1A and the delayed clock signal 1B acts on the calculation result signal 1C through the first sample-and-hold channel 120 and the second sample-and-hold channel 130, obtaining different voltage values of the calculation result signal 1C corresponding to different moments. The calculation state of the current circuit can be detected according to the voltage values at different moments.

[0062] In this embodiment, both the first sample-and-hold channel 120 and the second sample-and-hold channel 130 are composed of a gate bootstrapping switch and a sampling capacitor C2 as shown in Figure 3 The clock signal 1A and the delayed clock signal 1B of the first sample-and-hold channel 120 and the second sample-and-hold channel 130 respectively control Figure 3 the switches SW1 - SW5 in

[0063] In this embodiment, the first sample-and-hold channel 120 is composed of as shown in Figure 3It consists of the gate voltage bootstrap switch and the sampling capacitor C2 shown. The input signal at the clock signal input terminal of the first sample and hold channel 120 is the clock signal 1A, and this signal directly controls Figure 3 the conduction or cutoff of SW1 to SW5 in Figure 3 . When the clock signal 1A is at a low level, the switches SW1 and SW2 are conducting to charge the capacitor C1, SW3 and SW4 are cutoff, SW5 is conducting, and the N1 transistor is in the cutoff state, and the charge amount on C2 is maintained. When the clock signal 1A is at a high level, the switches SW1, SW2, and SW5 are cutoff, SW4 and SW3 are conducting. At this time, the gate-source voltage on N1 is the power supply voltage on the capacitor C1, the NMOS transistor is conducting, and the voltage on the sampling capacitor C2 starts to follow the change of VIN. The difference between the second sample and hold channel 130 and the first sample and hold channel 120 is that the clock signals input at the clock input terminals are different. The clock input of the second sample and hold channel is the delayed clock signal 1B. In this embodiment, a form of parallel connection of a P-type gate voltage bootstrap switch and an N-type gate voltage bootstrap switch can also be used as the sample and hold channel, and its specific implementation method is the same as the foregoing, and will not be elaborated here one by one.

[0064] It should be noted that the structural compositions of the first sample and hold channel 120 and the second sample and hold channel 130 are the same, so as to ensure that the calculation result signal 1C sampled and held by the first sample and hold channel 120 and the second sample and hold channel 130 has the same degree of distortion.

[0065] The first comparison channel 140 includes a first comparison input terminal, a second comparison input terminal, and a first comparison output terminal. The first comparison input terminal is used to receive the sample and hold signal 1D output from the first sample and hold output terminal of the first sample and hold channel 120, the second comparison input terminal is used to receive the sample and hold signal 1E output from the second sample and hold output terminal of the second sample and hold channel 130, and the first comparator output terminal is used to output the comparison result of the sample and hold signal 1D and the sample and hold signal 1E. When the sample and hold signal 1D is greater than the sample and hold signal 1E, the comparison signal 1F output from the first comparison output terminal is at a high level. When the sample and hold signal 1D is less than the sample and hold signal 1E, the comparison signal 1F output from the first comparison output terminal is at a low level.

[0066] The second comparison channel 150 includes a third comparison input terminal, a fourth comparison input terminal, and a second comparison output terminal. The third comparison input terminal is used to receive the sample-and-hold signal 1E output from the second sample-and-hold output terminal of the second sample-and-hold channel 130. The fourth comparison input terminal is used to receive the sample-and-hold signal 1D output from the first sample-and-hold output terminal of the first sample-and-hold channel 120. The second comparator output terminal is used to output the comparison result of the sample-and-hold signal 1E and the sample-and-hold signal 1D. When the sample-and-hold signal 1E is greater than the sample-and-hold signal 1D, the comparison signal 1G output from the first comparison output terminal is at a high level. When the sample-and-hold signal 1E is less than the sample-and-hold signal 1D, the comparison signal 1G output from the second comparison output terminal is at a low level.

[0067] The rising process of the calculation result signal 1C can be reflected on the comparison signal 1F through the first comparison channel 140. In this embodiment, by setting an additional second comparison channel 150, it is ensured that the falling process of the calculation result signal 1C can be reflected on the comparison signal 1G. Compared with the first comparison channel 140, the biggest difference in the second comparison channel 150 lies in the processing of the input sample-and-hold signals 1D and 1E. The former treats the sample-and-hold signal 1D as a positive input, while the latter treats the sample-and-hold signal 1D as a negative input.

[0068] In one embodiment, as Figure 4 shown, the first comparison channel 140 is composed of a first-stage comparator 141 and a second-stage comparator 142. Both the first-stage comparator 141 and the second-stage comparator 142 include a positive signal input terminal, a negative signal input terminal, and a comparison result output terminal. When the voltage value at the positive signal input terminal is greater than the voltage value at the negative signal input terminal, the comparison result output terminal outputs a high level; otherwise, it outputs a low level. The positive signal input terminal of the first-stage comparator 141 is connected to the first hold signal input terminal, the negative signal input terminal is connected to the second hold signal input terminal, the comparison result output terminal of the first-stage comparator 141 is connected to the positive input signal input terminal of the second-stage comparator 142, and the negative signal input terminal of the second-stage comparator 142 is connected to the reference voltage 1. The composition structure of the second comparison channel 150 is the same as that of the first comparison channel 140 and will not be elaborated here. The difference from the first comparison channel 140 is that the positive signal input terminal of the first-stage comparator 151 of the second comparison channel 150 is connected to the second hold signal input terminal, and the negative signal input terminal is connected to the first hold signal input terminal.

[0069] In one embodiment, as Figure 5As shown, the first comparison channel 140 and the second comparison channel 150 are composed of a shared first-stage comparator 141 / 151, a second-stage comparator 142, and a second-stage comparator 152. The first-stage comparator 141 / 151 is composed of a differential subtraction circuit, including a first hold signal input terminal, a second hold signal input terminal, and a subtraction signal output terminal. The first hold signal input terminal and the second hold signal input terminal are respectively used to receive the sampled and held signal 1D output by the first sample-and-hold channel 120 and the sampled and held signal 1E of the second sample-and-hold channel 130. Taking R1 = R2 = R3 = R4 = 10 kΩ, the subtraction signal output terminal of the first-stage comparator 141 / 151 is used to output the difference between the output signals of the two hold channels, which is beneficial for the second-stage comparator to make a comparison. It is also possible to take R1 = R4, R2 = R3 and R1 / R2 = k, and use the differential subtraction circuit to amplify the difference between the output signals of the two hold channels by k times, which is beneficial for the downstream comparator to process the signal. The second-stage comparator 142 and the second-stage comparator 152 include a positive signal input terminal, a negative signal input terminal, and a comparison result output terminal. When the voltage value at the positive signal input terminal is greater than the voltage value at the negative signal input terminal, the comparison result output terminal outputs a high level; otherwise, it outputs a low level. The output terminals of the first-stage comparator 141 / 151 are respectively connected to the positive signal input terminal and the negative signal input terminal of the second-stage comparator 142 and the second-stage comparator 152. The negative signal input terminal of the second-stage comparator 142 is connected to the reference voltage 1. When the output signal of the first-stage comparator 141 / 151 is greater than the reference voltage 1, the first-stage comparator 142 outputs a high level. At this time, the held value of the first sample-and-hold channel 120 is greater than the held value of the second sample-and-hold channel 130. The positive signal input terminal of the second-stage comparator 152 is connected to the reference voltage 2. When the output signal of the first-stage comparator 141 / 151 is less than the reference voltage 2, the second-stage comparator 152 outputs a high level. At this time, the held value of the first sample-and-hold channel 120 is less than the held value of the second sample-and-hold channel 130. The outputs of the second-stage comparator 142 and the second-stage comparator 152 respectively represent the rising and falling processes of the calculated output signal 1C during the transient to steady-state process.

[0070] The logic processing unit 160 includes a first logic input terminal, a second logic input terminal, a fourth clock signal input terminal, a fifth clock signal input terminal, and a first logic processing output terminal. The first logic input terminal is used to receive the comparison signal 1F, the second logic input terminal is used to receive the comparison signal 1G, the fourth clock signal input terminal is used to receive the clock signal 1A, and the fifth clock signal input terminal is used to receive the clock signal 1B. The logic processing unit 160 can combine the comparison signal 1F representing the rising information of the calculation result signal 1C and the comparison signal 1G representing the falling information, and filter the outputs of the first sample and hold channel 120 and the second sample and hold channel 130 when they are in the sampling state. When the calculation end signal 1H output from the first logic processing output terminal is at the rising edge, it indicates that the calculation result signal 1C breaks away from the steady state. When the signal 1H output from the first logic processing output terminal is at the falling edge, it indicates that the calculation result signal 1C returns to the steady state.

[0071] In this embodiment, the specific implementation circuit diagram of the logic processing unit 160 is as Figure 6 shown, and it is composed of a clock processing part 161, a comparison result processing part 162, and a D flip-flop 163. The clock processing part 161 is composed of an inverter I1, an inverter I2, and a dual-input AND gate I3. Its function is to take the time period when the clock signal 1A and the delayed clock signal 1B are both at the low level and output it to the comparison result processing part 162 in the form of a high level. This time period is also the time period when the first sample and hold channel 120 and the second sample and hold channel 130 are both in the hold state. The input signals of the first comparison channel 140 and the second comparison channel 150 include both the signals of the first sample and hold channel 120 and the second sample and hold channel 130 when they are in the sampling state and the signals when they are in the hold state. In this embodiment, by adding the clock processing part 161 and the comparison result processing part 162, the output signals of the first sample and hold channel 120 and the second sample and hold channel 130 when they are in the sampling state can be filtered out. The output signal of the comparison result processing part 162 is an intermittent rectangular wave as Figure 2 shown. In order to provide a more reasonable signal form to the downstream circuit, in this embodiment, by adding an additional D flip-flop 163, the comparison output signal 1J of the comparison result processing part 162 as Figure 2 shown can be converted into the calculation end signal 1H as Figure 2 shown and output to the first logic processing output terminal. The clock of the D flip-flop 163 is provided by the delayed clock signal 1B.

[0072] The signal feature extraction unit 170, as Figure 6 and Figure 7 shown, is used to add and sum the multiple branch signals of the arithmetic circuit 23.

[0073] In this embodiment, by adding an additional signal feature extraction unit 170, the response time of each output signal link of the unified arithmetic circuit 23 can be unified. The unified response time is determined by the signal link with the longest response time. In addition, the signal feature extraction unit 170 can also amplify the voltage signal amplitude during the steady-state establishment process, which is beneficial for the first comparison channel 140 and the second comparison channel 150 to make comparisons. In this embodiment, the signal feature extraction unit 170 adopts an adder circuit composed of operational amplifiers, and other circuits capable of completing the response time can also be used.

[0074] As Figure 7 shown, an in-memory computing arithmetic circuit 20 is also provided in an embodiment of the present application. In one embodiment, the in-memory computing arithmetic circuit includes an analog-to-digital conversion (ADC) circuit 21, a digital-to-analog conversion (DAC) circuit 22, an arithmetic circuit 23, and the in-memory computing acceleration device in any of the above embodiments, where

[0075] The ADC circuit 21 includes a sampling pulse input terminal, a signal acquisition terminal, and an acquisition completion input terminal. The sampling pulse input terminal of the ADC circuit 21 is used to receive a sampling enable pulse. When the sampling enable pulse is at the falling edge, the ADC starts sampling. The signal acquisition terminal is used to receive multiple arithmetic result output signals of the arithmetic circuit 23, and the acquisition completion output terminal is used to output an acquisition completion pulse signal.

[0076] The DAC circuit 22 includes a conversion pulse input terminal and an analog voltage output terminal. The conversion pulse input terminal is connected to the acquisition completion output terminal of the ADC circuit 21. When the ADC circuit 21 completes sampling, it will send an acquisition completion pulse signal. The DAC circuit 22 performs digital-to-analog conversion according to the falling edge of the acquisition completion pulse signal and outputs it to the arithmetic circuit 23 through the analog voltage output terminal.

[0077] The arithmetic circuit 23 includes a data input terminal and a result output terminal, and is used to complete matrix multiplication operations, and generally has multiple outputs.

[0078] The in-memory computing structure acceleration computing device includes: an adjustable delay unit 110, a first sample-and-hold channel 120, a second sample-and-hold channel 130, a first comparison channel 140, a second comparison channel 150, and a logic processing unit 160. Among them, the input terminal of the delay unit 110, the clock input terminal of the first sample-and-hold channel 120, and the clock input terminal of the logic processing unit 160 are used to receive clock 1A. The output terminal of the signal feature extraction unit 170 is respectively connected to the first signal input terminal and the second signal input terminal of the first sample-and-hold channel 120 and the second sample-and-hold channel 130. The output terminal of the logic processing unit 160 is connected to the sampling pulse input terminal of the ADC circuit 21.

[0079] In this embodiment, a computing-in-memory acceleration computing device 10 is provided in the computing-in-memory operation circuit. Among them, the first sample-and-hold channel 120 and the second sample-and-hold channel 130 of the computing-in-memory acceleration computing device 10 hold the voltage values of the calculation output signal 1C of the signal feature extraction unit 170 at the specified delay time difference moment. The first comparison channel 140 and the second comparison channel 150 obtain the rising and falling information during the establishment process of the calculation output signal 1C from transient to steady state by comparing the sample-and-hold signal 1D and the sample-and-hold signal 1E. After being processed by the logic processing unit 160, it is output to the ADC circuit 21, and the steady-state detection of the calculation result signal 1C can be completed. After receiving the steady-state signal, the ADC circuit 21 samples the operation circuit result. After the sampling is completed, the DAC circuit 22 is enabled for digital-to-analog conversion to transmit a signal to the operation circuit. By adaptively adjusting the calculation period of the operation unit according to the different response durations of the operation unit 23 under different data inputs, the acceleration of the computing-in-memory operation circuit can be completed. In this embodiment, this device is applied to the operation circuit of a 3*10*10*2 water molecule deep neural network and processes 9,600 groups of data. Under the same result accuracy, the speed of this device is increased by nearly 4 times. If the accuracy requirement is relaxed, the increase is even more. It should be noted that the larger the amount of data processed by the operation circuit, the greater the speed improvement of this device, that is, the more operation time saved by the adaptive processing.

[0080] This application example also provides a method for accelerating the computing-in-memory structure. In one embodiment, this computing-in-memory operation circuit acceleration method is applied to a computing-in-memory acceleration device. As Figure 1 shown, the computing-in-memory structure acceleration computing device includes: an adjustable delay unit 110, a first sample-and-hold channel 120, a second sample-and-hold channel 130, a first comparison channel 140, a second comparison channel 150, and a logic processing unit 160.

[0081] As Figure 8 shown, the computing-in-memory operation circuit acceleration method includes step 802 - step 808. Among them:

[0082] Step 802, set the delay value of the delay unit and the period of the clock signal according to the average response time of the operation circuit, and control the adjustable delay unit to delay the clock signal according to the delay preset value.

[0083] In one embodiment, the delay time DT can be set to 5 ns, the period of the clock signal 1A is 12 ns, and the delayed clock signal 1B is a clock signal with a period of 12 ns obtained by delaying the clock signal 1A by 5 ns. The above two signals are input into the first sample-and-hold channel and the second sample-and-hold channel to obtain the voltage values of the calculation result signal at the t0 moment and the (t0 + 5 ns) moment.

[0084] It should be noted that the structural compositions of the two sample-and-hold channels are the same, so as to ensure that the signals sampled and held by the two sample-and-hold channels have the same degree of distortion of the calculated result signal 1C.

[0085] Step 804: Store a series of binary codes for storing the input signal of the arithmetic circuit in the data buffer unit of the DAC circuit.

[0086] The above binary codes need to be converted into analog input signals of the arithmetic circuit through DAC conversion.

[0087] Step 806: Send a sampling completion pulse to the DAC circuit to start the entire circuit and update the data in the data buffer unit at the same time.

[0088] After starting the circuit, the DAC circuit converts the first binary code stored in the data buffer unit of the DAC circuit into an analog signal and transmits it to the arithmetic circuit. At this time, the first binary code has lost its meaning. Therefore, it is necessary to update the data in the data buffer unit so that the analog signal output next time is the second input signal of the arithmetic circuit.

[0089] Step 808: Record the result of the adaptive calculation of the signal arithmetic circuit according to the output pulse signal recorded at the output signal end of the ADC circuit sampling completion signal.

[0090] The ADC circuit changes the sampling frequency of the result of the arithmetic circuit according to the response time length of the arithmetic circuit, and the DAC circuit changes the conversion frequency of the input signal of the arithmetic circuit according to the response time length of the arithmetic circuit. During the entire operation cycle of the circuit, the ADC and the DAC automatically input and capture signals to the arithmetic circuit, so the obtained is the result of adaptive calculation.

Claims

1. A device for accelerating computing with a memory - in - computing architecture, characterized in that, Comprising: An adjustable delay unit for delaying a clock signal, including a first clock signal input terminal and a first delayed clock signal output terminal, where the first clock signal input terminal is used to receive the clock signal; the first delayed clock signal output terminal is used to output the clock signal after delay; A signal feature extraction unit, including a plurality of signal input terminals and a signal output terminal, where the plurality of signal input terminals are used to receive a plurality of operation result signals of an arithmetic circuit; the output terminal of the signal feature extraction unit is used to output an output signal including the response features of the plurality of operation result signals of the memory - in - computing arithmetic circuit; A first sample - and - hold channel, including a second clock signal input terminal, a first signal input terminal, and a first sample - and - hold output terminal, where the second clock signal input terminal is used to receive the clock signal; the first signal input terminal is connected to the sum signal output terminal of the signal feature extraction unit; the first sample - and - hold output terminal is used to output the first input signal when the clock signal is at a high or low level, and output the instantaneous value of the first input signal at the moment when the clock signal is at a falling or rising edge when the clock signal is at a low or high level; A second sample - and - hold channel, including a third clock signal input terminal, a second signal input terminal, and a second sample - and - hold output terminal, where the third clock signal input terminal is connected to the adjustable delay unit to receive the delayed clock signal of the first delayed clock signal output terminal; the second signal input terminal is connected to the sum signal output terminal of the signal feature extraction unit; the second sample - and - hold output terminal is used to output the second input signal when the clock signal is at a high or low level, and output the instantaneous value of the second input signal at the moment when the clock signal is at a falling or rising edge when the clock signal is at a low or high level; A first comparison channel, including a first comparison input terminal, a second comparison input terminal, and a first comparison output terminal, where the first comparison input terminal is connected to the first sample - and - hold output terminal, the second comparison input terminal is connected to the second sample - and - hold output terminal, and the first comparison output terminal is used to output the comparison result of the input signals of the first comparison input terminal and the second comparison input terminal; A second comparison channel, including a third comparison input terminal, a fourth comparison input terminal, and a second comparison output terminal, where the third comparison input terminal is connected to the first sample - and - hold output terminal, the fourth comparison input terminal is connected to the second sample - and - hold output terminal, and the second comparison output terminal is used to output the comparison result of the input signals of the second comparison input terminal and the first comparison input terminal; A logic processing unit, including a first logic input terminal, a second logic input terminal, a fourth clock signal input terminal, a fifth clock signal input terminal, and a first logic processing output terminal, where the first logic input terminal and the second logic input terminal are respectively connected to the first comparison output terminal and the second comparison output terminal; the fourth clock signal input terminal is used to receive the clock signal; The fifth clock signal input terminal is connected to the first delayed clock signal output terminal; the first logic output terminal is connected to the output terminal; the output signal of the first logic output terminal will be saved for one clock cycle; When the clock signal, the output signal of the first delayed clock output terminal is at a low or high level and the output signal of the first comparison channel output terminal or the second comparison channel output terminal is simultaneously at a high or low level, the output of the first logic output terminal is at a high level; When the clock signal or the output signal of the first delayed clock output terminal is at a high level and the output signal of the first logic output terminal was at a high level in the previous clock cycle, the output of the first logic output terminal is at a high level; Output terminal.

2. The device for accelerating calculation of the memory-computation integrated structure according to claim 1, wherein The output signal of the signal feature extraction unit can unify the response time of each output signal link of the arithmetic circuit, and the unified response time is determined by the signal link with the longest response time; the signal feature extraction unit can superimpose and amplify the voltage signal amplitude during the steady-state establishment process to facilitate the comparison between the first comparison channel and the second comparison channel.

3. The device for accelerating calculation of the memory-computation integrated structure according to claim 1, wherein, The first sample-and-hold channel consists of a first gate voltage bootstrap switch and a first sampling capacitor; the second sample-and-hold channel consists of a second gate voltage bootstrap switch and a second sampling capacitor; when both the clock signal and the delayed clock signal are at a low level, the sample-and-hold channel enters the hold state, and the hold value is the output value of the calculation unit at the falling edge of the clock signal and the delayed clock signal.

4. The device for accelerating computing of the memory-computation integrated structure according to claim 1, wherein The first comparison channel includes a first comparator and a second comparator, and the output terminal of the first comparator is connected to the input terminal of the second comparator; the second comparison channel includes a third comparator and a fourth comparator, and the output terminal of the third comparator is connected to the input terminal of the fourth comparator; it is judged whether the output signal of the calculation unit is in a steady state according to the signal after the output value of the sample-and-hold channel passes through the comparison channel.

5. The device for accelerating calculation of the memory-computation integrated structure according to claim 1, wherein The logic processing unit includes: A combinational logic unit, including basic logic gate circuits, is connected to the first comparison output terminal, the second comparison output terminal, the first delayed clock signal output terminal and the clock signal. The clock signal and the delayed clock signal pass through the combinational logic unit to obtain a first hold flag signal. The first hold flag signal is at a high level only when both the first sample-and-hold channel and the second sample-and-hold channel are in the hold state. The first hold flag signal is ANDed with the output signal of the comparison channel to filter out the invalid information of the sample-and-hold channel during the sampling stage to obtain a first output signal; A sequential logic unit, including basic flip-flop circuits, stores the value of the first output signal in a clock signal period to obtain a second output signal; the second output signal is output to the first logic output terminal.

6. An in-memory computing structure, characterized in that, Including: The device for accelerating calculation of the memory-computation integrated structure according to any one of claims 1-5; An ADC circuit, including a sampling pulse input terminal, a sampling completion signal output terminal and a signal acquisition terminal; wherein, the sampling pulse input terminal is connected to the output terminal of the above-mentioned memory-computation integrated structure accelerating calculation device for receiving a sampling pulse signal; the sampling completion signal output terminal is connected to the DAC circuit for outputting a sampling completion pulse signal after sampling; the signal acquisition terminal is connected to the signal feature extraction unit for acquiring the output result signal of the arithmetic circuit; The DAC circuit includes a conversion pulse input terminal and multiple analog voltage output terminals; the conversion pulse input terminal is used to receive the acquisition completion pulse signal, and the multiple analog voltage output terminals are used to output analog signals corresponding to multiple digital signals; The operation circuit includes multiple analog signal input terminals and multiple result output terminals. The multiple analog signal input terminals are connected to the DAC circuit and are used to receive the analog signals after digital signal conversion; the multiple result output terminals are connected to the ADC circuit and are used for ADC sampling output.

7. The in-memory computing structure according to claim 6, wherein The sampling clock signal of the DAC circuit is provided by the sampling completion signal output terminal of the ADC circuit. It is further characterized in that the DAC circuit includes a main conversion circuit and a data cache unit, and the data cache unit can store the input digital signals of multiple operation circuits.

8. A method for accelerating computing in a computing-in-memory structure, characterized in that Applied to the device according to any one of claims 1-5, wherein the method includes: Setting the delay value of the delay unit and the period of the clock signal according to the average response time of the operation circuit, and controlling the adjustable delay unit to delay the clock signal according to the delay preset value; Storing a series of binary codes for storing the input signals of the operation circuit in the data cache unit of the DAC circuit; Sending an acquisition completion pulse to the DAC circuit to start the entire circuit, and simultaneously updating the data in the data cache unit; Recording the output pulse signal of the sampling completion signal output terminal of the ADC circuit, and obtaining the result of the adaptive calculation of the operation circuit according to the recorded signal.

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