An NVMe command processing method, apparatus, device, and medium

Abstract

This application discloses an NVMe instruction processing method, apparatus, device, and medium, relating to the field of storage hardware technology. The method includes: acquiring currently pending NVMe request instructions in a target transmission queue and determining the instruction type of the NVMe request instruction; if it is a read instruction, sending a data acquisition instruction to the backend so that the backend moves first target data to the embedded system memory; determining the currently used composite queue in the controller and sending a first DMA instruction to the composite queue for moving the first target data from the embedded system memory to the server host memory and a completion instruction indicating the completion of the NVMe request; after the composite queue completes the instruction transfer operation, sending a notification signal to the server host through the controller for processing the completion instruction so that the server host can reclaim the NVMe request. This solution can reduce the latency of the system when processing read instructions and improve read efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage hardware, and particularly relates to an NVMe instruction processing method and device, equipment and medium. BACKGROUND

[0002] Virtualization technology is one of the most critical technologies in the cloud computing era. Through virtualization technology, a server host can provide more, more flexible and secure virtual hardware interfaces to users, thereby improving the utilization of the device. However, the storage virtualization service itself also consumes certain host computing and memory resources. In order to solve this problem, storage hardware virtualization emerges as the times require, and storage hardware virtualization uses embedded hardware devices to provide virtualization storage services to the host side, and unloads the software virtualization service stack to the embedded system, thereby saving the hardware resources of the server host.

[0003] With the continuous development of storage hardware technology, the NVMe (Nonvolatile Memory Express, that is, non-volatile memory host controller interface) protocol gradually becomes mainstream, and most virtualization systems support NVMe virtual disks, and embedded virtualization storage systems are no exception. However, the embedded virtualization storage system itself will also bring additional delay time due to the internal interaction between the storage protocol instruction and data processing flow and the embedded components. Figure 1 It is a structural schematic diagram of an embedded virtualization storage system, according to Figure 1 The embedded storage virtualization system mainly includes a controller and a driver, the storage controller is responsible for TLP (Transaction Layer Packet, transaction layer data packet) packet interaction and DMA (Direct Memory Access, direct memory access) data communication with the server host through the PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) interface; the driver is responsible for NVMe protocol virtualization service and storage data processing. Since the software driver runs on the embedded operating system, when the controller or the backend persistent module completes the corresponding processing, the software driver needs to be rescheduled to process the received task. Referring to Figure 2 , the software driver is scheduled on the embedded system CPU for multiple times to finally complete the I / O instruction. With the increase of virtual devices or the increase of system load, the required scheduling time will also increase accordingly, thereby increasing the delay of I / O instruction processing and reducing the system efficiency.

[0004] In summary, how to reduce the delay of instruction processing in the embedded system to improve the system efficiency is a problem to be solved at present. SUMMARY

[0005] Therefore, the present application aims to provide an NVMe instruction processing method, device, equipment and medium, which can reduce the delay of instruction processing in an embedded system to improve system efficiency. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses an NVMe instruction processing method, comprising:

[0007] obtaining a current NVMe request instruction to be processed in a target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction;

[0008] if the instruction type is a read instruction, sending a data acquisition instruction to a back end, so that the back end moves first target data to an embedded system memory based on the data acquisition instruction;

[0009] determining a composite queue currently used in a controller, and sending a first DMA instruction for moving the first target data from the embedded system memory to a server host memory and a completion instruction representing the completion of the NVMe request to the composite queue;

[0010] after the composite queue completes the instruction moving operation, sending a notification signal for processing the completion instruction to a server host through the controller, so that the server host recycles the NVMe request.

[0011] Optionally, the determination of the composite queue currently to be used in the controller comprises:

[0012] determining a composite queue used by a previous read instruction; wherein the composite queue comprises a first composite queue and a second composite queue;

[0013] if the composite queue used by the previous read instruction is the first composite queue, the second composite queue is used as the composite queue currently used in the controller.

[0014] Optionally, after the analysis of the NVMe request instruction to determine the instruction type of the NVMe request instruction, the method further comprises:

[0015] if the instruction type is a write instruction, a second DMA instruction for moving second target data from a server host memory to an embedded system memory is sent to the first composite queue;

[0016] after a signal for completing the second DMA instruction is obtained, the back end is notified to perform persistent processing on the second target data, and a completion instruction representing the completion of the NVMe request is sent to the second composite queue after the persistent processing is completed.

[0017] after the second composite queue completes the migration operation of the completion instruction, sending, by the controller, a notification signal for processing the completion instruction to a server host, so that the server host recycles the NVMe request.

[0018] Optionally, after the controller sends the notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request, the method further comprises:

[0019] performing, by a server host kernel, recycling processing of the NVMe request, and sending a corresponding recycling success signal to the controller after the recycling processing is completed, so that the controller updates a register head pointer corresponding to the composite queue.

[0020] Optionally, after the controller sends the notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request, the method further comprises:

[0021] performing, by a server host kernel, recycling processing of the NVMe request, and sending a corresponding recycling success signal to the controller after the recycling processing is completed, so that the controller updates a register head pointer corresponding to the second composite queue.

[0022] Optionally, before the target sending queue obtains the current NVMe request instruction to be processed, the method further comprises:

[0023] sending, by the controller, the NVMe request instruction to a target sending queue in a driver, and sending a get instruction to the driver of the embedded system by using a register, so that after the driver obtains the get instruction, the target sending queue obtains the current NVMe request instruction to be processed.

[0024] Optionally, the queue depth of the target sending queue is the same as the queue depth of the composite queue.

[0025] In a second aspect, the application discloses an NVMe instruction processing device applied to a driver in an embedded system, comprising:

[0026] An instruction obtaining module is configured to obtain a current NVMe request instruction to be processed in a target sending queue, and analyze the NVMe request instruction to determine the instruction type of the NVMe request instruction.

[0027] A first data migration module is configured to send a data obtaining instruction to a back end if the instruction type is a read instruction, so that the back end migrates first target data to an embedded system memory based on the data obtaining instruction.

[0028] a second data migration module configured to determine a current composite queue to be used in the controller, and send a first DMA instruction for migrating the first target data from the embedded system memory to the server host memory and a completion instruction for indicating completion of the NVMe request to the composite queue;

[0029] a completion instruction notification module configured to send a notification signal for processing the completion instruction to the server host through the controller after the composite queue completes the instruction migration operation, so that the server host recycles the NVMe request.

[0030] In a third aspect, the present application discloses an electronic device, comprising:

[0031] a memory configured to save a computer program;

[0032] a processor configured to execute the computer program to implement the steps of the NVMe instruction processing method disclosed above.

[0033] In a fourth aspect, the present application discloses a computer readable storage medium configured to store a computer program; wherein the computer program is executed by a processor to implement the steps of the NVMe instruction processing method disclosed above.

[0034] It can be seen that, by acquiring the current to-be-processed NVMe request instruction in the target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction, if the instruction type is a read instruction, a data acquisition instruction is sent to the backend, so that the backend moves the first target data to the embedded system memory based on the data acquisition instruction; the currently used composite queue in the controller is determined, and the first DMA instruction for moving the first target data from the embedded system memory to the server host memory and the completion instruction representing the completion of the NVMe request are sent to the composite queue; after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request. It can be seen that, after the to-be-processed NVMe request instruction is acquired and it is determined that the instruction type is a read instruction, the first target data required is moved to the embedded system memory through the backend, and then the first DMA instruction is sent to the currently used composite queue to complete the operation of moving the first target data from the embedded system memory to the server host memory, and the completion instruction representing the completion of the NVMe request is also sent to the composite queue, and after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host completes the recycling processing of the NVMe request. That is, after the first DMA instruction is sent, there is no need to wait for the polling scheduling of the embedded system CPU, but the completion instruction is directly sent to the same composite queue, the scheduling time and times are saved, and thus the delay of the embedded system in processing the read instruction is reduced, and the system efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0036] Figure 1 It is a structural schematic diagram of an embedded virtualization storage system.

[0037] Figure 2 It is a distribution diagram of read instruction processing delay time consumption.

[0038] Figure 3 It is a flowchart of an NVMe instruction processing method disclosed by the present application.

[0039] Figure 4 It is a flowchart of a specific NVMe instruction processing method disclosed by the present application.

[0040] Figure 5 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure;

[0041] Figure 6 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure;

[0042] Figure 7 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure;

[0043] Figure 8 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure;

[0044] Figure 9 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure;

[0045] Figure 10 A specific NVMe instruction processing flowchart disclosed by the present application is shown in the figure. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0047] With the continuous development of storage hardware technology, the NVMe (Nonvolatile Memory Express, i.e. non-volatile memory host controller interface) protocol has gradually become mainstream, and most virtualization systems support NVMe virtual disks, and embedded virtualization storage systems are no exception. However, the embedded virtualization storage system itself will also bring additional delay time due to the internal interaction between the storage protocol instruction and data processing flow and the embedded components. In the embedded virtualization storage system, since the software driver runs on the embedded operating system, when the controller or the backend persistent module completes the corresponding processing, the software driver needs to be rescheduled to process the received task. Specifically, the software driver needs to be scheduled multiple times on the embedded system CPU to finally complete the I / O instruction. With the increase of virtual devices or the increase of system load, the required scheduling time will also increase accordingly, thus increasing the delay of I / O instruction processing and reducing the system efficiency. Therefore, the embodiments of the present application disclose an NVMe instruction processing method, device, equipment and medium, which can reduce the delay of instruction processing in the embedded system to improve the system efficiency.

[0048] Referring toFigure 3 As shown, the embodiment of the present application discloses a method for processing NVMe instruction, applied to a driver in an embedded system, which comprises the following steps:

[0049] Step S11: obtaining a current NVMe request instruction to be processed in a target sending queue, and parsing the NVMe request instruction to determine the instruction type of the NVMe request instruction.

[0050] In the embodiment, the driver obtains a current NVMe request instruction to be processed from a target sending queue, and parses the obtained NVMe request instruction to determine the instruction type of the NVMe request instruction; wherein the instruction type can specifically include a read instruction and a write instruction.

[0051] It should be noted that before obtaining the current NVMe request instruction to be processed in the target sending queue, the following steps are further included: sending an NVMe request instruction to a target sending queue in the driver by a controller, and sending a fetch instruction to the driver by a register, so that the driver executes the step of obtaining the current NVMe request instruction to be processed in the target sending queue after obtaining the fetch instruction. That is, the NVMe request instruction in the target sending queue in the embodiment is sent by the controller, specifically, the controller first sends an NVMe request instruction (Submission Queue Entry, SQE) to the tail of a target sending queue (Submission Queue, SQ) on the driver side, and then sends a signal of a fetch instruction to the driver by a register, so that the driver obtains the current NVMe request instruction to be processed from the target sending queue after obtaining the fetch instruction.

[0052] Step S12: if the instruction type is a read instruction, sending a data acquisition instruction to a back end, so that the back end moves first target data to an embedded system memory based on the data acquisition instruction.

[0053] In the embodiment, if the instruction type is a read instruction, a data acquisition instruction is first sent to the back end, that is, the back end is notified to move the required first target data to the embedded system memory.

[0054] Step S13: determining a composite queue currently used in the controller, and sending a first DMA instruction for moving the first target data from the embedded system memory to a server host memory and a completion instruction representing completion of the NVMe request to the composite queue.

[0055] In the embodiment, the current used composite queue in the controller is determined, and then the first DMA instruction for moving the first target data from the embedded system memory to the server host memory and the completion instruction (Completion Queue Entry, CQE) for representing the completion of the NVMe request are sent to the composite queue. That is, the first DMA instruction is sent to the current used composite queue to complete the operation of moving the first target data from the embedded system memory to the server host memory, and the completion instruction (Completion Queue Entry, CQE) for representing the completion of the NVMe request is also sent to the composite queue immediately, without waiting for the polling scheduling of the embedded system CPU, so that the problem that the completion instruction processing needs to wait for the data DMA instruction processing to be completed and then needs the scheduling of the embedded system CPU to participate is solved, the scheduling time is saved, the delay of the embedded system in processing the read instruction is reduced, and the system efficiency is improved. It can be understood that two queues corresponding to two instructions, i.e., the DMA instruction and the CQE instruction, are generated for one I / O request, the two queues are combined to obtain the composite queue in the embodiment, the composite queue can process the DMA instruction of the data and the completion instruction, and is recorded as CDQ (i.e., Completion and DMA Queue); in addition, it should be pointed out that the queue depth of the target sending queue is the same as the queue depth of the composite queue, that is, the composite queue CDQ and the sending queue SQ have the same queue depth, so that the load balancing of the instructions in the logical controller is ensured.

[0056] Step S14: After the completion instruction moving operation of the composite queue is completed, the notification signal for processing the completion instruction is sent to the server host through the controller, so that the server host recycles the NVMe request.

[0057] In the embodiment, after the completion instruction moving operation of the composite queue is completed, the driver sends the signal for reading the completion instruction to the controller through the write register, and then sends the notification signal for processing the completion instruction to the server host through the controller, so that the server host recycles the NVMe request. That is, through the above method, the controller can directly send the notification signal for processing the completion instruction to the server host after the DMA instruction processing is completed, so that the polling scheduling time overhead of the embedded system is avoided.

[0058] It can be seen that, by acquiring the current NVMe request instruction to be processed in the target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction, if the instruction type is a read instruction, a data acquisition instruction is sent to the backend, so that the backend moves first target data to the embedded system memory based on the data acquisition instruction; the composite queue currently used in the controller is determined, and the first DMA instruction for moving the first target data from the embedded system memory to the server host memory and the completion instruction representing the completion of the NVMe request are sent to the composite queue; after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request. It can be seen that, after the NVMe request instruction to be processed is acquired and it is determined that the instruction type is a read instruction, the first target data required is moved to the embedded system memory through the backend, and then the first DMA instruction is sent to the composite queue currently used, so as to complete the operation of moving the first target data from the embedded system memory to the server host memory, and the completion instruction representing the completion of the NVMe request is also sent to the composite queue, and after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host completes the recycling processing of the NVMe request. That is, after the first DMA instruction is sent, there is no need to wait for the polling scheduling of the embedded system CPU, but the completion instruction is directly sent to the same composite queue, which saves the scheduling time and times, thereby reducing the delay of the embedded system in processing the read instruction and improving the system efficiency.

[0059] Referring to Figure 4 and Figure 5 It can be seen that, by acquiring the current NVMe request instruction to be processed in the target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction, if the instruction type is a read instruction, a data acquisition instruction is sent to the backend, so that the backend moves first target data to the embedded system memory based on the data acquisition instruction; the composite queue currently used in the controller is determined, and the first DMA instruction for moving the first target data from the embedded system memory to the server host memory and the completion instruction representing the completion of the NVMe request are sent to the composite queue; after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request. It can be seen that, after the NVMe request instruction to be processed is acquired and it is determined that the instruction type is a read instruction, the first target data required is moved to the embedded system memory through the backend, and then the first DMA instruction is sent to the composite queue currently used, so as to complete the operation of moving the first target data from the embedded system memory to the server host memory, and the completion instruction representing the completion of the NVMe request is also sent to the composite queue, and after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host completes the recycling processing of the NVMe request. That is, after the first DMA instruction is sent, there is no need to wait for the polling scheduling of the embedded system CPU, but the completion instruction is directly sent to the same composite queue, which saves the scheduling time and times, thereby reducing the delay of the embedded system in processing the read instruction and improving the system efficiency.

[0060] Specifically includes:

[0061] Step S21: acquiring the current NVMe request instruction to be processed in the target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction.

[0062] Step S22: if the instruction type is a read instruction, a data acquisition instruction is sent to the backend, so that the backend moves first target data to the embedded system memory based on the data acquisition instruction.

[0063] Step S23: Determine the composite queue used by the previous read instruction; wherein the composite queue includes a first composite queue and a second composite queue; if the composite queue used by the previous read instruction is the first composite queue, then the second composite queue is used as the composite queue currently in use in the controller.

[0064] In this embodiment, after moving the first target data from the backend to the embedded system memory, a DMA operation needs to be completed. For read instructions, this embodiment needs to determine the currently used composite queue in the controller. Specifically, the currently used composite queue is determined based on the composite queue used by the previous read instruction. It can be understood that the composite queue includes a first composite queue (CDQ1) and a second composite queue (CDQ2). If the composite queue used by the previous read instruction was the first composite queue, then the second composite queue is used as the currently used composite queue in the controller; if the composite queue used by the previous read instruction was the second composite queue, then the first composite queue is used as the currently used composite queue in the controller. That is, when the system processes read instructions, composite queues CDQ1 and CDQ2 are used in a round-robin fashion.

[0065] Step S24: Send a first DMA instruction to the composite queue for moving the first target data from the embedded system memory to the server host memory and a completion instruction indicating that the NVMe request is completed.

[0066] In this embodiment, after determining the currently used composite queue, a first DMA instruction for moving the first target data from the embedded system memory to the server host memory is sent to the composite queue. The NVMe request completion instruction (CQE) is also sent to the composite queue to ensure that the DMA instruction and CQE instruction corresponding to the same I / O request are placed in the same composite queue in sequence. It should be noted that after completing the DMA operation, the backend also needs to perform persistence processing on the first target data. In this way, compared to existing technologies, such as... Figure 6 As shown, after receiving the DMA operation completion signal, the embedded system still needs to re-polulate and schedule the embedded driver to send the completion instruction, saving a significant amount of scheduling time. That is, in this embodiment, the controller can process the next CQE instruction immediately after completing the DMA instruction, facilitating subsequent forwarding to the server host. This effectively avoids the extra waiting time caused by the embedded CPU's polling and scheduling, ensuring that the composite queue does not become a bottleneck in the system. Two composite queues and one send queue SQ are used to form a new queue pair. A comparison of latency times can be seen in the following diagram. Figure 7 As shown in the image.

[0067] Step S25: After the completion instruction migration operation of the composite queue is completed, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recycles the NVMe request.

[0068] Step S26: The server host kernel executes the recycling processing of the NVMe request, and sends a recycling success signal corresponding to the recycling processing to the controller after the recycling processing is completed, so that the controller updates the register head pointer corresponding to the composite queue.

[0069] In the embodiment, after the controller sends the notification signal for processing the completion instruction (CQE) to the server host memory, the server host kernel further executes the recycling processing of the NVMe request, and sends a recycling success signal corresponding to the recycling processing to the controller after the recycling processing is completed. After receiving the recycling success signal from the server host, the controller updates the register head pointer (Head) corresponding to the composite queue.

[0070] The more specific processing procedures of the above steps S21, S22 and S25 can refer to the corresponding contents disclosed in the foregoing embodiments, and will not be described here again.

[0071] As can be seen, in the embodiment of the application, after the first target data is migrated from the back end to the embedded system memory, the DMA operation needs to be completed. For the read instruction, the currently used composite queue in the controller needs to be determined. The composite queue includes a first composite queue and a second composite queue, and the two queues are used in turn in a round robin manner. That is, if the composite queue used by the last read instruction is the first composite queue, the second composite queue is used as the currently used composite queue in the controller. If the composite queue used by the last read instruction is the second composite queue, the first composite queue is used as the currently used composite queue in the controller. After the currently used composite queue is determined, a first DMA instruction for migrating the first target data from the embedded system memory to the server host memory is sent to the composite queue, and the completion instruction of the NVMe request is also sent to the composite queue, so as to ensure that the DMA instruction and the CQE instruction corresponding to the same I / O request are sequentially placed in the same composite queue. After the controller sends the notification signal for processing the completion instruction to the server host memory, the server host kernel further executes the recycling processing of the NVMe request, and updates the register head pointer corresponding to the composite queue. Through the above scheme, the problem of high latency and low efficiency of the embedded storage hardware virtualization system in processing the read instruction is optimized.

[0072] Referring to Figure 8 The embodiment of the application discloses a specific NVMe instruction processing method. Compared with the previous embodiment, the technical solution is further described and optimized. Specifically, it includes:

[0073] Step S31: Obtain the current NVMe request instruction to be processed in the target sending queue, and parse the NVMe request instruction to determine the instruction type of the NVMe request instruction.

[0074] Step S32: If the instruction type is a write instruction, send a second DMA instruction for moving the second target data from the server host memory to the embedded system memory to the first composite queue.

[0075] In this embodiment, if the instruction type is a write instruction, the second target data required is determined, and a second DMA instruction is sent to the first composite queue to complete the operation of moving the second target data from the server host memory to the embedded system memory.

[0076] Step S33: After obtaining the signal indicating that the second DMA instruction is completed, the back end performs persistent processing on the second target data, and after the persistent processing is completed, a completion instruction representing the completion of the NVMe request is sent to the second composite queue.

[0077] In this embodiment, after the driver obtains the signal indicating that the second DMA instruction is completed, i.e., the signal indicating that the first composite queue completes the data moving, the back end needs to be notified to perform persistent processing on the second target data, and after the persistent processing is completed, a completion instruction representing the completion of the NVMe request is sent to the second composite queue. That is, for the write instruction, the DMA instruction and the completion instruction are still processed by different queues, i.e., the first composite queue and the second composite queue, respectively.

[0078] Step S34: After the second composite queue completes the moving operation of the completion instruction, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recovers the NVMe request.

[0079] In this embodiment, after the completion instruction representing the completion of the NVMe request is sent to the second composite queue, the second composite queue completes the moving operation of the completion instruction, and after the second composite queue completes the moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host recovers the NVMe request.

[0080] Step S35: The server host kernel executes the recovery processing of the NVMe request, and after the recovery processing is completed, a corresponding recovery success signal is sent to the controller, so that the controller updates the register header pointer corresponding to the second composite queue.

[0081] In the embodiment, since the completion instruction is sent to the second composite queue, the controller needs to update the register head pointer corresponding to the second composite queue.

[0082] More specific processes about the steps S31 and S34 can refer to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

[0083] It can be seen that in the embodiment, if the instruction type is a write instruction, the second target data is determined, and a second DMA instruction is sent to the first composite queue to complete the operation of moving the second target data from the server host memory to the embedded system memory, and after the data moving is completed, the completion instruction for representing the completion of the NVMe request is sent to the second composite queue. That is, for the write instruction, the DMA instruction and the completion instruction are still processed by different queues.

[0084] Referring to Figure 9 The embodiment discloses an NVMe instruction processing device applied to a driver in an embedded system, and the device comprises:

[0085] An instruction acquisition module 11 is configured to acquire a current NVMe request instruction to be processed in a target sending queue, and analyze the NVMe request instruction to determine an instruction type of the NVMe request instruction;

[0086] A first data moving module 12 is configured to, if the instruction type is a read instruction, send a data acquisition instruction to a back end, so that the back end moves first target data to an embedded system memory based on the data acquisition instruction;

[0087] A second data moving module 13 is configured to determine a composite queue to be currently used in a controller, and send a first DMA instruction for moving the first target data from the embedded system memory to a server host memory and a completion instruction representing the completion of the NVMe request to the composite queue;

[0088] A completion instruction notification module 14 is configured to, after the composite queue completes the instruction moving operation, send a notification signal for processing the completion instruction to the server host through the controller, so that the server host recycles the NVMe request.

[0089] It can be seen that, by acquiring the current to-be-processed NVMe request instruction in the target sending queue, and parsing the NVMe request instruction to determine the instruction type of the NVMe request instruction, if the instruction type is a read instruction, a data acquisition instruction is sent to the backend, so that the backend moves the first target data to the embedded system memory based on the data acquisition instruction; the composite queue currently used in the controller is determined, and the first DMA instruction for moving the first target data from the embedded system memory to the server host memory and the completion instruction representing the completion of the NVMe request are sent to the composite queue; after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host through the controller, so that the server host recycles the NVMe request. It can be seen that, after the to-be-processed NVMe request instruction is acquired and it is determined that the instruction type is a read instruction, the first target data required is moved to the embedded system memory through the backend, and then the first DMA instruction is sent to the composite queue currently used, so as to complete the operation of moving the first target data from the embedded system memory to the server host memory, and the completion instruction for representing the completion of the NVMe request is also sent to the composite queue, and after the composite queue completes the instruction moving operation, the controller sends a notification signal for processing the completion instruction to the server host, so that the server host completes the recycling processing of the NVMe request. That is, after the first DMA instruction is sent, there is no need to wait for the polling scheduling of the embedded system CPU, but the completion instruction is directly sent to the same composite queue, the scheduling time and times are saved, so as to reduce the delay of the embedded system in processing the read instruction and improve the system efficiency.

[0090] Figure 10 A structural schematic diagram of an electronic device provided by an embodiment of the present application is provided. Specifically, it can include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the related steps in the NVMe instruction processing method performed by the electronic device disclosed in any of the preceding embodiments.

[0091] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 is any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input / output interface 25 is used to acquire external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited specifically herein.

[0092] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 21 can further include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0093] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223, etc. The storage mode can be temporary storage or permanent storage.

[0094] The operating system 221 is used to manage and control each hardware device on the electronic device 20 and the computer program 222, so as to realize the operation and processing of the processor 21 on the mass data 223 in the memory 22. It can be Windows, Unix, Linux, etc. In addition to including the computer program capable of completing the NVMe instruction processing method executed by the electronic device 20 disclosed in any of the preceding embodiments, the computer program 222 can further include a computer program capable of completing other specific work. The data 223 can include data received by the electronic device from an external device, as well as data collected by the self input / output interface 25, etc.

[0095] Further, the embodiments of the present application also disclose a computer readable storage medium, the storage medium stores a computer program, and the computer program is loaded and executed by the processor to realize the method steps executed in the NVMe instruction processing process disclosed in any of the preceding embodiments.

[0096] The various embodiments described in this specification are presented by way of example, and each embodiment is not necessarily composed of all features described with respect to other embodiments. Each embodiment described in this specification can be implemented in software, firmware, hardware, or any combination thereof. The various embodiments described in this specification can be implemented in any combination of the following technologies: software defined radio, code division multiple access (CDMA) networks, time division multiple access (TDMA) networks, frequency division multiple access (FDMA) networks, orthogonal frequency division multiplexing (OFDM) networks, orthogonal frequency division multiple access (OFDMA) networks, global system for mobile communications (GSM) networks, 3rd Generation (3G) networks, 4th Generation (4G) networks, and draft 5th Generation (5G) networks.

[0097] Those skilled in the art will further appreciate that the units and algorithms described in connection with the examples disclosed herein can be implemented in electronic hardware, computer software, or any combination thereof. To clearly illustrate this interchangeability of hardware and software, various examples disclosed herein have been described in general terms that are applicable to both hardware and software implementations.

[0098] Instructions for the operating system, applications, and / or programs can be located in storage media in a computer readable storage medium device. Furthermore, the required operating system or program can be downloaded from a remote location through the network interface (e.g., modem or network connection) or through a CD-ROM or DVD-ROM device. The essential elements of a computer program, which perform processes described herein, are known. As used herein, the term "computer" or "processor" encompasses all of these elements and variants thereof known to those with skill in the art.

[0099] Finally, it should be noted that the terms "comprises", "comprising", or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Reference to an element with the indefinite articles "a" or "an" does not exclude the presence of two or more identical elements in the process, method, article, or apparatus.

[0100] The above describes in detail the NVMe instruction processing method, device, equipment and storage medium provided by the present application. The principles and implementation manners of the present application are described by applying specific examples. The above example is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. The above description should not be understood as a limitation of the present application.

Claims

1. A method for processing an NVMe instruction, the method comprising: The application relates to a driver applied to an embedded system, comprising: obtaining a current NVMe request instruction to be processed in a target sending queue, and analyzing the NVMe request instruction to determine the instruction type of the NVMe request instruction; if the instruction type is a read instruction, sending a data obtaining instruction to a back end, so that the back end moves first target data to an embedded system memory based on the data obtaining instruction; determining a current composite queue used in a controller, and sending a first DMA instruction for moving the first target data from the embedded system memory to a server host memory and a completion instruction representing completion of the NVMe request to the composite queue; after the composite queue completes the instruction moving operation, sending a notification signal for processing the completion instruction to the server host through the controller, so that the server host recycles the NVMe request.

2. The method of claim 1, wherein, The determination of the current composite queue used in the controller comprises: determining a composite queue used by a previous read instruction; wherein the composite queue comprises a first composite queue and a second composite queue; if the composite queue used by the previous read instruction is the first composite queue, the second composite queue is used as the current composite queue in the controller.

3. The method of claim 2, wherein, After the analysis of the NVMe request instruction to determine the instruction type of the NVMe request instruction, the method further comprises: if the instruction type is a write instruction, a second DMA instruction for moving second target data from a server host memory to an embedded system memory is sent to the first composite queue; after a signal for completing the second DMA instruction is obtained, the back end is notified to perform persistent processing on the second target data, and a completion instruction representing completion of the NVMe request is sent to the second composite queue after the persistent processing is completed; after the second composite queue completes the moving operation of the completion instruction, a notification signal for processing the completion instruction is sent to the server host through the controller, so that the server host recycles the NVMe request.

4. The method of claim 1, wherein, After the sending of the notification signal for processing the completion instruction to the server host through the controller, so that the server host recycles the NVMe request, the method further comprises: the server host kernel executes the recycling processing of the NVMe request, and sends a corresponding recycling success signal to the controller after the recycling processing is completed, so that the controller updates a register head pointer corresponding to the composite queue.

5. The method of claim 3, wherein, After the second composite queue completes the moving operation of the completion instruction, a notification signal for processing the completion instruction is sent to the server host through the controller, so that the server host recycles the NVMe request, and the method further comprises: the server host kernel executes the recycling processing of the NVMe request, and sends a corresponding recycling success signal to the controller after the recycling processing is completed, so that the controller updates a register head pointer corresponding to the second composite queue.

6. The method of claim 1, wherein, Before the obtaining of the current NVMe request instruction to be processed in the target sending queue, the method further comprises: The controller sends an NVMe request instruction to a target sending queue in a driver, and sends a get instruction to the driver of the embedded system by using a register, so that after the driver gets the get instruction, the driver executes a step of obtaining a current NVMe request instruction to be processed in the target sending queue.

7. The method of claim 1-6, wherein, The queue depth of the target sending queue is the same as the queue depth of the composite queue.

8. An NVMe instruction processing apparatus, characterized by, The application is applied to a driver in an embedded system, and comprises: An instruction obtaining module is configured to obtain a current NVMe request instruction to be processed in a target sending queue, and analyze the NVMe request instruction to determine the instruction type of the NVMe request instruction. A first data moving module is configured to send a data obtaining instruction to a back end if the instruction type is a read instruction, so that the back end moves first target data to an embedded system memory based on the data obtaining instruction. A second data moving module is configured to determine a composite queue currently used in a controller, and send a first DMA instruction for moving the first target data from the embedded system memory to a server host memory and a completion instruction representing completion of the NVMe request to the composite queue. A completion instruction notification module is configured to send a notification signal for processing the completion instruction to a server host by the controller after the composite queue completes a data moving operation, so that the server host recycles the NVMe request.

9. An electronic device, comprising: The application comprises: A memory is configured to save a computer program. A processor is configured to execute the computer program to implement steps of the NVMe instruction processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The application is configured to store a computer program, wherein the computer program is executed by a processor to implement steps of the NVMe instruction processing method according to any one of claims 1 to 7.

Images