Fully hardware offloaded nvme storage acceleration system

Abstract

This invention provides a fully hardware-offloaded NVMe storage acceleration system, comprising a heterogeneous acceleration card consisting of an ARM software processor and an FPGA hardware processor. A management module is located in the ARM to process NVMe management commands, while a command capture module, a virtual queue binding module, an I / O processing module, and an I / O bandwidth fair scheduling module are located in the FPGA to achieve hardware acceleration of NVMe I / O commands and fair I / O bandwidth scheduling. Testing shows that the system proposed in this invention has read / write speeds 4.65 / 4.92 times faster than existing systems and reduces the CPU cost of fair I / O bandwidth scheduling to zero. This invention solves the problems of slow read / write speeds and strong CPU binding to fair I / O bandwidth scheduling in previous designs, better meeting the needs of multi-user / application sharing.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of computer software and hardware architecture and non-volatile storage system, in particular to a completely hardware-unloaded NVMe storage acceleration system. BACKGROUND

[0002] Flash-based solid-state disks (SSDs) non-volatile memory (NVM) as a storage class memory (SCM) with high I / O performance (such as low power consumption, low latency and high throughput) has become the preferred data persistence memory of data centers. The support of Non-Volatile memory express (NVMe) has further consolidated the position of SSDs in storage systems. In recent years, the continuous growth of massive data and the increasing demand of cloud users and cloud services not only promote the development of SSDs but also promote the optimization of NVMe. In addition, in order to meet the multi-tenant, low-latency and high-throughput requirements of data-intensive applications and cloud services, some higher-performance SCMs have gradually emerged, such as 3D XPoint, phase change RAM (PCM), resistance RAM (ReRAM) and magnetoresistive RAM (MRAM) and so on.

[0003] Taking NAND Flash SSD as an example, the number of chips and Flash channels inside it is growing, providing higher throughput, higher bandwidth and lower latency for data-intensive applications in data centers and cloud platforms. In order to fully utilize the inherent parallelism of SSDs, the NVMe protocol has replaced the serial attached SCSI (SAS) protocol and serial advanced technology attachment (SATA) designed for traditional hard disk drives (HDDs) and has become one of the standard components of SSDs. NVMe is a high-performance storage protocol based on peripheral component interconnect express (PCIe), which adopts a multi-I / O queue mechanism to fully exploit the parallelism of NVMe SSDs. NVMe supports up to 64K I / O queues and each queue supports 64K I / O command entries, which means that the host can fully utilize the low-latency, high-throughput and high-bandwidth characteristics of SSDs by submitting a large number of concurrent I / O requests.

[0004] The multi-queue mechanism of NVMe endows SSDs with the ability to serve multiple users / applications simultaneously. How to fairly allocate the bandwidth of SSDs among multiple tenants or applications while ensuring independence from each other is also a challenge. Unfortunately, NVMe is a kernel-level driver. Each time an NVMe I / O is triggered, it will go through the complex I / O stack of the host, causing context switching between user mode and kernel mode. At the same time, embedding a bandwidth fair scheduling policy into the kernel / NVMe driver is currently the common solution to guarantee the performance of multiple tenants or applications sharing a single SSD. Considering the multi-queue concurrent I / O characteristics of NVMe, this undoubtedly aggravates the burden of the host CPU. In addition, the multi-I / O queue concurrency mechanism also promotes the deployment of SSDs in virtualization and cloud environments. Fair allocation of I / O bandwidth is very important for such SSDs, as they are required to be shared compared to local SSDs.

[0005] Patent document CN105426120A (application number: CN201510726309.3) discloses a hybrid acceleration system based on NVME, including a business application pool, a PCIe exchange pool, a network communication pool, and at least two management modules. The business application module, the PCIe exchange module, and the data communication module are connected to the management module through an I2C bus and Ethernet at the same time. The I2C bus is used to obtain the underlying core device information of each module. The business application module includes multiple NVME disk arrays and PCIe exchange units. The PCIe exchange pool is connected to the business application pool and is used to transmit PCIe data between the business application modules. At least two management modules are designed to manage each module, and a dual management link design of I2C and Ethernet is adopted at the same time. Redundant design prevents single management module or link failure. The entire architecture uses PCIe transmission technology as the core data transmission network, realizes the pooling of the physical underlying resources of NVME disk arrays and the pooling of other modules, and facilitates centralized deployment and management.

[0006] Existing research has shown that high-performance SSDs are shifting the system performance bottleneck from SSD to CPU, and I / O bandwidth fair scheduling at the driver level not only causes high CPU overhead, but also causes long I / O delay and low I / O performance. Offloading the I / O bandwidth fair scheduling policy to the device is a novel solution to this challenge. Foreign researchers have successfully used the weighted round robin (WRR) feature of NVMe devices to offload the arbitration of bandwidth fair scheduling to the device, while the driver layer only needs to complete command submission and scheduling. However, although this reduces CPU overhead and alleviates the adverse effects of I / O scheduling on delay and performance, the driver layer is still modified to complete scheduling loads other than arbitration, such as virtual time calculation, command redirection submission, and dynamic adjustment of weight ratio. This shows that as the performance of modern SSDs continues to improve, the additional work left in the driver layer by I / O bandwidth fair scheduling is likely to become a performance bottleneck again. More importantly, the performance of I / O bandwidth fair scheduling, i.e. the amount of additional delay introduced by I / O bandwidth fair scheduling, is still tightly coupled with CPU cost. SUMMARY

[0007] In view of the defects in the prior art, the purpose of the present application is to provide a completely hardware offloaded NVMe storage acceleration system.

[0008] The completely hardware offloaded NVMe storage acceleration system provided by the present application comprises a heterogeneous acceleration card composed of an ARM software processor and a field programmable logic gate array (FPGA) hardware processor, and the heterogeneous acceleration card is connected with a host through a high-speed serial bus.

[0009] The heterogeneous acceleration card comprises:

[0010] The ARM software processor is internally provided with a management module for processing NVMe management commands, including I / O queue creation and deletion.

[0011] The FPGA hardware processor is internally provided with a command grabbing module for transmitting NVMe management and NVMe I / O commands submitted by the host in parallel and in batches; and also for transmitting NVMe management and NVMe I / O completion commands generated by the acceleration card in parallel and in batches.

[0012] A virtual queue binding module is used to dispatch NVMe I / O commands of different users / applications in the I / O submission queue in the local memory of the acceleration card to the designated virtual I / O submission queue in the local memory of the acceleration card.

[0013] An I / O processing module pool comprising 16 I / O processing modules is used to process NVMe I / O commands.

[0014] An I / O bandwidth fair scheduling module is configured to implement I / O bandwidth fair scheduling among different users / applications.

[0015] An administration submission queue is set in the local memory of the acceleration card, which is used to expose an administration submission queue to the host, and at the same time, it is also used to cache the NVMe administration commands obtained from the host memory.

[0016] An administration completion queue is set in the local memory of the acceleration card, which is used to expose an administration completion queue to the host, and at the same time, it is also used to cache the NVMe administration completion commands generated by the administration module.

[0017] Eight I / O submission queues are set in the local memory of the acceleration card, which are used to expose eight I / O submission queues to the host, and at the same time, they are also used to cache the NVMe I / O commands obtained from the host memory.

[0018] Eight I / O completion queues are set in the local memory of the acceleration card, which are used to expose eight I / O completion queues to the host, and at the same time, they are also used to cache the NVMe I / O completion commands generated by the I / O processing module.

[0019] Eight virtual I / O submission queue pools are set in the local memory of the acceleration card, and the eight virtual I / O submission queue pools correspond to the eight I / O submission queues in the local memory of the acceleration card one-to-one, which are used to cache the NVMe I / O commands submitted by different users / applications stored in the eight I / O submission queues.

[0020] Preferably, the administration module reads the NVMe administration commands from the administration submission queue in the local memory of the acceleration card through memory read-write control and processes them, and after processing, the administration module generates corresponding NVMe administration completion commands and writes them into the administration completion queue in the local memory of the acceleration card through memory read-write control.

[0021] Preferably, the command grabbing module obtains the NVMe administration commands in the administration submission queue and the NVMe I / O commands in the I / O submission queue in the host memory through direct memory access, and writes the NVMe administration commands and the NVMe I / O commands into the administration submission queue and the corresponding I / O submission queue in the local memory of the acceleration card through direct memory access; at the same time, the command grabbing module obtains the NVMe administration completion commands in the administration completion queue and the NVMe I / O completion commands in the I / O completion queue in the local memory of the acceleration card through direct memory access, and writes the NVMe administration completion commands and the NVMe I / O completion commands into the administration completion queue and the corresponding I / O completion queue in the host memory through direct memory access.

[0022] Preferably, the virtual queue binding module reads NVMe I / O commands from the I / O submission queue in the local memory of the accelerator card and parses the user ID field in the command through memory read and write control. Then, based on the user ID, it writes the NVMe I / O commands into the specified virtual I / O submission queue in the local memory of the accelerator card through memory read and write control.

[0023] The I / O processing module reads and processes NVMe I / O commands from the virtual I / O submission queue in the accelerator card's local memory through memory read / write control. After processing, the I / O processing module generates the corresponding NVMe I / O completion command and writes the NVMe I / O completion command into the corresponding I / O completion queue in the accelerator card's local memory through memory read / write control.

[0024] Preferably, the I / O bandwidth fair scheduling module obtains the amount of data transmitted by each user / application in real time by reading from registers, and accumulates the data amount into the bandwidth accumulation register corresponding to each user / application by writing to registers. Then, the I / O bandwidth fair scheduling module uses the value in the bandwidth accumulation register to obtain the I / O bandwidth obtained by each user / application in real time and selects the user with the smallest obtained I / O bandwidth. Finally, the I / O bandwidth fair scheduling module sets the virtual I / O submission queue corresponding to the local memory of the acceleration card to an active state according to the user ID of the selected user, while setting the virtual I / O submission queues corresponding to other user IDs to a silent state, thereby limiting the I / O command processing speed of high-bandwidth users and accelerating the I / O command processing speed of low-bandwidth users.

[0025] Preferably, the management module includes a queue processing submodule, a data processing submodule, and a completion processing submodule;

[0026] The queue processing submodule reads NVMe management commands from the management submission queue in the accelerator card's local memory via memory read / write control, identifies and decodes the NVMe management commands, and then selectively retains the decoding results or sends the decoding results to the data processing submodule based on the identified NVMe management command type. After receiving the decoding results, the data processing submodule performs address parsing and translation to obtain the source address and destination address of the data, and transfers the data from the source address to the destination address through direct memory access. When the queue processing submodule completes the process of retaining the decoding results or the data processing submodule completes the data transfer, it indicates that the processing of the NVMe management commands has been completed. The completion processing submodule then generates an NVMe management completion command and writes the NVMe management completion command into the management completion queue in the accelerator card's local memory via memory read / write control.

[0027] Preferably, the command capture module monitors a management commit queue and eight I / O commit queues in the host memory in real time, and also monitors a management completion queue and eight I / O completion queues in the accelerator card's local memory in real time. When there are new NVMe management commands and NVMe I / O commands in the management commit queue and eight I / O commit queues in the host memory, the command capture module transmits the NVMe management commands to the management commit queue in the accelerator card's local memory and the NVMe I / O commands to the corresponding I / O commit queues in the accelerator card's local memory via direct memory access. When there are new NVMe management completion commands and NVMe I / O completion commands in the management completion queue and eight I / O completion queues in the accelerator card's local memory, the command capture module transmits the NVMe management completion commands to the management completion queue in the host memory and the NVMe I / O completion commands to the corresponding I / O completion queues in the host memory via direct memory access.

[0028] Preferably, the virtual queue binding module includes a user ID parsing submodule and a user ID binding submodule;

[0029] The user ID parsing submodule reads NVMe I / O commands from eight I / O submission queues in the accelerator card's local memory using memory read / write control and extracts the user ID from the commands. The user ID is then passed to the user ID binding submodule. The user ID binding submodule uses the user ID to search for a virtual I / O submission queue with the same user ID in the virtual I / O submission queue pool corresponding to the I / O submission queue in the accelerator card's local memory. When a virtual I / O submission queue is found, the user ID binding submodule dispatches the NVMe I / O command to that virtual I / O submission queue; otherwise, the user ID binding submodule allocates a new virtual I / O submission queue in the virtual I / O submission queue pool and submits the NVMe I / O command to the newly created virtual I / O submission queue.

[0030] Preferably, the I / O processing module pool contains 16 I / O processing modules, which are evenly distributed to eight virtual I / O submission queue pools, that is, two I / O processing modules process NVMe I / O commands in one virtual I / O submission queue pool in parallel;

[0031] Each I / O processing module includes a queue processing submodule, a data processing submodule, and a completion processing submodule;

[0032] The queue processing submodule reads NVMe I / O commands from the active virtual I / O submission queue in the virtual I / O submission queue pool in the accelerator card's local memory via memory read / write control. It then identifies and decodes the NVMe I / O commands and sends the decoding results to the data processing submodule. Upon receiving the decoding results, the data processing submodule performs address resolution and translation to obtain the source and destination addresses of the data, and transfers the data from the source address to the destination address via direct memory access. When the data processing submodule completes the data transfer, it indicates that the NVMe I / O command processing is complete. The completion processing submodule then generates an NVMe I / O completion command and writes it to the corresponding I / O completion queue in the accelerator card's local memory via memory read / write control.

[0033] Preferably, the I / O bandwidth fair scheduling module includes eight command selection submodules, eight bandwidth accumulation submodules, and one fair scheduling submodule;

[0034] The command selection submodule, through memory read / write control, reads NVMe I / O commands from the virtual I / O submission queue matching the user ID specified by the fair scheduling submodule, within the virtual I / O submission queue pool corresponding to the accelerator card's local memory. It then transmits the NVMe I / O commands to the corresponding I / O processing module in the I / O processing module pool for processing. Simultaneously, the bandwidth accumulation submodule monitors the data transfer volume generated during NVMe I / O command processing in real time and adjusts the bandwidth according to the NVMe scheduler. The user ID field of the I / O command is accumulated in the bandwidth accumulation register matching the user ID. The fair scheduling submodule then reads the values ​​in all bandwidth accumulation registers in real time via register read / write control and sorts them from smallest to largest. When the sorting is complete, the fair scheduling submodule selects the bandwidth accumulation register with the smallest value and reads its user ID via register read / write. Finally, the fair scheduling submodule generates a fair scheduling signal based on the read user ID. This fair scheduling signal is transmitted to the command selection submodule, which sets the virtual I / O submission queues matching the user ID in the virtual I / O submission queue pool to an active state, while setting virtual I / O submission queues that do not match the user ID to a silent state.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] This invention provides a fully hardware-offloaded NVMe storage acceleration system, which boasts read / write speeds 4.65 / 4.92 times faster than existing systems and reduces CPU utilization for I / O bandwidth fair scheduling to 0. Compared to existing Linux kernel-integrated I / O bandwidth fair scheduling (BFQ) and the most advanced I / O bandwidth fair scheduling (D2FQ), the system described in this invention saves an average of 84.65% and 18.40% of CPU costs, respectively. It addresses the issue that existing CPU-based I / O bandwidth fair scheduling systems cannot meet the requirements of high performance, low CPU cost, and low CPU dependency in multi-user / application sharing scenarios for high-performance NVMe SSD storage systems. Attached Figure Description

[0037] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0038] Figure 1 This is a system block diagram of the present invention;

[0039] Figure 2 This is a system block diagram of an embodiment of the present invention;

[0040] Figure 3 This is a flowchart illustrating the processing flow of the management module in an embodiment of the present invention.

[0041] Figure 4 This is a flowchart of the command capture module in an embodiment of the present invention.

[0042] Figure 5 This is a flowchart illustrating the processing flow of the virtual queue binding module according to an embodiment of the present invention.

[0043] Figure 6 This is a flowchart of the I / O processing module according to an embodiment of the present invention;

[0044] Figure 7 This is a flowchart of the I / O bandwidth fair scheduling module in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0046] Example:

[0047] like Figure 1 and 2As shown, the accelerator card in this embodiment uses a self-developed development board equipped with a Xilinx xczu19eg-ffvc1760-2-e heterogeneous processing chip. It consists of a software processor and a hardware processor. In addition, it also includes some commonly used peripheral devices. The peripheral devices used in this embodiment include a PCIe Gen3×8 bus interface and local memory (BRAM). The software processor corresponds to a quad-core ARM A53 processor with a management module. The hardware processor corresponds to a Field-Programmable Gate Array (FPGA), which includes a command fetching module, a management submission queue, a management completion queue, eight I / O submission queues, eight I / O completion queues, a virtual queue binding module, an eight-virtual I / O submission queue pool, an I / O processing module pool, and an I / O bandwidth fair scheduling module. The command capture module, located in the hardware processor, retrieves NVMe management commands and NVMe I / O commands from the host (server / desktop) memory via the PCIe Gen3×8 bus interface using direct memory access. It then writes the NVMe management commands to the management submission queue in the local BRAM and the NVMe I / O commands to their corresponding I / O submission queues in the local BRAM using direct memory access. Subsequently, the management module, located in the software processor, reads the NVMe management commands from the management submission queues and processes them in real-time via memory read / write control, including queue processing, data processing, and completion processing. After the NVMe management commands are processed, the management module generates the corresponding NVMe completion command and writes it to the management completion queue in the local BRAM using memory read / write control. Finally, the command capture module transmits the NVMe completion command from the management completion queue in the local BRAM to the management completion queue in the host (server / desktop) memory via the PCIe Gen3×8 bus interface to complete the entire NVMe management command processing flow. The management module is implemented in a single core of the software processor, namely an ARM A53 core, using the C software programming language, while the command capture module is implemented in a hardware processor, namely an FPGA, using the Verilog hardware programming language.

[0048] Meanwhile, the virtual queue binding module located in the hardware processor reads NVMe I / O commands in parallel from eight I / O submission queues in the local memory BRAM via memory read / write control. It then uses the user ID field in the NVMe I / O command to assign it to the corresponding virtual I / O submission queue in the local memory BRAM pool that matches the user ID. This achieves binding and isolation between NVMe I / O commands submitted by different users / applications and specific virtual I / O submission queues, including steps such as user ID parsing and user ID binding. Subsequently, the I / O processing module in the I / O processing module pool located in the hardware processor reads and processes NVMe I / O commands from the corresponding "active" virtual I / O submission queues via memory read / write control, including queue processing, data processing, and completion processing steps. The I / O processing module pool contains 16 I / O processing modules, which are evenly distributed across 8 virtual I / O submission queue pools. This means that adjacent I / O processing modules process NVMe I / O commands in the same "active" virtual I / O submission queue pool in parallel. After an I / O processing module completes the processing of an NVMe I / O command, it generates a corresponding NVMe I / O completion command and writes it to the corresponding I / O completion queue in the local BRAM via memory read / write control. Finally, the command capture module uses direct memory access via the PCIeGen3×8 bus interface to transfer the NVMe I / O completion command from the I / O completion queue in the local BRAM to the corresponding I / O completion queue in the host (server / desktop) memory, completing the entire NVMe I / O command processing flow. The virtual queue binding module, the I / O processing module pool, and the I / O processing modules are implemented in the hardware processor (FPGA) using the Verilog hardware programming language.

[0049] The I / O bandwidth fairness scheduling module, located in the hardware processor, collects the data volume transmitted by each NVMe I / O command in real time while the I / O processing module processes the NVMe I / O commands. It then uses the user ID field in the NVMe I / O command to accumulate the data volume in real time into the bandwidth accumulation register matching the user ID. Subsequently, the I / O bandwidth fairness scheduling module sorts the bandwidth accumulation registers and selects the one with the smallest value, using its user ID to generate an I / O bandwidth fairness scheduling signal. This signal is transmitted to each of the eight virtual I / O submission queues in the local BRAM pool. Virtual I / O submission queues whose user IDs match the I / O bandwidth fairness scheduling signal are set to an "active" state, while other virtual I / O submission queues are set to a "silent" state. The I / O bandwidth fairness scheduling module is implemented in the hardware processor, i.e., the FPGA, using the Verilog hardware programming language.

[0050] Furthermore, to overcome the shortcomings of existing CPU-based I / O bandwidth fairness scheduling systems in meeting the high performance, low CPU cost, and low CPU dependency requirements of high-performance NVMe SSD storage systems shared by multiple users / applications, the aforementioned processing flows all employ a coarse-grained parallel architecture between queues and a fine-grained pipeline architecture within queues to provide low latency and high throughput. More importantly, the I / O bandwidth fairness scheduling module is embedded in the parallel and pipelined processing flows to provide fair I / O bandwidth scheduling with low additional latency and low CPU cost.

[0051] like Figure 3The diagram shows the processing flow of the management module in this embodiment. In this embodiment, the management module is implemented as C code software within a core of the ARM A53 software processor. The queue processing submodule, data processing submodule, and completion processing submodule are the three main submodules of the management module, used for processing NVMe management commands. The queue processing submodule first reads and processes NVMe management commands from the management submission queue in the local memory BRAM. Within the queue processing submodule, the read function is used to read NVMe management commands from the management submission queue in the local memory BRAM using memory read / write control and update the management submission queue head pointer. The decoding function is responsible for identifying and decoding NVMe management commands and, depending on the command type, directs the decoding results to the processing function within the queue processing submodule or the data processing submodule. The processing function receives and processes the decoding results of NVMe management commands such as I / O submission / completion queue creation and I / O submission / completion queue deletion. For example, after receiving the decoding result of an NVMe management command for I / O submission / completion queue creation, eight hardware I / O submission / completion queues are created. At the same time, the parameters of these I / O submit / complete queues, such as the I / O submit queue base address, I / O submit queue ID, I / O complete queue base address, and I / O complete queue ID, are also written into the reserved registers in the FPGA hardware processor.

[0052] The decoding results of NVMe management commands, which retrieve information about the NVMe controller such as namespace information, are transmitted to the data processing submodule. The address resolution function in the data processing submodule then performs address resolution and translation to obtain the source and destination addresses of the data. These addresses are then used by the Direct Memory Access (DMA) controller for DMA control, completing the data transfer without CPU intervention. It is worth noting that because the amount of information about the NVMe controller is limited and does not consume a large amount of storage resources, it is stored in the local BRAM of the FPGA hardware processor, referred to as the controller information storage area. Once the NVMe management commands are processed, the required results and other data are transmitted to the completion processing submodule. The completion processing submodule uses this intermediate data to construct the NVMe management completion command. Specifically, the encoding function encodes the data into an NVMe management completion command that can be recognized by the host-side (server / desktop) NVMe driver. Next, the write function writes the generated NVMe management completion command to the management completion queue in the local BRAM using memory read / write control and updates the tail pointer of the management completion queue.

[0053] like Figure 4The diagram shows the processing flow of the command fetching module in this embodiment. Low latency is one of the key advantages of NVMe storage systems. Unfortunately, fair I / O bandwidth scheduling masks this advantage. Therefore, improving the efficiency of fair I / O bandwidth scheduling is the most direct measure to minimize this adverse effect. Furthermore, increasing the transmission speed of NVMe management / I / O commands from the host (server / desktop) to the NVMe device, ensuring they reach the device as quickly as possible for processing, can also reduce latency. Whether at the kernel or hardware level, the increase in latency due to fair I / O bandwidth scheduling is unavoidable. However, this latency can be mitigated by improving the efficiency of fair I / O bandwidth scheduling and the speed of other processing flows for NVMe management / I / O commands. Therefore, the command fetching module is located in the FPGA hardware processor of this embodiment to achieve parallel fetching of commands from different queues. Parallel command fetching not only shortens the time for NVMe management / I / O commands to reach the device but also provides sufficient processing time for the fair I / O bandwidth scheduling module.

[0054] In this embodiment, each pair of (management / I / O) submit queues / complete queues is equipped with a pair of command capture modules. The command capture modules for different pairs of submit queues / complete queues implement parallel mapping between the host (server / desktop) memory and the accelerator card's local BRAM. Within each pair of submit queues / complete queues, two command capture modules respectively implement parallel mapping between the submit queue and the complete queue. Each command capture module consists of a monitoring function and a DMA controller. The monitoring function is used to monitor in real time whether new commands are injected into the submit queue in the host (server / desktop) memory or the complete queue in the accelerator card's local BRAM. Whenever a new command is submitted to the submit queue or complete queue, the DMA controller is notified to control the DMA to transfer the command from the submit queue from the host (server / desktop) memory to the corresponding submit queue in the accelerator card's local BRAM, or to transfer the command from the complete queue from the accelerator card's local BRAM to the corresponding complete queue in the host (server / desktop) memory. Furthermore, within the accelerator card's local memory (BRAM), different pairs of commit queues / complete queues are separated by isolated memory regions. These regions are pre-allocated using a static partitioning strategy to provide memory isolation between the different pairs of commit queues / complete queues.

[0055] like Figure 5The diagram shows the processing flow of the virtual queue binding module in this embodiment. The virtual queue binding module is used in this embodiment to provide isolation of virtual I / O submission queues for NVMe I / O commands from different users / applications. The user ID parsing submodule and the user ID binding submodule are its two hardware submodules. First, the user ID parsing submodule reads the NVMe I / O command from the I / O submission queue in the local memory BRAM and extracts the data from its user ID field (bytes 8 to byte 11). Then, the extracted user ID is passed to the user ID binding submodule. The user ID binding submodule uses the user ID to search for a virtual I / O submission queue with the same user ID in the virtual I / O submission queue pool corresponding to the I / O submission queue in the local memory BRAM. When the virtual I / O submission queue is found, the user ID binding submodule dispatches the NVMe I / O command to that virtual I / O submission queue. Conversely, the user ID binding submodule allocates a new virtual I / O commit queue, submits NVMe I / O commands to the newly created virtual I / O commit queue, and configures the user ID register of the virtual I / O commit queue with the user ID. In this embodiment, each I / O commit queue in the local memory BRAM is equipped with a virtual queue binding module to enable parallel processing between different I / O commit queues.

[0056] like Figure 6The diagram shows the processing flow of the I / O processing module in this embodiment. This embodiment implements 16 I / O processing modules in Verilog hardware code within the FPGA hardware processor to form an I / O processing module pool. The 16 I / O processing modules are evenly distributed among 8 virtual I / O submission queue pools, meaning two I / O processing modules process NVMe I / O commands in one virtual I / O submission queue pool in parallel. The queue processing submodule, data processing submodule, and completion processing submodule are the three main submodules of the I / O processing module, used for processing NVMe I / O commands. The queue processing submodule first reads and processes NVMe I / O commands from the "active" virtual I / O submission queues in the local memory BRAM. Within the queue processing submodule, the read function is used to read NVMe I / O commands from the "active" virtual I / O submission queues in the local memory BRAM using memory read / write control and to update the virtual I / O submission queue head pointer. The decoding function is responsible for recognizing and decoding NVMe I / O commands and sending the decoding results to the data processing submodule. The address resolution function in the data processing submodule then performs address resolution and translation to obtain the source and destination addresses of the data. These addresses are used by the Direct Memory Access (DMA) controller for DMA control, completing the data transfer without CPU intervention. Once the NVMe I / O command is processed, the required results and other data are transferred to the completion processing submodule. The completion processing submodule uses this intermediate data to construct the NVMe I / O completion command. Specifically, the encoding function encodes the data into an NVMe I / O completion command that can be recognized by the host-side (server / desktop) NVMe driver. Next, the write function writes the generated NVMe I / O completion command to the corresponding I / O completion queue in the local BRAM using memory read / write control and updates the tail pointer of the I / O completion queue.

[0057] like Figure 7The diagram shows the processing flow of the I / O bandwidth fair scheduling module in this embodiment. The I / O bandwidth fair scheduling module is implemented in the FPGA hardware processor using Verilog hardware code. It sets up a command selection submodule for each virtual I / O submission queue pool. The command selection submodule reads NVMe I / O commands from the virtual I / O submission queue in the corresponding virtual I / O submission queue pool in the local memory BRAM via memory read / write control. The NVMe I / O commands read by the command selection submodule are submitted to the corresponding I / O processing module in the I / O processing module pool for execution. While the I / O processing module processes the NVMe I / O commands, the user ID and data transfer amount in the NVMe I / O commands are extracted and submitted to the bandwidth accumulation submodule. The bandwidth accumulation submodule accumulates the data transfer amount output by the I / O processing module into the bandwidth accumulation register matching the user ID, based on the user ID. The bandwidth accumulation register is a 64-bit register, which is sufficient for measuring the bandwidth of the SSD.

[0058] To minimize latency and performance penalties caused by fair I / O bandwidth scheduling, the execution flow from reading NVMe I / O commands from the command selection submodule to accumulating the data transfer volume into the bandwidth accumulator register is divided at the granularity of virtual I / O submission queue pools. That is, the execution flows of the eight virtual I / O submission queue pools are independent and parallel. Furthermore, the command selection submodule, I / O processing module, and bandwidth accumulator submodule within the same execution flow are organized in a pipelined operating mode. Next, the fair scheduling submodule reads the values ​​in each bandwidth accumulator register in real time to achieve real-time fair I / O bandwidth scheduling. The fair scheduling submodule includes three main functions: comparison, selection, and decision. The comparison function compares the values ​​in each bandwidth accumulator register and sorts them in ascending order. The selection function selects the bandwidth accumulator register with the smallest value based on the comparison result and reads its user ID through register read / write control. The user ID is used to notify the decision function. The decision function generates a fair scheduling signal based on the received user ID. The fair scheduling signal is delivered to the command selection submodule of each virtual I / O submission queue pool. The command selection submodule then sets the virtual I / O submission queues in each pool to "active" status in real time based on the user ID transmitted by the fair scheduling signal, while setting virtual I / O submission queues with mismatched user IDs to "silent" status. The command selection submodule only reads NVMe I / O commands from the "active" virtual I / O submission queues, thus achieving real-time fair I / O bandwidth scheduling across users / applications. This is a simple global minimum tracking strategy. Furthermore, each time the I / O bandwidth fair scheduling module completes a round of scheduling, the values ​​of all bandwidth accumulation registers and the fair scheduling signal are cleared to prevent register overflow and prepare for the next round of scheduling.

[0059] Finally, the software and hardware processing system of this embodiment was built using Xilinx's Vivado development tools on a self-developed development board equipped with a Xilinx xczu19eg-ffvc1760-2-e heterogeneous processing chip.

[0060] The purpose of this invention is to address the shortcomings of existing CPU-based I / O bandwidth fair scheduling systems in meeting the requirements of high performance, low CPU cost, and low CPU dependency of high-performance NVMe SSD storage systems when shared by multiple users / applications. Therefore, this invention discloses a fully hardware-offloaded NVMe storage acceleration system.

[0061] Experiments were conducted on the fully hardware-offloaded NVMe storage acceleration system disclosed in this invention, and the results were analyzed. The system prototype of this invention was implemented on a self-developed development board. This development board is a self-developed heterogeneous computing acceleration platform equipped with a Xilinx xczu19eg-ffvc1760-2-e heterogeneous processing chip, as well as various peripherals such as PCIe interconnect interfaces, DDR4 memory modules, and QSFP high-speed network interfaces. The xczu19eg-ffvc1760-2-e is a heterogeneous processing core composed of a 4-core ARM A53 and an FPGA. The software processing system of this invention is located in one ARM A53 software processor core of the xczu19eg-ffvc1760-2-e, while the hardware processing system is located in the FPGA hardware processor of the xczu19eg-ffvc1760-2-e. The PCIe interconnect interface is set to Gen3×8 operating mode for comparison with other systems. The development board connects to the host computer via a PCIe interconnect interface. In the experiments related to this invention, the host computer is equipped with an AMD Ryzen 5 5600X 6-Core processor, a 2TB Intel SSD DCP4600, a 1TB Western Digital HDD, and a graphics card used only for display. Furthermore, the host computer has 16GB of memory, consisting of two 8GB DDR4 modules running at 2666MHz. An Ubuntu 20.04.4LTS operating system with a Linux 5.9.0 kernel is installed on the host computer. To ensure a fair comparison with existing systems, the open-source testing tool FIO is used as the primary tester to generate a series of test loads to verify the system described in this invention.

[0062] Tables 1 and 2 show the experimental verification results of the fully hardware-offloaded NVMe storage acceleration system disclosed in this invention. Table 1 shows the comparison results of the present invention and existing NVMe storage acceleration systems in terms of I / O read and write speed, while Table 2 shows the comparison results of the present invention and existing I / O bandwidth fair scheduling systems in terms of CPU utilization (CPU cost) and I / O latency.

[0063] Table 1. I / O read / write speed test results of the NVMe storage acceleration system (this invention) with complete hardware offloading.

[0064]

[0065] Table 2. I / O bandwidth fair scheduling test results of the NVMe storage acceleration system with complete hardware offloading (this invention).

[0066] Experimental results show that the fully hardware-offloaded NVMe storage acceleration system disclosed in this invention achieves a read latency of 1.14µs and a write latency of 1.301µs, a read throughput of 1702KIOPS and a write throughput of 1551KIOPS, and a read bandwidth of 7.304GB / s and a write bandwidth of 7.593GB / s under a workload generated by the open-source testing tool FIO. Its I / O read / write speeds are 4.65 times / 4.92 times faster than the fastest existing NVMe storage acceleration system (NVMeCHA). Furthermore, the fully hardware-offloaded NVMe storage acceleration system disclosed in this invention achieves 0% CPU utilization (i.e., zero CPU cost) and introduces no excessive I / O latency (i.e., I / O latency increase percentage is less than or equal to 0.50%) when implementing fair I / O bandwidth scheduling, which is superior to existing fair I / O bandwidth scheduling systems. Therefore, the fully hardware-offloaded NVMe storage acceleration system disclosed in this invention can better meet the requirements of high-performance NVMe SSD storage systems in multi-user / application sharing scenarios, offering high performance, low CPU cost, and low CPU dependency. It solves the problem that existing CPU-based I / O bandwidth fair scheduling systems cannot meet the requirements of high performance, low CPU cost, and low CPU dependency of high-performance NVMe SSD storage systems when shared by multiple users / applications, and has certain innovative and practical value.

[0067] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0068] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A fully hardware-offloaded NVMe storage acceleration system, characterized in that, It includes a heterogeneous acceleration card consisting of an ARM software processor and a field-programmable gate array hardware processor, the heterogeneous acceleration card being connected to the host via a high-speed serial bus; The heterogeneous accelerator card includes: The ARM software processor has a built-in management module for handling NVMe management commands, including I / O queue creation and deletion. The FPGA hardware processor has a command capture module that is used to transmit NVMe management and NVMe I / O commands submitted by the host in parallel and in batches; it is also used to transmit NVMe management and NVMe I / O completion commands generated by the accelerator card in parallel and in batches. The virtual queue binding module is used to dispatch NVMe I / O commands from different users / applications in the I / O submission queue in the accelerator card's local memory to a specified virtual I / O submission queue in the accelerator card's local memory; The I / O processing module pool includes 16 I / O processing modules for processing NVMe I / O commands; The I / O bandwidth fair scheduling module is used to implement fair I / O bandwidth scheduling among different users / applications. A management commit queue is set up in the accelerator card's local memory to expose a management commit queue to the host. At the same time, it is also used to cache NVMe management commands retrieved from the host's memory. A management completion queue is set up in the local memory of the accelerator card to expose a management completion queue to the host. At the same time, it is also used to cache NVMe management completion commands generated by the management module. Eight I / O commit queues are set up in the accelerator card's local memory to expose eight I / O commit queues to the host. At the same time, they are also used to cache NVMe I / O commands fetched from the host's memory. Eight I / O completion queues are set up in the local memory of the accelerator card to expose eight I / O completion queues to the host. At the same time, they are also used to cache NVMe I / O completion commands generated by the I / O processing module. Eight virtual I / O commit queue pools are set up in the local memory of the accelerator card. Each of the eight virtual I / O commit queue pools corresponds one-to-one with the eight I / O commit queues in the local memory of the accelerator card. They are used to cache NVMe I / O commands submitted by different users / applications stored in the eight I / O commit queues.

2. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The management module reads and processes NVMe management commands from the management submission queue in the accelerator card's local memory through memory read / write control. After processing, the management module generates a corresponding NVMe management completion command and writes the NVMe management completion command into the management completion queue in the accelerator card's local memory through memory read / write control.

3. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The command capture module obtains NVMe management commands from the management commit queue and NVMe I / O commands from the I / O commit queue in the host memory via direct memory access, and writes them into the management commit queue and the corresponding I / O commit queue in the accelerator card's local memory via direct memory access. Simultaneously, the command capture module obtains NVMe management completion commands from the management completion queue and the NVMe I / O completion queue in the accelerator card's local memory via direct memory access, and writes them into the management completion queue and the corresponding I / O completion queue in the host memory via direct memory access.

4. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The virtual queue binding module reads NVMe I / O commands from the I / O submission queue in the local memory of the accelerator card through memory read and write control and parses the user ID field in the command. Then, based on the user ID, it writes the NVMe I / O commands into the specified virtual I / O submission queue in the local memory of the accelerator card through memory read and write control. The I / O processing module reads and processes NVMe I / O commands from the virtual I / O submission queue in the accelerator card's local memory through memory read / write control. After processing, the I / O processing module generates the corresponding NVMe I / O completion command and writes the NVMe I / O completion command into the corresponding I / O completion queue in the accelerator card's local memory through memory read / write control.

5. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The I / O bandwidth fair scheduling module obtains the amount of data transmitted by each user / application in real time by reading registers, and accumulates the data amount into the bandwidth accumulation register corresponding to each user / application by writing to registers. Then, the I / O bandwidth fair scheduling module uses the value in the bandwidth accumulation register to obtain the I / O bandwidth obtained by each user / application in real time and selects the user with the smallest obtained I / O bandwidth. Finally, the I / O bandwidth fair scheduling module sets the virtual I / O submission queue corresponding to the accelerator card's local memory to an active state according to the user ID of the selected user, while setting the virtual I / O submission queues corresponding to other user IDs to a silent state, thereby limiting the I / O command processing speed of high-bandwidth users and accelerating the I / O command processing speed of low-bandwidth users.

6. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The management module includes a queue processing submodule, a data processing submodule, and a completion processing submodule; The queue processing submodule reads NVMe management commands from the management submission queue in the local memory of the accelerator card through memory read and write control, identifies and decodes the NVMe management commands, and then selectively retains the decoding results or sends the decoding results to the data processing submodule according to the type of the identified NVMe management command. After receiving the decoding result, the data processing submodule performs address parsing and translation to obtain the source and destination addresses of the data, and transfers the data from the source address to the destination address through direct memory access. When the queue processing submodule completes the processing of retaining the decoding result or the data processing submodule completes the data transfer, it indicates that the processing of the NVMe management command has been completed. The completion processing submodule then generates the NVMe management completion command and writes the NVMe management completion command into the management completion queue in the local memory of the accelerator card through memory read and write control.

7. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The command capture module monitors a management commit queue and eight I / O commit queues in the host memory in real time, and also monitors a management completion queue and eight I / O completion queues in the accelerator card's local memory in real time. When there are new NVMe management commands and NVMe I / O commands in the management commit queue and eight I / O commit queues in the host memory, the command capture module transmits the NVMe management commands to the management commit queue in the accelerator card's local memory and the NVMe I / O commands to the corresponding I / O commit queues in the accelerator card's local memory via direct memory access. When there are new NVMe management completion commands and NVMe I / O completion commands in the management completion queue and eight I / O completion queues in the accelerator card's local memory, the command capture module transmits the NVMe management completion commands to the management completion queue in the host memory and the NVMe I / O completion commands to the corresponding I / O completion queues in the host memory via direct memory access.

8. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The virtual queue binding module includes a user ID parsing submodule and a user ID binding submodule; The user ID parsing submodule reads NVMe I / O commands from eight I / O submission queues in the accelerator card's local memory and extracts the user ID from the commands through memory read / write control. The user ID is then passed to the user ID binding submodule. The user ID binding submodule uses the user ID to search for a virtual I / O submission queue with the same user ID in the virtual I / O submission queue pool corresponding to the I / O submission queue in the accelerator card's local memory. When a virtual I / O submission queue is found, the user ID binding submodule dispatches the NVMe I / O command to that virtual I / O submission queue; otherwise, the user ID binding submodule allocates a new virtual I / O submission queue in the virtual I / O submission queue pool and submits the NVMe I / O command to the newly created virtual I / O submission queue.

9. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The I / O processing module pool contains 16 I / O processing modules, which are evenly distributed to eight virtual I / O commit queue pools. That is, two I / O processing modules process NVMe I / O commands in one virtual I / O commit queue pool in parallel. Each I / O processing module includes a queue processing submodule, a data processing submodule, and a completion processing submodule; The queue processing submodule reads NVMe I / O commands from the active virtual I / O submission queue in the virtual I / O submission queue pool in the local memory of the accelerator card through memory read and write control. Then, it identifies and decodes the NVMe I / O commands and sends the decoding results to the data processing submodule. After receiving the decoding result, the data processing submodule performs address parsing and translation to obtain the source and destination addresses of the data, and then transfers the data from the source address to the destination address through direct memory access. When the data processing submodule completes the data transfer, it indicates that the processing of the NVMe I / O command has been completed. The completion processing submodule then generates an NVMe I / O completion command and writes the NVMe I / O completion command into the corresponding I / O completion queue in the accelerator card's local memory through memory read and write control.

10. The NVMe storage acceleration system with complete hardware offloading according to claim 1, characterized in that, The I / O bandwidth fair scheduling module includes eight command selection submodules, eight bandwidth accumulation submodules, and one fair scheduling submodule. The command selection submodule reads NVMe I / O commands from the virtual I / O submission queue matching the user ID in the virtual I / O submission queue pool in the accelerator card's local memory, based on the user ID specified by the fair scheduling submodule, using memory read / write control. The NVMe I / O commands are then transmitted to the corresponding I / O processing module in the I / O processing module pool for processing. Simultaneously, the bandwidth accumulation submodule monitors the data transmission volume generated during NVMe I / O command processing in real time and accumulates it into the bandwidth accumulation register matching the user ID based on the user ID field of the NVMe I / O command. Subsequently, the fair scheduling submodule reads the values ​​in all bandwidth accumulation registers in real time through register read / write control and sorts them from smallest to largest. When the sorting is complete, the fair scheduling submodule selects the bandwidth accumulation register with the smallest value and reads its user ID through register read / write. Finally, the fair scheduling submodule generates a fair scheduling signal based on the read user ID. This fair scheduling signal is transmitted to the command selection submodule, which sets the virtual I / O submission queues in the virtual I / O submission queue pool that match the user ID to the active state, and sets the virtual I / O submission queues that do not match the user ID to the silent state.

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