Interface method for normalizing discrete quantity output or input

Abstract

The discrete quantity output or input normalization interface circuit and method of the present invention relate to the technical field of airborne computer interfaces. It includes multiple channels, and each channel includes a comparison unit, a D / A conversion unit, a current conversion unit, a P-channel power switch tube Q1, a P-channel power switch tube Q2, an N-channel power switch tube Q3, and a controller. The method can be configured as a 28V / open discrete quantity output interface, a ground / open discrete quantity output interface, a 28V / open discrete quantity input interface, or a ground / open discrete quantity input interface. The method also includes inverse time overcurrent protection for the output interface. By comprehensively applying the normalization interface and method of the present invention, the types of interfaces inside the remote interface unit or the electromechanical management computer can be reduced, the versatility of the product and the interface utilization rate can be improved, and the 28V / open or ground / open discrete quantity output or input interface multiplexing, reconstruction, and high-reliability output and input can be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of airborne computer interfaces, and particularly relates to an interface method for normalizing discrete quantity output or input. Background Art

[0002] Aircraft airborne systems usually include a large number of 28V / open discrete quantity output interfaces, ground / open discrete quantity output interfaces, 28V / open discrete quantity input interfaces, and ground / open discrete quantity input interfaces, which are used for output driving of relays, contactors, and solenoid valves, or acquisition and precise control of sensor states. With the development of mechatronics integration, this type of interface is integrated into the core important components of the mechatronics control and management system, namely the remote interface unit or the mechatronics management computer. The traditional ground / open discrete quantity output interface and the ground / open discrete quantity input interface are implemented by different dedicated circuits, and they are functionally independent of each other. When designing, a large number of external connector pins need to be configured as signal outputs or inputs. When the product needs to be reused on different aircraft, the required quantities of the ground / open discrete quantity output interface and the ground / open discrete quantity input interface on different aircraft are different, resulting in the inability to reuse the product. It is necessary to re-perform functional design and interface definition. The product has poor versatility, low interface utilization rate, a large variety of types, high maintenance costs, a long design cycle, is not convenient for product standardization and pedigree planning, and does not meet the requirements of the new generation of aircraft for the adaptability, homogeneity, and reuse and reconstruction of the remote interface unit or the mechatronics management computer interface. Summary of the Invention

[0003] In view of this, the present invention provides a normalized interface circuit for discrete quantity output or input, which reduces the types of interfaces inside the remote interface unit or the mechatronics management computer, improves the versatility and interface utilization rate of the product, and realizes the reuse, reconstruction, and high-reliability output and input of the 28V / open discrete quantity output interface, the ground / open discrete quantity output interface, the 28V / open discrete quantity input interface, and the ground / open discrete quantity input interface.

[0004] A normalized interface circuit for discrete quantity output or input is provided, which is applicable to power control of an airborne mechatronics system. It includes multiple channels, and each channel includes a comparison unit, a D / A conversion unit, a current conversion unit, a P-channel power switch tube Q1, a P-channel power switch tube Q2, an N-channel power switch tube Q3, and a controller, where:

[0005] The busbar current of the mechatronics system is converted into a voltage by the current conversion unit and then delivered to the comparison unit;

[0006] The comparison unit is used to compare the outputs of the current conversion unit and the D / A conversion unit, and input the comparison result into the controller. The D / A conversion unit is used to receive the control instruction of the controller and convert it into a voltage;

[0007] The output terminal of each channel is connected to the copper plane on the PCB board through the diode D2, that is, it is connected to the "common area". A TVS tube for lightning protection is connected to the "common area", and the TVS tube is connected to the chassis ground. A diode D3, a diode D4 and a capacitor C are connected in parallel between the chassis ground and the power ground to limit the voltage difference between the chassis ground and the power ground.

[0008] The output terminal of the current conversion unit is connected to the source electrode of the power switch tube Q1. The drain electrode of Q1 is connected to the source electrode of the power switch tube Q2. The drain electrode of the power switch tube Q2 is connected to the drain electrode of the power switch tube Q3. The source electrode of the power switch tube Q3 is connected to the power ground. A freewheeling diode D1 is connected in anti-parallel between the drain electrode and the source electrode of the power switch tube Q3.

[0009] The gate electrodes of the power switch tubes Q1, Q2 and Q3 are respectively connected to the controller through the first driving unit, the second driving unit and the third driving unit 3. Between the drain electrode of the power switch tube Q1 and the source electrode of Q2, and between the drain electrode of the power switch tube Q2 and the drain electrode of Q3, they are respectively connected to the controller through the first discrete quantity input unit and the second discrete quantity input unit.

[0010] The technical beneficial effects of the present invention:

[0011] It is applicable to 28V open output, ground open output, 28V open input and ground open input, with a wider applicable range, higher integration, fewer power tubes used, and can prevent the through-fault of a single power tube. Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0013] Figure 1 It is a functional block diagram of a discrete quantity output / input normalization interface.

[0014] Figure 2 It is a flow chart of a discrete quantity output / input normalization method.

[0015] Figure 3 It is a logic control block diagram of a discrete quantity input. Detailed Embodiments

[0016] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0017] The following describes the embodiments of the present disclosure through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all embodiments. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0018] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement a device and / or practice a method. Additionally, this device and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0019] As Figure 1 shown, the discrete quantity output or input normalization interface circuit is applicable to the power control of an airborne electromechanical system. It is characterized in that it includes multiple channels, and each channel includes a comparison unit, a D / A conversion unit, a current conversion unit, a P-channel power switch tube Q1, a P-channel power switch tube Q2, an N-channel power switch tube Q3, and a controller. The controller is an FPGA controller and is electrically connected to a CPU processor, where:

[0020] The busbar current of the electromechanical system is converted into a voltage by the current conversion unit and then delivered to the comparison unit;

[0021] The comparison unit is used to compare the outputs of the current conversion unit and the D / A conversion unit, and input the comparison result into the controller. The D / A conversion unit is used to receive the control instruction from the controller and convert it into a voltage;

[0022] The output terminal of each channel is connected to the copper foil plane on the PCB circuit board through a diode D2, that is, connected to the "common area". The "common area" is connected with a TVS tube for lightning protection, and the TVS tube is connected to the chassis ground. A diode D3, a diode D4, and a capacitor C are connected in parallel between the chassis ground and the power ground to limit the voltage difference between the chassis ground and the power ground;

[0023] The output terminal of the current conversion unit is connected to the source electrode of power switch Q1. The drain electrode of Q1 is connected to the source electrode of power switch Q2. The drain electrode of power switch Q2 is connected to the drain electrode of power switch Q3. The source electrode of power switch Q3 is connected to the power ground, and a freewheeling diode D1 is anti-parallelly connected between the drain and source electrodes of power switch Q3.

[0024] The gate electrodes of power switches Q1, Q2, and Q3 are respectively connected to the controller through the first driving unit 1, the second driving unit 2, and the third driving unit 3. Between the drain electrode of power switch Q1 and the source electrode of Q2, and between the drain electrode of power switch Q2 and the drain electrode of Q3, they are respectively connected to the controller through the first discrete quantity input unit 1 and the second discrete quantity input unit 2. The first discrete quantity input unit 1 and the second discrete quantity input unit 2 use the 8-channel dedicated discrete quantity acquisition chip DEI1282 of DEI Company or the 8-channel dedicated discrete quantity acquisition chip HKA1223 of domestic Xiangteng Company. It is applicable to 28v open output, ground open output, 28v open input, and ground open input, with a wider applicable range, higher integration, fewer power tubes used, and can prevent the through-fault of a single power tube.

[0025] The CPU processor realizes the configuration of interface output and input types, and the configuration of the current protection point and duration of the protection unit, and comprehensively judges the BIT status of the interface and the over-current trip status.

[0026] The FPGA controller realizes the configuration and acquisition of the protection unit and the discrete quantity input unit, sends the driving unit control signal, and combines the information sent by the protection unit and the CPU controller to realize output protection.

[0027] The protection unit realizes the indication of the over-current protection status.

[0028] The power unit realizes discrete quantity output.

[0029] The discrete quantity input unit realizes the acquisition of the interface output and input status.

[0030] The lightning protection unit realizes the lightning protection of the interface.

[0031] The grounding unit realizes the reliable grounding of the power part of the interface.

[0032] The input “+” terminal of the comparison unit is connected to the output of the D / A conversion unit. The input “-” terminal of the comparison unit is connected to the output of the current conversion unit. The output of the comparison unit is connected to the general-purpose I / O of the FPGA controller.

[0033] Such as Figure 2Provide an interface method for discrete quantity output or input normalization, using the above circuit, including a CPU processor communicating with a controller, and the controller is an FPGA controller. The method includes:

[0034] The interface is configured as a 28V / open discrete quantity output interface, a ground / open discrete quantity output interface, a 28V / open discrete quantity input interface, or a ground / open discrete quantity input interface, where: during the same power-on period, the interface can be repeatedly configured and multiplexed in a time-sharing manner.

[0035] As a partial embodiment provided in this case, the interface is configured as a 28V / open discrete quantity output. The steps for outputting "28V" are:

[0036] Step 1: The CPU processor configures the input modes of the first discrete quantity input unit 1 and the second discrete quantity input unit 2 as 28V / open discrete quantity input through the FPGA controller; the CPU processor configures the drive signal of the third drive unit 3 to the "on" state through the FPGA controller.

[0037] Step 2: The CPU processor configures the signals of the first drive unit 1 and the second drive unit 2 to the "on" state through the FPGA controller. The CPU processor collects the states of the first discrete quantity input unit 1 and the second discrete quantity input unit 2 through the FPGA controller. If the collection results are both in the "on" state, execute Step 3; otherwise, simultaneously lock the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state, report a 28V / open discrete quantity output interface fault, and do not execute the subsequent steps.

[0038] Step 3: The CPU processor configures the drive signal of the first drive unit 1 to the "28V" state through the FPGA controller. The CPU processor collects whether the state of the first discrete quantity input unit 1 is in the "28V" state through the FPGA controller. If not, simultaneously lock the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state, report a 28V / open discrete quantity output interface fault and a power switch tube Q1 fault, and do not execute the subsequent steps. If so, the CPU processor configures the drive signal of the second drive unit 2 to the "28V" state through the FPGA controller. The FPGA controller collects that the state of the second discrete quantity input unit 2 is in the "28V" state; otherwise, simultaneously lock the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state, report a 28V / open discrete quantity output interface fault and a power switch tube Q2 fault.

[0039] As a partial embodiment provided in this case, the interface is configured as a 28V / open discrete quantity output. The method for outputting "on" includes:

[0040] Step 1: The CPU processor configures the input modes of the first discrete input unit 1 and the second discrete input unit 2 as 28V / open discrete input through the FPGA controller; the CPU processor configures the drive signal of the third drive unit 3 to the "on" state through the FPGA controller.

[0041] Step 2: The CPU processor configures the drive signal of the second drive unit 2 to the "on" state through the FPGA controller. The CPU processor acquires the state of the second discrete input unit 2 as the "on" state through the FPGA controller. Otherwise, lock the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state, report a 28V / open discrete output interface fault and a power switch tube Q2 fault, and do not execute the subsequent steps.

[0042] Step 3: The CPU processor configures the drive signal of the first drive unit 1 to "on" through the FPGA controller. The CPU processor acquires the state of the first discrete input unit 1 as the "on" state through the FPGA controller. Otherwise, lock the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state, report a 28V / open discrete output interface fault and a power switch tube Q1 fault, and do not execute the subsequent steps.

[0043] As some implementation manners provided in this case, the interface is configured as ground / open discrete output. The method for outputting "ground" includes:

[0044] Step 1: The CPU processor configures the input modes of the first discrete input unit 1 and the second discrete input unit 2 as ground / open discrete input through the FPGA controller; the CPU processor configures the drive signals of the first drive unit 1 and the second drive unit 2 to the "on" state through the FPGA controller.

[0045] Step 2: The CPU processor configures the drive signal of the third drive unit 3 to the "on" state through the FPGA controller. The CPU processor acquires the states of the first discrete input unit 1 and the second discrete input unit 2 through the FPGA controller. If the acquisition results are both "on" states, execute Step 3. Otherwise, lock the drive signals of the first drive unit 1, the second drive unit 2, and the third drive unit 3 to the "on" state, report a ground / open discrete output interface fault and a power switch tube Q3 fault, and do not execute the subsequent steps.

[0046] Step 3: The CPU processor configures the drive signal of the third drive unit 3 to the "ground" state through the FPGA controller. The CPU processor acquires the states of the first discrete input unit 1 and the second discrete input unit 2 through the FPGA controller. If the acquisition results are both "ground" states, report that the ground / open discrete output interface is normal. Otherwise, report a ground / open discrete output interface fault.

[0047] As part of the embodiments provided in this case, when the interface is configured for ground / open discrete output, the method for outputting "open" includes:

[0048] Step 1: The CPU processor configures the input modes of the first discrete input unit 1 and the second discrete input unit 2 as ground / open discrete input through the FPGA controller; the CPU processor configures the drive signals of the first drive unit 1 and the second drive unit 2 to the "open" state through the FPGA controller;

[0049] Step 2: The CPU processor configures the drive signal of the third drive unit 3 to the "open" state through the FPGA controller. The CPU processor collects through the FPGA controller that both the first discrete input unit 1 and the second discrete input unit 2 are in the "open" state. Otherwise, lock the drive signals of the first drive unit 1, the second drive unit 2, and the third drive unit 3 to the "open" state, and report a ground / open discrete output interface fault.

[0050] As part of the embodiments provided in this case, the method for protection when the interface is configured for 28V / open discrete output includes:

[0051] Configure the trip threshold: The CPU processor configures the output voltage of the D / A conversion unit through the FPGA controller, and configures the current amplitude threshold for overcurrent protection of the 28V / open discrete output interface;

[0052] Configure the trip time: The CPU processor configures the sustainable time for overcurrent protection of the 28V / open discrete output interface through the FPGA controller. The FPGA controller accumulates the duration of the comparator outputting a high level. The FPGA controller sets the trip state by comparing in real time the sustainable time configured by the CPU processor and the accumulated duration.

[0053] Configure the trip strategy: When the interface is in the trip state, perform three clearing trip retry operations. When the clearing trip fails three times in a row, lock the trip state, lock the drive signals of the first drive unit 1, the second drive unit 2, and the second drive unit 2 to the "open" state, and report a discrete output interface fault.

[0054] As part of the embodiments provided in this case, the method for the interface to be configured for 28V / open discrete input or ground / open discrete input includes:

[0055] Step 1: The CPU processor configures the input modes of the first discrete input unit 1 and the second discrete input unit 2 as 28V / open or ground / open discrete input simultaneously through the FPGA controller; the CPU processor configures the drive signals of the first drive unit 1, the second drive unit 2, and the third drive unit 3 to the "open" state through the FPGA controller;

[0056] Step 2: The FPGA controller simultaneously stores the acquisition results of the first discrete quantity input unit 1 and the second discrete quantity input unit 2 into data register 1 and data register 2;

[0057] Step 3: The FPGA controller compares the results of data register 1 and data register 2 according to the principle of bit-by-bit comparison;

[0058] Step 4: When the results of the same bit in data register 1 and data register 2 are the same after comparison by the FPGA controller, the result is stored in the redundant register; otherwise, a "FAULT" signal is issued.

[0059] The above are only specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An interface method for discrete quantity output or input normalization, applicable to power control of an airborne electromechanical system, characterized in that, It includes multiple channels, and each channel includes a comparison unit, a controller, a D / A conversion unit, a current conversion unit and a power unit. The power unit includes a P-channel power switch tube Q1, a P-channel power switch tube Q2 and an N-channel power switch tube Q3. The power unit is electrically connected to the discrete input unit controller through a drive unit. The drive unit includes a first drive unit, a second drive unit and a third drive unit. The discrete input unit includes a first discrete input unit and a second discrete input unit. The electromechanical system bus current is converted into a voltage by the current conversion unit and then transmitted to the comparison unit; the comparison unit is used to compare the output of the current conversion unit with the output of the D / A conversion unit and input the comparison result to the controller. The D / A conversion unit is used to receive the control instruction of the controller and convert it into a voltage; the output end of each channel is connected to the copper plane on the PCB circuit board through a diode D2, that is, connected to the "public area". The "public area" is connected to a TVS tube for lightning protection, and the TVS tube is connected to the casing. A diode D3, a diode D4, and a capacitor C are connected in parallel between the chassis ground and the power ground to limit the voltage difference between the chassis ground and the power ground; the output end of the current conversion unit is connected to the source of the power switch tube Q1, the drain of Q1 is connected to the source of the power switch tube Q2, and the drain of the power switch tube Q2 is connected to the drain of the power switch tube Q3; the source of the power switch tube Q3 is connected to the power ground, and a freewheeling diode D1 is connected in anti-parallel between the drain and source of the power switch tube Q3; the gates of the power switch tubes Q1, Q2, and Q3 are connected to the controller through a first drive unit, a second drive unit, and a third drive unit, respectively; the drain of the power switch tube Q1 and the source of Q2, and the drain of the power switch tube Q2 and the drain of Q3 are connected to the controller through a first discrete input unit and a second discrete input unit, respectively; the interface output and input states are collected respectively through a discrete output or input normalization interface circuit; the controller communicates with a CPU processor, and the controller is an FPGA controller. The method includes: The interface is configured as a 28V / open discrete output interface, a ground / open discrete output interface, a 28V / open discrete input interface, or a ground / open discrete input interface. The interface can be repeatedly configured and time-multiplexed during the same power-on period. The method of configuring the interface as a 28V / open discrete input or a ground / open discrete input includes: Step 1: The CPU processor configures the input modes of the first discrete input unit and the second discrete input unit to be 28V / open or ground / open discrete input at the same time through the FPGA controller; the CPU processor configures the drive signals of the first drive unit, the second drive unit, and the third drive unit 3 to be in the "open" state through the FPGA controller; Step 2: The FPGA controller simultaneously places the collection results of the first discrete input unit and the second discrete input unit into data register 1 and data register 2; Step 3: The FPGA controller compares the results of data register 1 and data register 2 according to the principle of bit-by-bit comparison; Step 4: The FPGA controller compares the same bit of data register 1 and data register 2. If the result is the same, the result is stored in the redundant register; otherwise, a "FAULT" signal is issued.

2. The interface method according to claim 1, wherein The interface is configured as 28V / open discrete output. The steps to output "28V" are: Step 1: The CPU processor configures the input mode of the first discrete input unit and the second discrete input unit to 28V / open discrete input through the FPGA controller; the CPU processor configures the drive signal of the third drive unit 3 to the "open" state through the FPGA controller; Step 2: The CPU processor configures the signals of the first drive unit and the second drive unit to be in the "on" state through the FPGA controller. The CPU processor collects the states of the first discrete input unit and the second discrete input unit through the FPGA controller. If the collected results are both in the "on" state, step 3 is executed; otherwise, the drive signals of the first drive unit and the second drive unit are simultaneously locked to the "on" state, a 28V / open discrete output interface fault is reported, and subsequent steps are not executed; Step 3: The CPU processor configures the driving signal of the first driving unit to be in the "28V" state through the FPGA controller, and the CPU processor collects the state of the first discrete input unit through the FPGA controller to see if it is in the "28V" state. If not, the CPU processor simultaneously locks the driving signals of the first driving unit and the second driving unit to the "on" state, reports a 28V / open discrete output interface fault and a power switch tube Q1 fault, and no longer executes subsequent steps. If so, the CPU processor configures the driving signal of the second driving unit to be in the "28V" state through the FPGA controller, and the FPGA controller collects the state of the second discrete input unit to see if it is in the "28V" state. Otherwise, the CPU processor simultaneously locks the driving signals of the first driving unit and the second driving unit to the "on" state, reports a 28V / open discrete output interface fault and a power switch tube Q2 fault.

3. The interface method according to claim 2, wherein The interface is configured as a 28V / on discrete output. The output "on" methods include: Step 1: The CPU processor configures the input mode of the first discrete input unit and the second discrete input unit to 28V / open discrete input through the FPGA controller; the CPU processor configures the drive signal of the third drive unit 3 to the "open" state through the FPGA controller; Step 2: The CPU processor configures the driving signal of the second driving unit to be in the "on" state through the FPGA controller. The CPU processor collects the state of the second discrete input unit through the FPGA controller and finds that it is in the "on" state. Otherwise, the driving signals of the first driving unit and the second driving unit are locked to the "on" state, and a 28V / open discrete output interface fault and a power switch tube Q2 fault are reported, and the subsequent steps are not executed. Step 3: The CPU processor configures the driving signal of the first driving unit to "on" through the FPGA controller. The CPU processor collects the state of the first discrete quantity input unit as the "on" state through the FPGA controller. Otherwise, lock the driving signals of the first driving unit and the second driving unit to the "on" state, report a 28V / on discrete quantity output interface fault and a power switch tube Q1 fault, and do not execute the subsequent steps.

4. The interface method according to claim 3, wherein The interface is configured as a ground / on discrete quantity output. The method for outputting "ground" includes: Step 1: The CPU processor configures the input modes of the first discrete quantity input unit and the second discrete quantity input unit as ground / on discrete quantity inputs through the FPGA controller. The CPU processor configures the driving signals of the first driving unit and the second driving unit to the "on" state through the FPGA controller. Step 2: The CPU processor configures the driving signal of the third driving unit 3 to the "on" state through the FPGA controller. The CPU processor collects the states of the first discrete quantity input unit and the second discrete quantity input unit through the FPGA controller. If the acquisition results are both in the "on" state, execute Step 3. Otherwise, lock the driving signals of the first driving unit, the second driving unit, and the third driving unit 3 to the "on" state, report a ground / on discrete quantity output interface fault and a power switch tube Q3 fault, and do not execute the subsequent steps. Step 3: The CPU processor configures the driving signal of the third driving unit 3 to the "ground" state through the FPGA controller. The CPU processor collects the states of the first discrete quantity input unit and the second discrete quantity input unit through the FPGA controller. If the acquisition results are both in the "ground" state, report that the ground / on discrete quantity output interface is normal. Otherwise, report a ground / on discrete quantity output interface fault.

5. The interface method according to claim 4, wherein When the interface is configured as a ground / on discrete quantity output, the method for outputting "on" includes: Step 1: The CPU processor configures the input modes of the first discrete quantity input unit and the second discrete quantity input unit as ground / on discrete quantity inputs through the FPGA controller. The CPU processor configures the driving signals of the first driving unit and the second driving unit to the "on" state through the FPGA controller. Step 2: The CPU processor configures the driving signal of the third driving unit 3 to the "on" state through the FPGA controller. The CPU processor collects that both the first discrete quantity input unit and the second discrete quantity input unit are in the "on" state through the FPGA controller. Otherwise, lock the driving signals of the first driving unit, the second driving unit, and the third driving unit 3 to the "on" state and report a ground / on discrete quantity output interface fault.

6. The interface method according to claim 5, wherein The protection method when the interface is configured as a 28V / on discrete quantity output includes: Configure the trip gate limit: The CPU processor configures the output voltage of the D / A conversion unit through the FPGA controller and configures the current amplitude gate limit for overcurrent protection of the 28V / on discrete quantity output interface. Configure the trip time: The CPU processor configures, through the FPGA controller, the sustainable time for overcurrent protection of the 28V / open discrete output interface. The FPGA controller accumulates the duration of the high-level output of the comparator. The FPGA controller sets the trip state by comparing in real time the sustainable time configured by the CPU processor and the accumulated duration. Configure the trip strategy: When the interface is in the trip state, perform three clearing trip retry operations. When the clearing trip fails three times in a row, lock the trip state, lock the drive signals of the first drive unit, the second drive unit, and the second drive unit to the "on" state, and report a discrete output interface fault.

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