Netlist reduction method, chip verification method and computer storage medium

Abstract

The netlist reduction method, chip verification method and computer storage medium of the present application, when the number of connection nodes of the target node is greater than the number threshold, eliminate the target node, and perform equivalent transformation on a part of the connection resistance, and transfer the other part to one of the connection nodes, which can eliminate the node and avoid the increase of the number of resistances, thereby improving the reduction efficiency of the netlist, and the error rate is small. Among them, a netlist reduction method of the present application includes the following steps: obtaining a target node to be eliminated in the netlist, wherein the target node is connected to the connection node through a connection resistance; when the number of connection nodes of the target node is greater than the number threshold, eliminate the target node, and perform equivalent transformation on a part of the connection resistance, and transfer the other part to one of the connection nodes.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a netlist reduction method, a chip verification method and a computer storage medium. Background Art

[0002] As the scale and complexity of chips continue to increase, the role of chip verification is becoming more and more important. In the chip verification process, the parasitic resistance and capacitance circuit netlist (referred to as netlist) obtained by parasitic parameter extraction will be passed to the subsequent timing verification. Therefore, the size of the netlist will directly affect the running time of the subsequent timing verification.

[0003] In order to shorten the running time of the verification link and accelerate the iteration cycle of the chip, it is necessary to reduce (reduce) the large-scale netlist so as to reduce at least one of the number of nodes and the number of resistors in the large-scale netlist while maintaining the equivalence of the netlist. However, the existing netlist reduction method may increase the number of resistors in the netlist while eliminating nodes, resulting in low netlist reduction efficiency. Summary of the invention

[0004] In response to the above technical problems, the present application provides a netlist reduction method that can eliminate nodes while avoiding an increase in the number of resistors, thereby improving the netlist reduction efficiency.

[0005] Technical Solution 1

[0006] A netlist reduction method, characterized in that it comprises the following steps:

[0007] Acquire a target node to be eliminated in the netlist, wherein the target node is connected to the connection node through a connection resistor;

[0008] After determining whether the number of connected nodes of the target node is greater than the number threshold, then:

[0009] Case 1: when the number of connection nodes of the target node is greater than the number threshold, the target node is eliminated, and a part of the connection resistance is equivalently transformed, and the other part is transferred to one of the connection nodes;

[0010] In case 2, when the number of nodes connected to the target node is not greater than the number threshold, the target node is eliminated and the connection resistance is equivalently transformed.

[0011] The netlist reduction method is characterized in that the first situation is specifically as follows:

[0012] The connection resistance whose resistance value is less than the resistance threshold is equivalently transformed; and the connection resistance whose resistance value is not less than the resistance threshold is transferred to one of the connection nodes.

[0013] The netlist reduction method is characterized in that the resistance threshold is determined according to the minimum value of the resistance values ​​of the connection resistors.

[0014] The netlist reduction method is characterized in that, in case 1, the "one of the connection nodes" is a connection node corresponding to the connection resistor with the smallest resistance value.

[0015] The netlist reduction method is characterized in that the "equivalent transformation of connection resistors whose resistance values ​​are less than the resistance threshold" is specifically implemented by using the TICER algorithm.

[0016] The netlist reduction method is characterized in that the number threshold is greater than or equal to 3.

[0017] The netlist reduction method is characterized in that the target node to be eliminated in the netlist is obtained, and the implementation method is:

[0018] Obtaining the time constant of the node to be confirmed in the netlist;

[0019] When the time constant of the node to be confirmed is not within a preset frequency range, the node to be confirmed is determined to be the target node to be eliminated.

[0020] The netlist reduction method is characterized in that the netlist reduction method further comprises:

[0021] When it is determined that there is a node to be confirmed in the netlist, the step of obtaining the time constant of the node to be confirmed in the netlist is entered.

[0022] Technical Solution 2

[0023] A chip verification method, characterized by comprising:

[0024] The netlist reduction method generates a netlist after nodes are eliminated;

[0025] Timing verification is performed based on the netlist after the nodes are eliminated.

[0026] Technical Solution 3

[0027] A computer storage medium, characterized in that a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the netlist reduction method is implemented.

[0028] The netlist reduction method, chip verification method and computer storage medium of the present application eliminate the target node when the number of connection nodes of the target node is greater than the number threshold, and perform equivalent transformation on a part of the connection resistance, and transfer the other part to one of the connection nodes. This can eliminate the node and avoid the increase in the number of resistances, thereby improving the netlist reduction efficiency and reducing the error rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of a netlist reduction method according to the first embodiment of the present application;

[0030] Figure 2 is a schematic diagram comparing the netlist structures before and after node elimination according to an embodiment of the present application;

[0031] Figure 3 It is a flowchart of a netlist reduction method according to the second embodiment of the present application. DETAILED DESCRIPTION

[0032] The following is an explanation of the implementation of the present application by means of specific embodiments. People familiar with the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0033] In the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0034] Although the terms first, second, etc. are used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0035] Furthermore, as used in this article, the singular forms "one", "an" and "the" are intended to include plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0036] First embodiment

[0037] Figure 1 FIG. 1 is a flow chart of a netlist reduction method according to the first embodiment of the present application. Figure 1 As shown, a netlist reduction method comprises the following steps:

[0038] Obtaining a target node to be eliminated in the netlist, wherein the target node is connected to the connection node through a connection resistor;

[0039] Determine whether the number of connected nodes of the target node is greater than the number threshold;

[0040] When the number of connection nodes is greater than the number threshold, the target node is eliminated, and a part of the connection resistance is equivalently transformed, and the other part is transferred to one of the connection nodes;

[0041] When the number of nodes connected to the target node is not greater than the number threshold, the target node is eliminated and the connection resistance is equivalently transformed.

[0042] In one embodiment, obtaining the target node to be eliminated in the netlist may include but is not limited to: obtaining the time constant of the node to be confirmed in the netlist; when the time constant of the node to be confirmed is not within a preset frequency range, determining that the node to be confirmed is the target node to be eliminated.

[0043] Among them, the time constant of the node to be confirmed is the total capacitance of the node to be confirmed to other nodes and to the ground divided by the total conductance of the node to be confirmed to other nodes and to the ground. By comparing the time constant of the node to be confirmed with the preset frequency range, the node to be confirmed whose time constant is not within the preset frequency range can be classified as a fast node or a slow node, and the node to be confirmed whose time constant is within the preset frequency range can be classified as a general node (or ordinary node). Fast nodes and slow nodes actually do not have a large impact on system performance within the frequency range of concern, so fast nodes and slow nodes, that is, nodes to be confirmed whose time constant is not within the preset frequency range, can be determined as target nodes to be eliminated, and then the target nodes to be eliminated can be eliminated from the netlist to reduce the size of the netlist. Among them, the preset frequency range can be pre-set by the system, or it can be set by the user according to needs.

[0044] In one embodiment, when the number of connection nodes is greater than a number threshold, the target node is eliminated, and a portion of the connection resistance is equivalently transformed, and the other portion is transferred to one of the connection nodes, including: equivalently transforming the connection resistance whose resistance value is less than the resistance threshold; transferring the connection resistance whose resistance value is not less than the resistance threshold to one of the connection nodes.

[0045] In one embodiment, the resistance threshold is determined according to the minimum value among the resistance values ​​of the connection resistors. Specifically, the resistance threshold may be R=t×R1, where t is a preset value and R1 is the minimum value among the resistance values ​​of the connection resistors. Wherein, t may be determined according to the upper limit value of the error rate. In other embodiments, the resistance threshold may also be other values ​​preset by the system or input by the user.

[0046] In one embodiment, in order to reduce the error caused by node elimination, the connection resistor with a resistance value not less than the resistance threshold can be transferred to the connection node corresponding to the connection resistor with the smallest resistance value. In other embodiments, the connection resistor with a resistance value not less than the resistance threshold can also be transferred to other connection nodes.

[0047] In one implementation, a TICER (Time Constant Equilibration Reduction) algorithm may be used to perform an equivalent transformation on the connection resistance. In other implementations, other algorithms may also be used to perform an equivalent transformation on the connection resistance, and the present application is not limited thereto.

[0048] Specifically, if the target node to be eliminated is connected to m connection nodes in sequence through the first connection resistor to the mth connection resistor R1~Rm, and m is greater than the number threshold, wherein the resistance values ​​of the first connection resistor R1 to the mth connection resistor are from small to large. If the resistance values ​​of the first connection resistor to the nth connection resistor R1~Rn are all less than the resistance threshold R, and the resistance values ​​of the n+1th connection resistor to the mth connection resistor R(n+1)~Rm are greater than the resistance threshold R, wherein n is less than m. Then the first connection resistor R1 to the nth connection resistor Rn are equivalently transformed, and the resistance values ​​of the n+1th connection resistor to the mth connection resistor are transferred to other connection nodes, for example, to the first connection node corresponding to the first connection resistor R1. Figure 2 For example:

[0049] Take m=6, n=3, R=t×R1 as an example. Figure 2 As shown in (a), the target node 0 to be eliminated is connected to the six connection nodes 1, 2, 3, 4, 5, and 6 in sequence through the first connection resistor to the sixth connection resistor R1, R2, R3, R4, R5, and R6, wherein the resistance values ​​of the first connection resistor to the third connection resistor R1, R2, and R3 are all less than the resistance threshold R, and the fourth connection resistor to the sixth connection resistor R4, R5, and R6 are all greater than the resistance threshold R, then Figure 2 As shown in (b), the target node 0 is eliminated, and the resistance values ​​of the first connection resistor to the third connection resistor R1, R2, and R3 are equivalently transformed. For example, the resistance values ​​of the first connection resistor to the third connection resistor R1, R2, and R3 are equivalently transformed by the TICER algorithm, and the fourth connection resistor to the sixth connection resistor R4, R5, and R6 are transferred to the first connection node 1.

[0050] Specifically, the equivalent transformation of the first connection resistor to the third connection resistor R1, R2, R3 by the above TICER algorithm can be:

[0051] A new resistor is inserted between any two adjacent connection nodes among the first connection node 1, the second connection node 2, and the third connection node 3, such as Figure 2 As shown in (b), the first new resistor r1 is inserted between the first connection node 1 and the second connection node 2, the second new resistor r2 is inserted between the second connection node 1 and the third connection node 2, and the third new resistor r3 is inserted between the first connection node 1 and the third connection node 3. The conductance of the first new resistor r1 is equal to g1g2 / (g1+g2+g3), the conductance of the second new resistor is equal to g2g3 / (g1+g2+g3), and the conductance of the third new resistor r3 is equal to g1g3 / (g1+g2+g3), wherein g1 is the conductance of the first connection resistor R1, g2 is the conductance of the second connection resistor R2, and g3 is the conductance of the third connection resistor R3.

[0052] The netlist reduction method of this embodiment eliminates the target node when the number of connection nodes of the target node is greater than the number threshold, and performs equivalent transformation on a part of the connection resistance, and transfers the other part to one of the connection nodes. This can eliminate the node and avoid the increase in the number of resistances, thereby improving the netlist reduction efficiency and reducing the error rate.

[0053] Second embodiment

[0054] like Figure 3 As shown, the netlist reduction method of this embodiment includes the following steps:

[0055] Step S30: Obtain the nodes to be confirmed in the netlist;

[0056] In one embodiment, the nodes to be confirmed in the netlist are obtained by traversing the netlist. Traversing the netlist means visiting each node in the netlist in turn along a certain search route. The operation performed on the visited node may be to check the value of the node, update the value of the node, etc.

[0057] Step S31: Obtain the time constant of the node to be confirmed in the netlist;

[0058] Step S32: determining whether the time constant of the node to be confirmed is within a preset frequency range;

[0059] If the time constant of the node to be confirmed is within the unpreset frequency range, the process proceeds to step S33: determining the node to be confirmed as a target node to be eliminated;

[0060] Step S34: determine whether the number of connected nodes of the target node is greater than the number threshold;

[0061] If it is greater than the number threshold, then go to step S35: eliminate the target node, perform equivalent transformation on a part of the connection resistance, and transfer the other part to one of the connection nodes;

[0062] If it is not greater than the number threshold, then proceed to step S36: eliminate the target node and perform equivalent transformation on the connection resistance;

[0063] In one embodiment, the number threshold may be preset by the system but is not limited to it, and may also be set by the user according to the needs. When the TICER algorithm is used to perform equivalent transformation on the connection resistance, the number threshold may be, for example, 3 or an integer greater than 3. Specifically, since the TICER algorithm inserts a new resistor between any two adjacent connection nodes when eliminating the target node, if the number of connection resistances before eliminating the target node is N, the number of connection resistances (inserted new resistances) after eliminating the target node is N*(N-1) / 2. Therefore, when N is greater than 3, the number of connection resistances generated after the target node is eliminated will be greater than the number of original connection resistances. Therefore, in the embodiment, the number threshold may be set to 3, so that when the number of connection nodes is greater than 3 or not greater than 3, the problem of low netlist reduction efficiency caused by the increase in the number of resistances after eliminating the target node can be avoided.

[0064] In one embodiment, the netlist reduction method further includes:

[0065] Step S37: Determine whether there is a node to be confirmed in the netlist;

[0066] In one embodiment, after eliminating the target node and performing equivalent transformation and / or transfer processing on the connection resistance, step S35 can be executed: eliminating the target node, and performing equivalent transformation on a part of the connection resistance, and transferring the other part to one of the connection nodes, or after performing step S36: eliminating the target node and performing equivalent transformation on the connection resistance, then entering step S37: determining whether there is a node to be confirmed in the netlist, or after executing step S33: determining that the node to be confirmed is the target node to be eliminated, directly entering step S37: determining whether there is a node to be confirmed in the netlist.

[0067] If there are nodes to be confirmed, return to step S30: obtain the nodes to be confirmed in the netlist;

[0068] In one embodiment, the netlist reduction method further includes:

[0069] If the time constant of the node to be confirmed is within the preset frequency range, the process proceeds to step S37: determining whether there is a node to be confirmed in the netlist.

[0070] In one embodiment, it is possible to determine whether there are unconfirmed nodes in the netlist by determining whether the traversal of the netlist is completed. Specifically, if the traversal of the netlist is completed, it is determined that there are no unconfirmed nodes in the netlist; if the traversal of the netlist is not completed, it is determined that there are unconfirmed nodes in the netlist.

[0071] The netlist reduction method of this embodiment can confirm the target node through the time constant, improve the netlist reduction efficiency, and when the number of connection nodes of the target node is greater than the number threshold, the connection resistance is divided into two parts, one part is equivalently transformed, and the other part is transferred to one of the connection nodes. When the number of connection nodes of the target node is not greater than the number threshold, all the connection resistances are equivalently transformed, which can avoid the increase in the number of connection resistances and reduce the error rate while eliminating the target node, thereby further improving the netlist reduction efficiency.

[0072] The present application also provides a chip verification method, which includes generating a netlist after node elimination according to the above-mentioned netlist reduction method; and performing timing verification according to the netlist after node elimination.

[0073] An embodiment of the present application further provides an intelligent terminal, comprising: a memory and a processor, wherein an operation program is stored in the memory, and when the operation program is executed by the processor, the steps of any of the above methods are implemented.

[0074] An embodiment of the present application further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0075] In the embodiments of the smart terminal and computer-readable storage medium provided in the present application, all technical features of any of the above-mentioned interaction method embodiments may be included, and the expanded and explained contents of the specification are basically the same as those of the embodiments of the above-mentioned methods, and will not be repeated here.

[0076] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.

[0077] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0078] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0079] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0080] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0081] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0083] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A netlist reduction method, characterized in that: The steps include: Acquire a target node to be eliminated in the netlist, wherein the target node is connected to the connection node through a connection resistor; After determining whether the number of connected nodes of the target node is greater than the number threshold, then: Case 1: when the number of connection nodes of the target node is greater than the number threshold, the target node is eliminated, and a part of the connection resistance is equivalently transformed, and the other part is transferred to one of the connection nodes; Case 2: when the number of nodes connected to the target node is not greater than the number threshold, the target node is eliminated and the connection resistance is equivalently transformed; The first situation is as follows: Performing equivalent transformation on the connection resistance whose resistance value is less than the resistance threshold; and transferring the connection resistance whose resistance value is not less than the resistance threshold to one of the connection nodes; The resistance threshold is determined according to the minimum value among the resistance values ​​of the connection resistors; The “one of the connection nodes” is a connection node corresponding to the connection resistance with the smallest resistance value; The "converting the connection resistance whose resistance value is less than the resistance threshold value into equivalent form" is specifically implemented by using the TICER algorithm.

2. The netlist reduction method according to claim 1, characterized in that: The number threshold is greater than or equal to 3.

3. The netlist reduction method according to claim 1, characterized in that: Get the target node to be eliminated in the netlist. The implementation method is: Obtaining the time constant of the node to be confirmed in the netlist; When the time constant of the node to be confirmed is not within a preset frequency range, the node to be confirmed is determined to be the target node to be eliminated.

4. The netlist reduction method according to claim 3, characterized in that: The netlist reduction method further includes: When it is determined that there is a node to be confirmed in the netlist, the step of obtaining the time constant of the node to be confirmed in the netlist is entered.

5. A chip verification method, characterized in that: include: The netlist reduction method according to any one of claims 1 to 4, generating a netlist after node elimination; Timing verification is performed based on the netlist after the nodes are eliminated.

6. A computer storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the netlist reduction method according to any one of claims 1 to 5 is implemented.

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