A radiation-hardened RRAM sense amplifier circuit

Abstract

The application discloses an anti-radiation reinforced RRAM sensitive amplifier circuit, which comprises a linear voltage stabilizing circuit, an adjustable current mirror circuit, an adjustable resistance circuit, a comparator circuit, an inverter circuit, a latch circuit and an anti-radiation reinforced layout structure. The linear voltage stabilizing circuit provides a stable reading voltage to a bit line of a storage unit and adds a limiting amplitude diode to limit the voltage of the bit line; the adjustable current mirror circuit is used for adjusting the amplification multiple of a reading current; the adjustable resistance circuit is used for current-voltage conversion and adjusting the amplification multiple of a voltage; the latch circuit latches an input voltage and outputs a final digital signal; and the anti-radiation reinforced layout structure adopts a ring gate and a reinforced guard ring. The RRAM sensitive amplifier circuit designed in the application has a large load range, a high reading speed, a strong anti-single-particle and total-dose radiation capacity and an easily realized layout layout.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of non-volatile memory circuit design, and in particular to a radiation-hardened RRAM sensitive amplifier circuit. BACKGROUND

[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory, which changes the conductive properties of thin film resistive random access memory (RRAM) by applying an electric field, and realizes the conversion of resistance value. Resistive random access memory (RRAM) has the advantages of simple structure, fast working speed, low power consumption and stable information retention. Based on the storage mechanism of non-charge, it has strong anti-radiation ability and great space application prospect.

[0003] However, resistive random access memory (RRAM) still has some problems to be solved, such as: (1) resistive random access memory (RRAM) does not have fixed high resistance state (HRS) and low resistance state (LRS), and HRS and LRS both have a certain range of process fluctuations, that is, HRSmin≤HRS≤HRSmax, LRSmin≤LRS≤LRSmax, and the ratio of HRSmin / LRSmax is not fixed, and the center value of (HRSmin+LRSmax) / 2 is also not fixed, so it is difficult to determine the read window; (2) although the device formed by resistive random access memory (RRAM) has certain natural anti-radiation ability, the CMOS process devices such as the selection tube and the peripheral circuit of the storage array still face reliability risks in the space radiation environment, such as single particle disturbance, single particle latch-up and ionizing total dose effect.

[0004] How to resist the influence of process fluctuations and space radiation on the reliability of resistive random access memory (RRAM) reading circuit and realize a wide load range anti-radiation hardened sensitive amplifier circuit is a technical problem to be solved in the field. SUMMARY

[0005] The present application provides a single-ended current type sensitive amplifier circuit with anti-radiation reinforcement, which aims to overcome the reliability problem of RRAM sensitive amplifier circuit in space radiation, realize single particle and ionizing total dose radiation reinforcement, and improve the reading reliability.

[0006] In a first aspect, a resistive random access memory (RRAM) sensitive amplifier circuit is provided, characterized in that it comprises a linear voltage stabilizing circuit, an adjustable current mirror circuit, an adjustable resistance circuit, a comparator circuit, an inverter circuit and a latch circuit.

[0007] The linear voltage stabilizing circuit adjusts the bit line voltage of the storage unit to the reading voltage through negative feedback, and generates a reading current on the bit line as the input of the adjustable current mirror circuit.

[0008] The adjustable current mirror circuit is configured to amplify the read current and output an amplified current signal;

[0009] The adjustable resistance circuit is configured to convert the amplified current signal into a voltage signal as a positive input of the comparator circuit;

[0010] The comparator circuit is configured to subtract the positive input voltage from a reference voltage and amplify a difference voltage, and output a comparison result as an input of the inverter circuit;

[0011] The inverter circuit is configured to shape the comparison result output by the comparator circuit as an input of the latch circuit;

[0012] The latch circuit is configured to latch the output voltage of the inverter circuit and output a digital signal as an output of the sense amplifier.

[0013] With reference to the first aspect, in some implementations of the first aspect, the linear voltage regulator circuit comprises: an operational transconductance amplifier, a power N-type metal-oxide-semiconductor (NMOS);

[0014] A positive input stage of the operational transconductance amplifier is connected to a reference voltage, a negative input stage of the operational transconductance amplifier is connected to a drain of the power NMOS and a bit line of a storage unit, an output stage of the operational transconductance amplifier is connected to a gate of the power NMOS, a source of the power NMOS is connected to an input stage of the adjustable current mirror circuit, and the negative input stage and the output stage of the operational transconductance amplifier and the gate and the drain of the power NMOS form a feedback loop.

[0015] With reference to the first aspect, in some implementations of the first aspect, the linear voltage regulator circuit further comprises a zeroing resistor and a Miller capacitor, a positive electrode of the zeroing resistor is connected to an output electrode of the operational transconductance amplifier, a negative electrode of the zeroing resistor is connected to a positive electrode of the Miller capacitor, and a negative electrode of the Miller capacitor is connected to the negative input stage of the operational transconductance amplifier.

[0016] With reference to the first aspect, in some implementations of the first aspect, the feedback loop is connected to ground or a negative power supply VSS.

[0017] With reference to the first aspect, in some implementations of the first aspect, the linear voltage regulator circuit further comprises a grounding resistor, which is electrically connected between the feedback loop and the VSS.

[0018] With reference to the first aspect, in some implementations of the first aspect, the linear voltage regulator circuit further comprises a limiting diode, which is electrically connected between the feedback loop and the VSS.

[0019] In some implementations of the first aspect, the adjustable current mirror circuit includes m+ same-size P-type metal-oxide-semiconductor (PMOS) transistors, each of which has a source connected to ground or a negative power supply, and the m+ same-size PMOS transistors include a reference PMOS and m mirror PMOS transistors, a gate of the reference PMOS and gates of the m mirror PMOS transistors are connected to serve as an input stage of the adjustable current mirror circuit, and drains of the m mirror PMOS transistors serve as an output stage of the adjustable current mirror circuit and are connected to a positive terminal of the adjustable resistance circuit and a positive input stage of the comparator circuit.

[0020] In some implementations of the first aspect, the adjustable resistance circuit includes n resistors connected in series, each of which has the same resistance value, a negative terminal of a first resistor is connected to VSS, and a positive terminal of an nth resistor is connected to the output stage of the adjustable current mirror circuit and the positive input stage of the comparator circuit. REF

[0021] In some implementations of the first aspect, mn*V READ / ((HRSmin+LRSmax) / )*R REF = V COM , V COM is a reference voltage, V READ is a read voltage, HRSmin is a minimum high resistance state resistance, and LRSmax is a maximum low resistance state resistance.

[0022] In some implementations of the first aspect, a positive input stage of the comparator circuit is connected to the output stage of the adjustable current mirror circuit and a positive terminal of the adjustable resistance circuit, a negative input stage of the comparator circuit is connected to a reference voltage, and an output stage of the comparator circuit is connected to an input stage of the inverter circuit.

[0023] In some implementations of the first aspect, the inverter circuit includes two inverters connected in sequence, an input stage of a first inverter is connected to an output stage of the comparator circuit, an output stage of the first inverter is connected to an input stage of a second inverter, and an output stage of the second inverter is connected to an input stage of the latch circuit.

[0024] ​In some implementations of the first aspect, the latch circuit includes four PMOSs of the same size and four NMOSs of the same size, wherein the sources of the PMOSs are connected to a power supply voltage, the sources of the NMOSs are connected to a ground or a negative power supply, the gates of the PMOSs are connected to the drains of the PMOSs, the drains of the NMOSs, the gates of the NMOSs, the drains of the PMOSs, the drains of the NMOSs, the gates of the PMOSs, the gates of the NMOSs, and an output stage of the inverter circuit, and the gates of the NMOSs are connected to the drains of the PMOSs, the drains of the NMOSs, the gates of the PMOSs, the drains of the PMOSs, the drains of the NMOSs, the gates of the PMOSs, the gates of the NMOSs, and the output stage of the inverter circuit.

[0025] In some implementations of the first aspect, the circuit is disposed on a substrate, and the substrate adopts an anti-radiation reinforced layout structure including a ring gate and an independent well contact reinforced structure.

[0026] Compared with the prior art, the present application has the following advantages:

[0027] (1) The adjustable current mirror circuit and the adjustable resistance circuit provided by the present application can adjust the read window in the full load range through reasonable design.

[0028] (2) The present application uses a linear voltage stabilizing circuit to provide continuous and stable pre-charging to the bit line, and the load can be read in a large range, and a high read speed can still be ensured when the address is continuously switched.

[0029] (3) The present application adds a limiting diode in the linear voltage stabilizing circuit, so that when the storage unit is disturbed by a single particle, the bit line will not be overcharged to cause the storage unit to be written by mistake, and the read operation has high reliability.

[0030] (4) The double interlocking structure used by the present application makes the output signal of the sensitive amplifier have strong anti-single particle flip ability.

[0031] (5) The anti-radiation reinforced layout structure of the present application adopts a ring gate and an independent protection ring, which can better avoid the device source-drain leakage and latch problem caused by ionizing total dose and single particle radiation. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 The circuit structure schematic diagram of the present application is shown in the figure.

[0033] Figure 2 The anti-radiation reinforced layout structure schematic diagram of the present application is shown in the figure. DETAILED DESCRIPTION

[0034] The present application will be described in further detail below in combination with the drawings and specific embodiments.

[0035] AsFigure 1 As shown, the present application provides an anti-radiation reinforced RRAM sensitive amplifier circuit structure, which comprises a linear voltage stabilizing circuit 11, an adjustable current mirror circuit 12, an adjustable resistance circuit 13, a comparator circuit 14, an inverter circuit 15 and a latch circuit 16.

[0036] The linear voltage stabilizing circuit 11 stabilizes the bit line voltage of the storage unit (i.e. the load) at the read voltage V READ by negative feedback regulation, and generates a read current I CELL as the input of the adjustable current mirror circuit 12.

[0037] Specifically, the linear voltage stabilizing circuit 11 can include an operational transconductance amplifier 111, a power N-type metal oxide semiconductor (NMOS) 116, a zeroing resistor 114, a Miller capacitor 115, a grounding resistor 112 and a limiting diode 113. The positive input stage of the operational transconductance amplifier 111 is electrically connected to the read voltage V READ . The negative input stage of the operational transconductance amplifier 111 is electrically connected to the drain of the power NMOS 116 and the bit line of the storage unit (i.e. the load). The output stage of the operational transconductance amplifier 111 is electrically connected to the gate of the power NMOS 116. The source of the power NMOS 116 is electrically connected to the input stage of the adjustable current mirror circuit 12.

[0038] As shown in Figure 1 , the output stage of the operational transconductance amplifier 111, the gate of the power NMOS 116, the drain of the power NMOS 116 and the negative input stage of the operational transconductance amplifier 111 can constitute a feedback loop 117. The transconductance operational amplifier 111 differentiates the bit line voltage from the V READ voltage, amplifies the difference voltage, and outputs the result to the gate of the power NMOS 116. The power NMOS 116 provides an output voltage to the bit line of the storage unit under the control of the gate voltage, and feeds back this output voltage to the negative input end of the operational transconductance amplifier 111.

[0039] In some embodiments provided in the present application, a Miller capacitor 115 and a zeroing resistor 114 can be arranged between the gate control end and the drain output end of the power NMOS 116. One end of the zeroing resistor 114 can be connected to the output stage of the operational transconductance amplifier 111 (or the gate of the power NMOS 116), and the other end of the zeroing resistor 114 can be connected to the positive electrode of the Miller capacitor 115. The negative electrode of the Miller capacitor 115 can be connected to the negative input stage of the operational transconductance amplifier 111 (or the drain of the power NMOS 116). Adding the Miller capacitor 115 and the zeroing resistor 114 between the gate control end and the drain output end of the power NMOS 116 compensates the phase margin of the feedback loop 117 in the full load range, increases the load readable range, and effectively resists process fluctuations.

[0040] In some embodiments provided in the present application, the feedback loop 117 is grounded (or negative of the power supply) to establish a direct current path from the feedback loop 117 to the ground (or negative of the power supply) and provide an initial operating point for the feedback loop 117.

[0041] The feedback loop 117 can be connected with the ground (or negative of the power supply) through a grounding resistor 112, that is, the grounding resistor 112 is electrically connected between the reverse input stage of the operational transconductance amplifier 111 (or the drain of the power NMOS 116) and the ground (or negative of the power supply). The resistance of the grounding resistor 112 is much larger than the maximum resistance of the high resistance state of the storage unit, has little effect on the resistance reading of the storage unit itself, and controls the leakage current at the level of nanoamperes. When the storage unit is disturbed by a single particle, a conductive path is formed between the bit line and the ground (or negative of the power supply), and the voltage of the bit line is instantaneously lowered. At this time, the feedback loop 117 is dynamically adjusted, the voltage at the output end of the operational transconductance amplifier 111, that is, the gate end of the power NMOS 116, is raised, the current flowing through the power NMOS 116 is increased, and the bit line is charged to the voltage before the disturbance.

[0042] In some embodiments provided in the present application, to prevent the bit line voltage from being overcharged and causing a false write in the above process, a limiting diode 113 can be arranged between the feedback loop 117 and the ground (or negative of the power supply), and the limiting diode 113 can be connected in parallel with the grounding resistor 112. The anode of the limiting diode 113 can be connected with the reverse input stage of the operational transconductance amplifier 111 (or the drain of the power NMOS 116). The cathode of the limiting diode 113 can be connected with the ground (or negative of the power supply). In this way, the voltage of the bit line can be limited to not exceed the forward conduction voltage of the limiting diode 113, and the reliability of the read operation is improved. At the same time, the linear voltage stabilizing circuit 11 is used to provide a continuous and stable precharge to the bit line, and a high read speed can still be ensured when the address is continuously switched.

[0043] The adjustable current mirror circuit 12 is used to amplify the read current I CELL , and the output amplified current is m*I CELL by adjusting the multiple m of the mirror transistor 122 through a switch.

[0044] Specifically, the adjustable current mirror circuit 12 includes m+1 P-type metal oxide semiconductor (PMOS) transistors of the same size, the source of each PMOS transistor is connected with the power supply voltage VDD, the gate of the reference PMOS 121 and the gates of the m mirror PMOS 122 are connected, serving as the input stage of the adjustable current mirror circuit 12, and the drains of the m mirror PMOS 122 serve as the output stage of the adjustable current mirror circuit 12 and are connected with the anode of the adjustable resistance circuit 13 and the positive input stage of the comparator circuit 14.

[0045] The adjustable resistance circuit 13 includes n resistors RREF each of which has the same resistance, wherein the negative pole of the first resistor is connected to the ground or the negative pole of the power supply, and the positive pole of the nth resistor is connected to the output stage of the adjustable current mirror circuit 12 and the positive input stage of the comparator circuit 14.

[0046] The adjustable resistor circuit 13 is used to convert the current signal m*I CELL to a voltage signal by adjusting the multiple n of the series resistor R REF , and generating a voltage V AMP = mn*I CELL *R REF at the output end of the adjustable current mirror circuit 12 as the positive input of the comparator circuit 14.

[0047] By designing the values of m and n, mn*V READ / ((HRSmin+LRSmax) / 2)*R REF = V COM , the read window center value (HRSmin+LRSmax) / 2 can fluctuate within the full load range.

[0048] The comparator circuit 14 differentiates the positive input voltage V AMP and the reference voltage V COM , amplifies the difference voltage, and outputs the comparison result as the input of the inverter circuit 15.

[0049] The positive input stage of the comparator circuit 14 is connected to the output stage of the adjustable current mirror circuit 12 and the positive pole of the adjustable resistor circuit 13, the negative input stage is connected to the reference voltage V COM , and the output stage is connected to the input stage of the inverter circuit 15.

[0050] The inverter circuit 15 shapes the output voltage of the comparator circuit 14 into a digital voltage signal D through two-stage inverters 151, 152, and inputs it to the latch circuit 16.

[0051] The inverter circuit 15 includes two sequentially connected inverters 151, 152, wherein the input stage of the first inverter 151 is connected to the output stage of the comparator circuit 14, the output stage of the first inverter 151 is connected to the input stage of the second inverter 152, and the output stage of the second inverter 152 is connected to the input stage of the latch circuit 16.

[0052] The latch circuit 16 includes four identical PMOS transistors: PMOS161, PMOS163, PMOS165, and PMOS167, and four identical NMOS transistors: NMOS162, NMOS164, NMOS166, and NMOS168. The sources of PMOS161, PMOS163, PMOS165, and PMOS167 are connected to VDD, while the sources of NMOS162, NMOS164, NMOS166, and NMOS168 are connected to VSS. The gate of PMOS161 is connected to the drains of PMOS167, NMOS168, NMOS166, PMOS163, NMOS164, PMOS165, and NMOS162, and serves as the output of a sensitive amplifier. The gate of NMOS168 is connected to the drain of PMOS161, the drain of NMOS162, the gate of PMOS163, the drain of PMOS165, the drain of NMOS166, the gate of PMOS167, the gate of NMOS164, and the output stage of inverter circuit 15.

[0053] The latch circuit 16 latches the output signal D of the inverter circuit 15 and outputs a digital signal Q as the output of the sensitive amplifier. The latch circuit 16 adopts a double interlock structure. When a single-event flip occurs at the output node of any one of the inverters 161, 162 or 163, 164 or 165, 165 or 167, 168, the data stored in the other three inverters will not change. Since the flipped data cannot be latched, it will return to its original state after a period of time.

[0054] like Figure 2 As shown, this invention provides a substrate with a radiation-hardened layout structure 22. The radiation-hardened layout structure 22 includes a ring gate 221 and independent well contacts 222. The radiation-hardened layout structure 22 replaces the traditional straight gate 211 with a ring gate 221, isolating the source and drain of the device and eliminating source-drain leakage caused by total dose radiation, thus providing accurate read current and amplification current for current-mode sensitive amplifier circuits. Furthermore, well contacts 222 are added around each device, enhancing resistance to single-event disturbances and latch-up compared to a single guard ring structure 212.

[0055] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims of the present invention.

Claims

1. A resistive random access memory (RRAM) sensitive amplifier circuit, characterized in that, It includes a linear voltage regulator circuit (11), an adjustable current mirror circuit (12), an adjustable resistor circuit (13), a comparator circuit (14), an inverter circuit (15), and a latch circuit (16); The linear voltage regulator circuit (11) stabilizes the bit line voltage of the memory cell at the read voltage through negative feedback regulation, and generates a read current on the bit line as the input of the adjustable current mirror circuit (12). The adjustable current mirror circuit (12) is used to amplify the reading current and output the amplified current signal; The adjustable resistor circuit (13) is used to convert the amplified current signal into a voltage signal as the positive input of the comparator circuit (14); The comparator circuit (14) calculates the difference between the positive input voltage and the reference voltage, amplifies the difference voltage, and outputs the comparison result as the input of the inverter circuit (15). The inverter circuit (15) shapes the comparison result output by the comparator circuit (14) and uses it as the input of the latch circuit (16); The latch circuit (16) latches the output voltage of the inverter circuit (15) and outputs a digital signal as the output of the sensitive amplifier.

2. The circuit according to claim 1, characterized in that, The linear voltage regulator circuit (11) includes: an operational transconductance amplifier (111) and a power N-type metal-oxide-semiconductor NMOS (116); The positive input stage of the operational transconductance amplifier (111) is connected to a reference voltage. The negative input stage of the operational transconductance amplifier (111) is connected to the drain of the power NMOS (116) and the bit line of the memory cell. The output stage of the operational transconductance amplifier (111) is connected to the gate of the power NMOS (116). The source of the power NMOS (116) is connected to the input stage of the adjustable current mirror circuit (12). The negative input stage and output stage of the operational transconductance amplifier (111) together with the gate and drain of the power NMOS (116) form a feedback loop (117).

3. The circuit according to claim 2, characterized in that, The linear voltage regulator circuit (11) further includes a zero-adjustment resistor (114) and a Miller capacitor (115). The positive terminal of the zero-adjustment resistor (114) is connected to the output terminal of the operational transconductance amplifier (111), the negative terminal of the zero-adjustment resistor (114) is connected to the positive terminal of the Miller capacitor (115), and the negative terminal of the Miller capacitor (115) is connected to the inverting input stage of the operational transconductance amplifier (111).

4. The circuit according to claim 2 or 3, characterized in that, The feedback loop (117) is connected to ground or the negative terminal of the power supply VSS.

5. The circuit according to claim 4, characterized in that, The linear voltage regulator circuit (11) also includes a grounding resistor (112), which is electrically connected between the feedback loop (117) and VSS.

6. The circuit according to claim 4, characterized in that, The linear voltage regulator circuit (11) also includes a limiting diode (113), which is electrically connected between the feedback loop (117) and VSS.

7. The circuit according to claim 1, characterized in that, The adjustable current mirror circuit (12) includes m+1 P-type metal-oxide-semiconductor PMOS of the same size. The source of each PMOS is connected to ground or the negative terminal of the power supply. The m+1 PMOS of the same size includes a reference PMOS (121) and m mirror PMOS (122). The gate and drain of the reference PMOS (121) and the gate of the m mirror PMOS (122) are connected as the input stage of the adjustable current mirror circuit (12). The drain of the m mirror PMOS (122) serves as the output stage of the adjustable current mirror circuit (12) and is connected to the positive terminal of the adjustable resistor circuit (13) and the positive input stage of the comparator circuit (14).

8. The circuit according to claim 7, characterized in that, The adjustable resistor circuit (13) includes n resistors R connected in series. REF Each resistor has the same resistance value. The negative terminal of the first resistor is connected to VSS, and the positive terminal of the nth resistor is connected to the output stage of the adjustable current mirror circuit (12) and the positive input stage of the comparator circuit (14).

9. The circuit according to claim 8, characterized in that, mn*V READ / ((HRSmin+LRSmax) / 2)*R REF =V COM V COM V is the reference voltage. READ The reading voltage is HRSmin, the minimum high-resistivity state resistance is HRSmin, and the maximum low-resistivity state resistance is LRSmax.

10. The circuit according to claim 1, characterized in that, The positive input stage of the comparator circuit (14) is connected to the output stage of the adjustable current mirror circuit (12) and the positive terminal of the adjustable resistor circuit (13). The inverting input stage of the comparator circuit (14) is connected to the reference voltage. The output stage of the comparator circuit (14) is connected to the input stage of the inverter circuit (15).

11. The circuit according to claim 1, characterized in that, The inverter circuit (15) includes two inverters (151, 152) connected in sequence, wherein the input stage of the first inverter (151) is connected to the output stage of the comparator circuit (14), the output stage of the first inverter (151) is connected to the input stage of the second inverter (152), and the output stage of the second inverter (152) is connected to the input stage of the latch circuit (16).

12. The circuit according to claim 1, characterized in that, The latch circuit (16) includes four PMOS (161, 163, 165, 167) of the same size and four NMOS (162, 164, 166, 168) of the same size. The source of the PMOS (161, 163, 165, 167) is connected to the power supply voltage, and the source of the NMOS (162, 164, 166, 168) is grounded or connected to the negative terminal of the power supply. The gate of the PMOS (161) is connected to the drain of the PMOS (167), the drain of the NMOS (168), and the gate of the NMOS (166). The drain of PMOS (163), the drain of NMOS (164), the gate of PMOS (165), and the gate of NMOS (162) are connected and used as the output of a sensitive amplifier. The gate of NMOS (168) is connected to the drain of PMOS (161), the drain of NMOS (162), the gate of PMOS (163), the drain of PMOS (165), the drain of NMOS (166), the gate of PMOS (167), the gate of NMOS (164), and the output stage of the inverter circuit (15).

13. The circuit according to claim 1, characterized in that, The circuit is disposed on a substrate, which adopts a radiation-hardened layout structure (22). The radiation-hardened layout structure (22) includes an annular gate (221) and an independent well contact (222) hardening structure.

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