Apparatus and method for programming and verifying data in non-volatile memory devices

Abstract

The present disclosure relates to an operating method of a nonvolatile memory device, including: performing a fog operation of applying a first applied voltage to a word line and applying a first verification voltage to the word line at a level equal to or higher than a target threshold voltage; determining whether to completely perform the fog operation according to whether a number of memory cells each having a threshold voltage higher than the first verification voltage is equal to or greater than a first number; performing a fine operation of applying a second applied voltage to the word line and applying a second verification voltage at a level equal to the target threshold voltage; and determining whether to completely perform the fine operation according to whether a number of memory cells each having a threshold voltage lower than the second verification voltage is less than or equal to a second number.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0124804, filed on September 17, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a memory device, and more specifically, to an apparatus and method for programming and verifying data in a non-volatile memory device. Background Technology

[0004] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which the data stored is lost when power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which the data stored is retained even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly classified into NOR memory and NAND memory. Summary of the Invention

[0005] Various embodiments of this disclosure relate to devices that can store data in a non-volatile memory device through programming operations including two different types of application operations and two different types of verification operations.

[0006] According to an embodiment of the present invention, a non-volatile memory device may include: a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines; peripheral circuitry adapted to: perform a fuzzy operation, the fuzzy operation including a first application operation of applying a first applied voltage to a selected word line among the plurality of word lines and a first verification operation of applying a first verification voltage of a level equal to or higher than a target threshold voltage to the selected word line, and perform a fine operation, the fine operation including a second application operation of applying a second applied voltage to the selected word line and a second verification operation of applying a second verification voltage of a level equal to the target threshold voltage; and control logic circuitry adapted to: determine whether to fully perform the fuzzy operation as a result of the first verification operation based on whether the number of memory cells with respective threshold voltages higher than the first verification voltage is equal to or greater than a first predetermined number, and determine whether to fully perform the fine operation as a result of the second verification operation based on whether the number of memory cells with respective threshold voltages lower than the second verification voltage is less than or equal to a second predetermined number.

[0007] According to an embodiment of the present invention, an operation method for a non-volatile memory device may include: performing a fuzzing operation, the fuzzing operation including a first application operation of applying a first applied voltage to selected word lines among a plurality of word lines and a first verification operation of applying a first verification voltage with a level equal to or higher than a target threshold voltage to the selected word lines; performing the following first determination as a result of the first verification operation: determining whether to fully perform the fuzzing operation based on whether the number of memory cells with respective threshold voltages higher than the first verification voltage is equal to or greater than a first predetermined number; and performing a fine operation, the fine operation including a second application operation of applying a second applied voltage to the selected word lines and a second verification operation of applying a second verification voltage with a level equal to the target threshold voltage; and performing the following second determination as a result of the second verification operation: determining whether to fully perform the fine operation based on whether the number of memory cells with respective threshold voltages lower than the second verification voltage is less than or equal to a second predetermined number.

[0008] According to an embodiment of the present invention, an operation method for a non-volatile memory device comprising rows of cells includes: performing a fuzzing operation on the row; performing a fuzzing verification operation by applying a fuzzing verification voltage equal to or higher than a target threshold voltage to the row and applying a fuzzing sensing voltage to columns of individual cells to verify the fuzzing operation; performing a fine programming operation on the row when the fuzzing operation is successfully verified; and performing a fine verification operation by applying a fine verification voltage equal to the target threshold voltage to the row and applying a fine sensing voltage higher than the fuzzing sensing voltage to columns to verify the fine programming operation. The fuzzing operation can be verified as successful when the number of cells with respective threshold voltages higher than the fuzzing verification voltage is greater than a first threshold, and the fine programming operation can be verified as successful when the number of cells with respective threshold voltages lower than the fuzzing verification voltage is less than a second threshold.

[0009] The technical attributes available from this disclosure are not limited to those described herein, and those skilled in the art to which this disclosure pertains will understand other technical attributes not described herein through the following description. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the memory device shown.

[0012] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the storage block is shown.

[0013] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the memory device shown.

[0014] Figure 5 This is a diagram illustrating programming operations including fuzzy operations and fine operations according to embodiments of the present disclosure.

[0015] Figure 6A and Figure 6B This is a diagram illustrating the execution sequence of programming operations, including fuzzy operations and fine operations, according to embodiments of the present disclosure.

[0016] Figure 7 This is a diagram illustrating examples of programming operations including fuzzy and fine operations according to embodiments of the present disclosure.

[0017] Figure 8This is a diagram illustrating another example of programming operations including fuzzy and fine operations according to embodiments of the present disclosure.

[0018] Figure 9 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the page buffer is shown.

[0019] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 The diagram shows the operation of the page buffer. Detailed Implementation

[0020] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0021] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0022] In this disclosure, the terms “comprising,” “including,” “including,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. Terms in the claims do not exclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0023] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured to" perform one or more tasks. In such context, "configured to" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when a specified block / unit / circuit / component is not currently operational (e.g., not turned on or activated), it can be said that the block / unit / circuit / component is configured to perform a task. Blocks / units / circuits / components used with the language "configured to" include hardware, such as circuits, memory storing program instructions operable to perform the operation, etc. Furthermore, "configured to" may include general structures (e.g., general-purpose circuits) that are manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to perform a task to be solved. "Configured to" may also include means (e.g., integrated circuits) that adjust manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means for implementing or performing one or more tasks.

[0024] As used in this disclosure, the term "circuit" or "logic" means all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuitry only) and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors, or (ii) a portion of a processor / software (including digital signal processors, software, and memory that work together to enable a device such as a mobile phone or server to perform various functions), and (c) a circuitry requiring software or firmware for operation, such as a microprocessor or a portion thereof, even if the software or firmware does not actually exist. This definition of "circuit" or "logic" applies to all uses of the term in this application, including in any claim. As a further example, as used in this application, the term "circuit" or "logic" also covers implementations of only one processor (or multiple processors) or a portion thereof and its (or their) accompanying software and / or firmware. Where applicable to a particularly stated element, the term "circuit" or "logic" also covers integrated circuits of memory devices.

[0025] When used herein, the terms “first,” “second,” “third,” etc., serve as labels for nouns following the term and do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must be written before the second. Furthermore, although the terms can be used to identify various elements herein, these elements are not limited by these terms. These terms are used to distinguish one element from another that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0026] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on those factors or at least partially on those factors. For example, the phrase "A is determined based on B." Although B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0027] In this document, a data item, data entry, or data term can be a sequence of bits. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a series of bits. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a data packet transmitted between two different components.

[0028] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0029] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or operatively connected to the memory system 110.

[0030] The host 102 may include portable electronic devices such as mobile phones, MP3 players and laptops, as well as electronic devices such as desktop computers, game consoles, televisions (TVs), projectors and so on.

[0031] Host 102 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is coupled to memory system 110, and users of memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems depending on the mobility of host 102. General-purpose operating systems can be categorized as personal operating systems and enterprise operating systems based on system requirements or user environment. Personal operating systems, including Windows and Chrome, can be used to support general-purpose services. However, enterprise operating systems, including Windows servers, Linux, Unix, etc., can be specifically designed to achieve and support high performance. Furthermore, mobile operating systems can include Android, iOS, Windows Mobile, etc. Mobile operating systems can be used to support services or functions specific to mobility (e.g., power-saving features). Host 102 can include multiple operating systems. Host 102 can run multiple operating systems interlocked with memory system 110 and corresponding to user requests. Host 102 can transfer multiple commands corresponding to user requests to memory system 110, thereby performing operations corresponding to commands within memory system 110.

[0032] The memory system 110 operates in response to a request from the host 102, and specifically, stores data to be accessed by the host 102. The memory system 110 can be used as either a main memory device or an auxiliary memory device of the host 102. Depending on the host interface protocol coupled to the host 102, the memory system 110 can be implemented as any of a variety of storage devices. For example, the memory system 110 can be implemented as any of the following: a solid-state drive (SSD), a multimedia card (e.g., MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), and micro MMC), a secure digital card (e.g., SD, mini SD, and micro SD), a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash memory (CF) card, a smart media card, and a memory stick.

[0033] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102. The controller 130 may control the operation of storing data in the memory device 150.

[0034] The controller 130 and memory device 150 included in the memory system 110 can be integrated into a single semiconductor device, which can include any of the various types of memory systems discussed in the examples above.

[0035] By way of example and not limitation, controller 130 and memory device 150 can be implemented using an SSD. When memory system 110 is used as an SSD, the operating speed of host 102 connected to memory system 110 can be significantly higher than the operating speed of host 102 implemented using a hard disk. Additionally, controller 130 and memory device 150 can be integrated into a single semiconductor device to form memory cards such as: PC card (PCMCIA), compact flash (CF) card, memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC), secure digital (SD) cards (SD, mini SD, micro SD, SDHC), general-purpose flash memory, etc.

[0036] The memory system 110 can be configured as a component of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a memory device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0037] The memory device 150 may be a non-volatile memory device and can retain the data stored therein even when power is not supplied. The memory device 150 can store data provided by the host 102 through write operations and provide the stored data to the host 102 through read operations.

[0038] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, each page may be a unit for storing data in the memory device 150 or retrieving data stored in the memory device 150.

[0039] A memory block can be a unit for erasing data. In embodiments, the memory device 150 can take many alternative forms such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory Device, Resistive RAM (RRAM), Phase Change Random Access Memory RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, it will be described based on the memory device 150 being NAND Flash Memory.

[0040] Memory device 150 can receive commands and addresses from controller 130 and can access address-selected regions of the memory cell array. That is, memory device 150 can perform operations instructed by commands on address-selected regions. For example, memory device 150 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 150 can program data into the address-selected region. During a read operation, memory device 150 can read data from the address-selected region. During an erase operation, memory device 150 can erase data stored in the address-selected region.

[0041] The controller 130 controls all operations of the memory system 110.

[0042] When power is supplied to the memory system 110, the controller 130 may run firmware (FW). When the memory device 150 is a flash memory device, the controller 130 may run firmware such as a flash translation layer (FTL) to control communication between the host 102 and the memory device 150.

[0043] In this embodiment, the controller 130 can receive data and logical block addresses (LBAs) from the host 102, and can translate the logical block addresses into physical block addresses (PBAs) that indicate the addresses of memory cells included in the memory device 150 and where data is to be stored. In this specification, logical block addresses (LBAs) and logical addresses can be used interchangeably. Similarly, physical block addresses (PBAs) and physical addresses can be used interchangeably.

[0044] The controller 130 can control the memory device 150 to perform programming, reading, or erasing operations in response to requests received from the host 102. During a programming operation, the controller 130 can provide the memory device 150 with programming commands, physical block addresses, and data.

[0045] During a read operation, controller 130 may provide read commands and physical block addresses to memory device 150. During an erase operation, controller 130 may provide erase commands and physical block addresses to memory device 150.

[0046] In this embodiment, controller 130 may automatically generate commands, addresses, and data regardless of requests from host 102, and transmit these commands, addresses, and data to memory device 150. For example, controller 130 may provide commands, addresses, and data to memory device 150 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0047] In one embodiment, the controller 130 may control two or more memory devices 100. In this case, the controller 130 may control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme may be an operational mode in which the operating cycles of at least two memory devices 100 overlap with each other.

[0048] The host 102 can communicate with the memory system 110 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0049] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the memory device shown.

[0050] Reference Figure 2 The memory device 150 may include a memory cell array 151, peripheral circuitry 152, and control logic circuitry 153.

[0051] Memory cell array 151 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to address decoder 155 via row lines RL. The multiple memory blocks BLK1 to BLKz can be connected to page buffer group 156 via bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In an embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0052] A row line RL can include at least one source select line, multiple word lines, and at least one drain select line.

[0053] The memory cells included in the memory cell array 151 can be configured as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data.

[0054] Peripheral circuitry 152 can be configured to perform programming, reading, or erasing operations on selected regions in memory cell array 151. Peripheral circuitry 152 can drive memory cell array 151. For example, peripheral circuitry 152 can apply various operating voltages to or release applied voltages to row lines RL and bit lines BL1 to BLn.

[0055] The peripheral circuitry 152 may include a line decoder 155, a voltage generator 154, a page buffer group 156, an input / output circuit 157, and a sensing circuit 158.

[0056] The peripheral circuitry 152 can drive the memory cell array 151. For example, the peripheral circuitry 152 can drive the memory cell array 151 to perform programming operations, reading operations, and erasing operations.

[0057] Address decoder 155 can be connected to memory cell array 151 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines.

[0058] Address decoder 155 can be configured to operate in response to control of control logic circuitry 153. Address decoder 155 can receive address RADD from control logic circuitry 153.

[0059] Address decoder 155 can be configured to decode block addresses in a received address RADD. Address decoder 155 can select at least one memory block from BLK1 to BLKz based on the decoded block address. Address decoder 155 can be configured to decode row addresses in a received address RADD. Address decoder 155 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 155 can apply the operating voltage Vop supplied by voltage generator 154 to the selected word line.

[0060] During programming operations, address decoder 155 can apply a programming voltage to the selected word line and a pass voltage lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 155 can apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line.

[0061] During a read operation, the address decoder 155 can apply a read voltage to the selected word line and apply a read pass voltage higher than the read voltage to the unselected word line.

[0062] Erasing operations on memory device 150 can be performed on a block-by-block basis. The address ADDR input to memory device 150 during the erase operation includes the block address. Address decoder 155 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, address decoder 155 can apply a ground voltage to the word line of the selected memory block.

[0063] Voltage generator 154 can be configured to generate multiple operating voltages Vop using an external power supply voltage supplied to memory device 150. Voltage generator 154 can operate in response to control of control logic circuitry 153.

[0064] In this embodiment, voltage generator 154 can adjust an external power supply voltage and generate an internal power supply voltage. The internal power supply voltage generated by voltage generator 154 can be used as the operating voltage of memory device 150.

[0065] In this embodiment, voltage generator 154 can generate multiple operating voltages Vop using either an external or internal power supply voltage. Voltage generator 154 can be configured to generate various voltages required by the memory device 150. For example, voltage generator 154 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0066] Voltage generator 154 may include a plurality of pump capacitors that receive an internal power supply voltage to generate a plurality of operating voltages having various voltage levels, and in response to control of control logic circuit 153, generate a plurality of operating voltages by selectively activating the plurality of pump capacitors.

[0067] The generated operating voltage Vop can be supplied to the memory cell array 151 through the address decoder 155.

[0068] Page buffer group 156 may include multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm may be connected to memory cell array 151 via bit lines BL1 to BLm respectively. The multiple page buffers PB1 to PBm may operate in response to the control of control logic circuitry 153.

[0069] Multiple page buffers PB1 to PBm can communicate data DATA with data input / output circuit 157. During programming operations, multiple page buffers PB1 to PBm can receive the data DATA to be stored through data input / output circuit 157 and data line DL.

[0070] During programming operations, when a programming voltage is applied to the selected word line, multiple page buffers PB1 to PBm can transfer data DATA received via data input / output circuit 157 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page can be programmed based on the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an elevated threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, multiple page buffers PB1 to PBm read data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0071] During a read operation, page buffer group 156 can read data DATA from the memory cell of the selected page via bit line BL and store the read data DATA in multiple page buffers PB1 to PBm.

[0072] During the erase operation, page buffer group 156 can float the bit line BL. In an embodiment, page buffer group 156 may include column select circuitry.

[0073] The data input / output circuit 157 can be connected to multiple page buffers PB1 to PBm via data lines DL. The data input / output circuit 157 can operate in response to the control logic circuit 153.

[0074] Data input / output circuitry 157 may include multiple input / output buffers (not shown) for receiving data DATA input thereto. During programming operation, data input / output circuitry 157 may be able to receive data DATA from controller 130 (see reference 130). Figure 1 The data input / output circuit 157 receives the data to be stored. During a read operation, the data DATA transferred from the multiple page buffers PB1 to PBm included in the page buffer group 156 can be output to the controller 130 (see reference). Figure 1 ).

[0075] During a read or verification operation, the sensing circuit 158 ​​may generate a reference current in response to the enable bit VRYBIT generated by the control logic circuit 153, and output a PASS or FAIL signal to the control logic circuit 153 by comparing the sensed voltage VPB received from the page buffer group 156 with the reference voltage generated by the reference current.

[0076] Control logic circuitry 153 can be connected to address decoder 155, voltage generator 154, page buffer group 156, data input / output circuitry 157, and sensing circuitry 158. Control logic circuitry 153 can be configured to control all operations of memory device 150. Control logic circuitry 153 can operate in response to commands (CMD) transmitted from external devices.

[0077] Control logic circuit 153 can generate various signals in response to command CMD and address ADDR, and control other components 154 to 158 included in peripheral circuit 152. For example, control logic circuit 153 can generate operation signal OPSIG, address RADD, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic circuit 153 can output operation signal OPSIG to voltage generator 154, address RADD to address decoder 155, read and write control signal PBSIGNALS to page buffer group 156, and enable bit VRYBIT to sensing circuit 158. In addition, control logic circuit 153 can determine whether the verification operation is successful or unsuccessful in response to pass signal PASS or failure signal FAIL output by sensing circuit 158.

[0078] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the storage block is shown.

[0079] Reference Figure 3Multiple word lines arranged in parallel can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple memory cell strings ST connected between bit lines BL1 to BLn and a common source line (CSL). Bit lines BL1 to BLm can be connected to memory cell strings ST individually, and the common source line (CSL) can be connected together to memory cell strings ST. Since memory cell strings ST can have the same configuration, the memory cell string ST connected to the first bit line BL1 is described in detail representatively.

[0080] A memory cell string ST may include a source selection transistor SST connected in series between a common source line CSL and a first bit line BL1, multiple memory cells MC1 to MC16, and a drain selection transistor DST. A memory cell string ST may include at least one drain selection transistor DST, and may include more source selection transistors SST and memory cells MC1 to MC16 than shown in the figure.

[0081] The source of the source select transistor SST can be connected to the common source line CSL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory cell strings ST can be connected to the source select line SSL, the gates of the drain select transistors DST included in different memory cell strings ST can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells in different memory cell strings ST that are connected to the same word lines can be called physical pages PG. Therefore, the memory block BLKi can include the same number of physical pages PG as word lines WL1 to WL16.

[0082] A memory cell can store 1 bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0083] A memory cell can store two or more bits of data. In this case, a physical page (PPG) can store two or more logical pages (LPGs) of data.

[0084] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2A detailed diagram of the memory device 150 shown.

[0085] Figure 5 This is a diagram illustrating programming operations including fuzzy operations and fine operations according to embodiments of the present disclosure.

[0086] Figure 6A and Figure 6B This is a diagram illustrating the execution sequence of programming operations, including fuzzy operations and fine operations, according to embodiments of the present disclosure.

[0087] Reference Figure 4 The memory device 150 may include a memory cell array 151, a programming and verification circuit 41, a voltage generator 154, and a programming operation control unit 43.

[0088] Reference Figure 2 The described peripheral circuitry 152 may include programming and verification circuitry 41 and voltage generator 154. Programming and verification circuitry 41 may include... Figure 2 The address decoder 155, sensing circuit 158, page buffer group 156, and data input / output circuit 157 are shown. (See reference...) Figure 2 The control logic circuit 153 described may include a programmable operation control unit 43. That is, the operation of the programming and verification circuit 41, which will be described below, can be the operation of the peripheral circuit 152, and the operation of the programmable operation control unit 43 can be the operation of the control logic circuit 153.

[0089] The memory cell array 151 may include multiple memory cells. The memory cell array 151 can be connected to the programming and verification circuit 41 via multiple word lines WL connected to the multiple memory cells. The memory cell array 151 can be connected to the programming and verification circuit 41 via multiple bit lines BL connected to the multiple memory cells. The multiple word lines WL and the multiple bit lines BL can be as follows: Figure 3 Cross-connection as described in [the text].

[0090] Voltage generator 154 can generate the operating voltage Vop required for operation of the memory cell in response to the voltage generation signal V_Gen. In the operating voltage Vop, the voltage applied to the word line can be the word line voltage. Voltage generator 154 can provide the generated operating voltage Vop to the programming and verification circuit 41.

[0091] The programming and verification circuit 41 can receive an operating voltage Vop from the voltage generator 154. The programming and verification circuit 41 can perform programming operations including fuzzy and fine operations, such that a plurality of memory cells included in a word line selected as a programming target among a plurality of word lines WL have a predetermined target threshold voltage. The fuzzy operation may include a first application operation and a first verification operation, and the fine operation may include a second application operation and a second verification operation. During the first verification operation included in the fuzzy operation, the programming and verification circuit 41 may apply a first verification voltage with a level equal to or higher than the target threshold voltage used for the programming operation to the word line selected as the programming target. During the second verification operation included in the fine operation, the programming and verification circuit 41 may apply a second verification voltage with a level equal to the target threshold voltage used for the programming operation to the word line selected as the programming target.

[0092] The programming operation control unit 43 can determine whether the fuzzing operation has been fully performed during the first verification operation included in the fuzzing operation, based on whether the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is higher than the first verification voltage is equal to or greater than a first predetermined number. The programming operation control unit 43 can determine whether the fine operation has been fully performed during the second verification operation included in the fine operation, based on whether the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is lower than the second verification voltage is less than or equal to a second predetermined number.

[0093] During the first verification operation included in the fuzzing operation, the programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the fuzzing operation until the fuzzing operation is fully executed. That is, when it is confirmed that the number of memory cells whose respective threshold voltages are higher than the first verification voltage among the multiple memory cells included in the word line selected as the programming target during the first verification operation included in the fuzzing operation is less than a first predetermined number, the programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the first application operation and the first verification operation included in the fuzzing operation.

[0094] When it is determined during the first verification operation included in the fuzzing operation that the fuzzing operation has been fully performed, the programming operation control unit 43 can control the programming and verification circuit 41 to begin performing the fine operation. That is, when it is confirmed that the number of memory cells whose respective threshold voltages are higher than the first verification voltage among the multiple memory cells included in the word line selected as the programming target during the first verification operation included in the fuzzing operation is equal to or greater than a first predetermined number, the programming operation control unit 43 can control the programming and verification circuit 41 to perform the second application operation and the second verification operation included in the fine operation.

[0095] During the second verification operation included in the fine-grained operation, the programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the fine-grained operation until the fine-grained operation is fully executed. That is, when it is confirmed that the number of memory cells whose respective threshold voltages are lower than the second verification voltage among the multiple memory cells included in the word line selected as the programming target during the second verification operation included in the fine-grained operation is greater than a second predetermined number, the programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the second application operation and the second verification operation included in the fine-grained operation.

[0096] When it is determined that the fine-grained operation has been fully performed during the second verification operation included in the fine-grained operation, the programming operation control unit 43 can control the programming and verification circuit 41 to terminate the programming operation. That is, when it is confirmed that the number of memory cells whose respective threshold voltages are lower than the second verification voltage among the multiple memory cells included in the word line selected as the programming target during the second verification operation included in the fine-grained operation is less than or equal to a second predetermined number, the programming operation control unit 43 can determine that the multiple memory cells have the target threshold voltage and control the programming and verification circuit 41 to terminate the programming operation.

[0097] The fuzzy and fine operations on a word line selected as a programming target can be discontinuous. According to an embodiment, a fuzzy operation can be performed on any word line selected as a programming target, and a fuzzy operation can be performed on another word line selected as a programming target before performing a fine operation on that word line. Performing a fuzzy operation on any word line selected as a programming target, and then performing a fuzzy operation on another word line selected as a programming target before continuing to perform a fine operation on that word line, is done to reduce interference between word lines and improve cell distribution.

[0098] The programming operation control unit 43 can control the programming and verification circuit 41 to apply a second sensing voltage to multiple bit lines BL during a second verification operation included in a fine operation, and to apply a first sensing voltage lower than the second sensing voltage to multiple bit lines BL during a first verification operation included in a fuzzy operation.

[0099] Typically, the application operation included in a programming operation can be an operation that raises the threshold voltage of a memory cell to a target threshold voltage corresponding to the target programming state of the programming operation, based on the data to be stored in the memory cell.

[0100] Furthermore, the verification operation included in the programming operation can typically be an operation to verify whether the programming operation on the memory cell was performed correctly. In other words, the verification operation can be an operation to check whether the threshold voltage of the memory cell that has undergone the programming operation has reached the target threshold voltage corresponding to the target programming state of the programming operation.

[0101] The programming operations according to the embodiments may include two types of application operations. That is, the programming operations according to the embodiments may include a first application operation included in fuzzy operations and a second application operation included in fine operations.

[0102] Reference Figure 4 and Figure 5 The programming and verification circuit 41 can perform a first application operation FOGGY PROGRAM, which is included in the fuzzing operation, on a plurality of memory cells included in the word line selected as the programming target, thereby increasing the threshold voltage Vth level of the memory cell that is in the erasure state, so that the memory cell can have the threshold voltage Vth level in the fuzzy state.

[0103] The programming and verification circuit 41 can perform a second application operation, FINE PROGRAM, on a plurality of memory cells included in the word lines selected as programming targets and having a threshold voltage Vth level in the fuzzy state after the fuzzy operation has been fully performed. Therefore, the programming and verification circuit 41 can increase the threshold voltage Vth level of the memory cells in the fuzzy state, so that the memory cells can have a threshold voltage Vth level in the fine state.

[0104] The programming operations according to the embodiments may include two types of verification operations. That is, the programming operations according to the embodiments may include a first verification operation included in fuzzy operations and a second verification operation included in fine operations.

[0105] Reference Figure 4 and Figure 5The programming and verification circuit 41 can perform a first application operation FOGGY PROGRAM, which is part of a fuzzing operation, on a plurality of memory cells included in a word line selected as the programming target. Then, it performs a first verification operation to verify whether the first application programming operation FOGGY PROGRAM has been correctly executed. When the first application operation FOGGY PROGRAM has been correctly executed, the plurality of memory cells included in the word line selected as the programming target may have a threshold voltage Vth level in a fuzzy state. Therefore, the programming operation control unit 43 can check, during the first verification operation, via the programming and verification circuit 41 whether the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is higher than the first verification voltage VFO is equal to or greater than a first predetermined number, and can verify whether the first application operation FOGGY PROGRAM has been correctly executed based on the check result. When the number of memory cells among the plurality of memory cells among the word line selected as the programming target whose respective threshold voltage is higher than the first verification voltage VFO is less than the first predetermined number during the first verification operation, the programming operation control unit 43 can determine that the first application operation FOGGY PROGRAM has not been correctly executed. When the number of memory cells whose respective threshold voltages are higher than the first verification voltage VFO among the multiple memory cells included in the word line selected as the programming target during the first verification operation is equal to or greater than a first predetermined number, the programming operation control unit 43 can determine that the first application operation FOGGYPROGRAM has been correctly executed, thereby determining that the fuzzing operation has been fully performed. The first predetermined number can be a natural number greater than 1. The first verification voltage VFO can have a level equal to or higher than the target threshold voltage corresponding to the target programming state of the multiple memory cells included in the word line selected as the programming target.

[0106] The programming and verification circuit 41 can perform a second application operation (FINE PROGRAM) within a fine-grained operation on a plurality of memory cells included in a word line selected as the programming target, and then perform a second verification operation to verify whether the second application programming operation (FINE PROGRAM) has been correctly executed. When the second application programming operation (FINE PROGRAM) has been correctly executed, the plurality of memory cells included in the word line selected as the programming target can have a threshold voltage Vth level in a fine state. Therefore, the programming operation control unit 43 can check, during the second verification operation, via the programming and verification circuit 41 whether the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is higher than the second verification voltage VFI is less than or equal to a second predetermined number, and can verify whether the second application operation (FINE PROGRAM) has been correctly executed based on the check result. When, during the second verification operation, the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is lower than the second verification voltage VFI is greater than the second predetermined number, the programming operation control unit 43 can determine that the second application operation (FINE PROGRAM) has not been correctly executed. When the number of memory cells whose threshold voltages are lower than the second verification voltage VFI among the multiple memory cells included in the word line selected as the programming target during the second verification operation is less than or equal to a second predetermined number, the programming operation control unit 43 can determine that the second application operation FINE PROGRAM has been correctly executed, thereby determining that the fine operation has been fully executed, that is, the programming operation has been fully executed. The second predetermined number can be a natural number greater than 1. The first predetermined number and the second predetermined number can be the same as or different from each other. That is, the first predetermined number and the second predetermined number can be determined separately and can be unrelated to each other. The second verification voltage VFI can have a level equal to the target threshold voltage corresponding to the target programming state of the multiple memory cells included in the word line selected as the programming target.

[0107] Typically, incremental step pulse programming (ISPP) can be used to repeatedly execute the application and verification operations included in the programming operation. That is, the application and verification operations included in the programming operation can be repeatedly executed until the multiple memory cells included in the word line selected as the programming target have a target threshold voltage corresponding to the target programming state.

[0108] In the programming operation according to the embodiment, fuzzy operations and fine operations can be repeatedly executed until each of the operations is fully executed. That is, a fuzzy operation can begin at the entry time of the programming operation and be repeatedly executed during a first verification operation included in the fuzzy operation until the fuzzy operation is fully executed, and a fine operation can begin in response to the full execution of the fuzzy operation. A fine operation can be repeatedly executed during a second verification operation included in the fine operation until the fine operation is fully executed, and the programming operation can terminate in response to the full execution of the fine operation.

[0109] Reference Figure 4 , Figure 5 and Figure 6A The programming operation control unit 43 can control the programming and verification circuit 41 to perform a fuzzy operation FOGGY on a plurality of memory cells included in the word line selected as the programming target. The programming operation control unit 43 can control the programming and verification circuit 41 to perform a first application operation FOGGY PROGRAM and a first verification operation FOGGY VERIFY. The programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the fuzzy operation FOGGY until it is determined that the fuzzy operation FOGGY has been fully executed during the first verification operation FOGGY VERIFY.

[0110] Reference Figure 4 , Figure 5 and Figure 6B The programming operation control unit 43 can control the programming and verification circuit 41 to perform a fine operation (FINE) on the plurality of memory cells included in the word line selected as the programming target after the fuzzy operation (FOGGY) has been fully executed. The programming operation control unit 43 can also control the programming and verification circuit 41 to perform a second application operation (FINE PROGRAM) and a second verification operation (FINE VERIFY). The programming operation control unit 43 can control the programming and verification circuit 41 to repeatedly execute the fine operation (FINE) until it is determined that the fine operation (FINE) has been fully executed during the second verification operation (FINE VERIFY).

[0111] like Figure 6A and Figure 6B The diagrams show that fuzzy operations (FOGGY) and fine operations (FINE) can be performed discontinuously on multiple memory cells included in a word line selected as the programming target. In other words, it is possible to... Figure 6A The illustrated method performs a fuzzy operation FOGGY on multiple memory cells included in the word line selected as the first application target, and can also be performed in the same way. Figure 6A The illustrated method performs a fuzzy operation (FOGGY) on multiple memory cells included in the word line selected as the second application target. Subsequently, it can be... Figure 6BThe fine-grained operation FINE is performed on multiple memory cells included in the word line selected as the first application target, as shown, and can also be performed in the same way. Figure 6B The method shown performs a fine operation FINE on multiple memory cells included in the word line selected as the second application target.

[0112] More specifically, refer to Figure 4 , Figure 5 and Figure 6A The programming operation control unit 43 can control the programming and verification circuit 41 to perform the first fuzzy operation FOGGY1, including the first application operation FOGGY PROGRAM and the first verification operation FOGGY VERIFY, on the multiple memory cells included in the word line selected as the programming target at the entry time of the programming operation.

[0113] Specifically, the programming operation control unit 43 can control the programming and verification circuit 41 to apply a first fuzzy programming voltage VFPM1 to the word line selected as the programming target during the first application operation FOGGY PROGRAM included in the first fuzzy operation FOGGY1, and increase the threshold voltage level of the plurality of memory cells included in the word line selected as the programming target. Subsequently, the programming operation control unit 43 can control the programming and verification circuit 41 to apply a first verification voltage VFO to the word line selected as the programming target during the first verification operation FOGGY VERIFY included in the first fuzzy operation FOGGY1, and confirm that the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is higher than the first verification voltage VFO is less than a first predetermined number. Therefore, the programming operation control unit 43 can control the programming and verification circuit 41 to start executing the second fuzzy operation FOGGY2.

[0114] The programming operation control unit 43 can control the programming and verification circuit 41 to apply a second fuzzy programming voltage VFPM2 to the word line selected as the programming target during the first application operation FOGGY PROGRAM included in the second fuzzy operation FOGGY2, and raise the threshold voltage level of the plurality of memory cells included in the word line selected as the programming target. Subsequently, the programming operation control unit 43 can control the programming and verification circuit 41 to apply a first verification voltage VFO to the word line selected as the programming target during the first verification operation FOGGY VERIFY included in the second fuzzy operation FOGGY2, and confirm that the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is higher than the first verification voltage VFO is equal to or greater than a first predetermined number. Therefore, the programming operation control unit 43 can control the programming and verification circuit 41 to no longer execute the fuzzy operation FOGGY.

[0115] For reference, the first fuzzy programming voltage VFPM1 and the second fuzzy programming voltage VFPM2 used in the first application operation FOGGYPROGRAM of the first fuzzy operation FOGGY1 and the second fuzzy operation FOGGY2 can have the same level as shown in the figure. Unlike what is shown in the figure, the levels of the first fuzzy programming voltage VFPM1 and the second fuzzy programming voltage VFPM2 can be different from each other.

[0116] Reference Figure 4 , Figure 5 and Figure 6B The programming operation control unit 43 can control the programming and verification circuit 41 to apply the first fine programming voltage VFIM1 generated by the voltage generator 154 to the word line selected as the programming target during the second application operation FINE PROGRAM included in the first fine operation FINE1, and raise the threshold voltage level of the plurality of memory cells included in the word line selected as the programming target. Subsequently, the programming operation control unit 43 can control the programming and verification circuit 41 to apply the second verification voltage VFI to the word line selected as the programming target during the second verification operation FINE VERIFY included in the first fine operation FINE1, and confirm that the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is lower than the second verification voltage VFI is greater than a second predetermined number. Therefore, the programming operation control unit 43 can control the programming and verification circuit 41 to start executing the second fine operation FINE2.

[0117] The programming operation control unit 43 can control the programming and verification circuit 41 to apply the second fine programming voltage VFIM2 generated by the voltage generator 154 to the word line selected as the programming target during the second application operation FINE PROGRAM included in the second fine operation FINE2, and raise the threshold voltage level of the plurality of memory cells included in the word line selected as the programming target. Subsequently, the programming operation control unit 43 can control the programming and verification circuit 41 to apply the second verification voltage VFI to the word line selected as the programming target during the second verification operation FINE VERIFY included in the second fine operation FINE2, and confirm that the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is lower than the second verification voltage VFI is greater than a second predetermined number. Therefore, the programming operation control unit 43 can control the programming and verification circuit 41 to start executing the third fine operation FINE3.

[0118] The programming operation control unit 43 can control the programming and verification circuit 41 to apply the third fine programming voltage VFIM3 generated by the voltage generator 154 to the word line selected as the programming target during the second application operation FINE PROGRAM included in the third fine operation FINE3, and raise the threshold voltage level of the plurality of memory cells included in the word line selected as the programming target. Subsequently, the programming operation control unit 43 can control the programming and verification circuit 41 to apply the second verification voltage VFI to the word line selected as the programming target during the second verification operation FINE VERIFY included in the third fine operation FINE3, and confirm that the number of memory cells among the plurality of memory cells included in the word line selected as the programming target whose respective threshold voltage is lower than the second verification voltage VFI is less than or equal to a second predetermined number. Therefore, the programming operation control unit 43 can control the programming and verification circuit 41 to terminate the programming operation without further performing the fine operation FINE. Each time a fine-tuning operation is repeatedly performed according to the ISPP method illustrated, the levels of the first to third fine-tuning voltages VFIM1, VFIM2, and VFIM3 used in the second application operation FINE PROGRAM of the first to third fine-tuning operations FINE1, FINE2, and FINE3 are increased. For ease of description, Figure 6A The programming operations shown include two fuzzy operations, FOGGY1 and FOGGY2. Figure 6B The programming operations shown include three fine operations, FINE1, FINE2, and FINE3, but these are merely examples, and actual operations may be implemented in different ways.

[0119] Typically, when performing a verification operation included in a programming operation, a power supply voltage or a ground voltage can be applied to each of the multiple bit lines that intersect with the word line selected as the programming target. For example, when performing a verification operation included in a programming operation, a power supply voltage can be applied to the bit line selected as the verification target, but a ground voltage can be applied to the unselected bit lines.

[0120] In the programming operation according to the embodiment, the voltage level applied to the bit line selected as the verification target in the first verification operation included in the fuzzy operation can be set to be different from the voltage level applied to the bit line selected as the verification target in the second verification operation included in the fine operation. Specifically, the voltage level applied to the bit line selected as the verification target in the second verification operation included in the fine operation can be set to be higher than the voltage level applied to the bit line selected as the verification target in the first verification operation included in the fuzzy operation. For example, a power supply voltage can be applied to the bit line selected as the verification target in the second verification operation included in the fine operation, while a voltage lower than the power supply voltage can be applied to the bit line selected as the verification target in the first verification operation included in the fuzzy operation.

[0121] Figure 7 This is a diagram illustrating examples of programming operations including fuzzy and fine operations according to embodiments of the present disclosure.

[0122] Figure 8 This is a diagram illustrating another example of programming operations including fuzzy and fine operations according to embodiments of the present disclosure.

[0123] Reference Figures 4 to 8 When performing the first application operation FOGGY PROGRAM (included in the fuzzy operation FOGGY) and the second application operation FINE PROGRAM (included in the fine operation FINE) on multiple memory cells included in a word line selected as the programming target, it can be seen how the threshold voltage distribution changes.

[0124] exist Figure 7 and Figure 8 In this context, each of the multiple memory cells is a three-level cell (TLC) capable of storing 3 bits of data. Therefore, when the programming operations are fully performed on the multiple memory cells included in the word line selected as the programming target, that is, when the first application operation FOGGY PROGRAM and the first verification operation FOGGY VERIFY included in the FOGGY operation and the second application operation FINE PROGRAM and the second verification operation FINE VERIFY included in the fine operation, the multiple memory cells can have a total of eight types of programming states E, P1, P2, P3, P4, P5, P6, and P7.

[0125] Reference Figures 4 to 7When multiple memory cells included in the word line selected as the programming target are all in erase state E, the programming operation can begin, and the first application operation FOGGY PROGRAM and the first verification operation FOGGY VERIFY included in the FOGGY operation can be executed at least once. In this case, three first verification voltages VFO1, VFO2, and VFO3 can be used in the first verification operation FOGGY VERIFY to determine whether the fuzzing operation FOGGY has been fully executed. Therefore, when the fuzzing operation FOGGY is fully executed, the multiple memory cells can have a total of four types of programming states E, PP1, PP2, and PP3.

[0126] Thus, after multiple memory cells included in the word line selected as the programming target have four programming states E, PP1, PP2, and PP3 through the fuzzy operation FOGGY, the second application operation FINEPROGRAM and the second verification operation FINEVERIFY included in the fine operation FINE can be executed at least once. In this case, seven second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 can be used in the second verification operation FINEVERIFY to determine whether the fine operation FINE has been fully executed.

[0127] As mentioned above, in Figure 7 In the fuzzy operation FOGGY, the number of first verification voltages VFO1, VFO2, and VFO3 used in the first verification operation FOGGY VERIFY can be set to be different from the number of second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 used in the second verification operation FINE VERIFY included in the fine operation FINE. In this paper, the seven second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 can have the same level as the seven target threshold voltages used to classify the eight types of programming states E, P1, P2, P3, P4, P5, P6, and P7. The three first verification voltages VFO1, VFO2, and VFO3 can have levels equal to or higher than three of the seven target threshold voltages used to classify the eight types of programming states E, P1, P2, P3, P4, P5, P6, and P7. Figure 7 It can be seen that the first verification voltage VFO1 has a level higher than the second target threshold voltage, the second verification voltage VFO2 has a level higher than the fourth target threshold voltage, and the third verification voltage VFO3 has a level higher than the sixth target threshold voltage.

[0128] Reference Figures 4 to 6B and Figure 8 When multiple memory cells included in the word line selected as the programming target are all in erase state E, the programming operation can begin, and the first application operation FOGGY PROGRAM and the first verification operation FOGGY VERIFY included in the FOGGY operation can be executed at least once. In this case, seven first verification voltages VFO1, VFO2, VFO3, ​​VFO4, VFO5, VFO6, and VFO7 can be used in the first verification operation FOGGY VERIFY to determine whether the fuzzing operation FOGGY has been fully executed. Therefore, in the state where the fuzzing operation FOGGY has been fully executed, the multiple memory cells can have a total of eight types of programming states E, PP1, PP2, PP3, PP4, PP5, PP6, and PP7.

[0129] Thus, after the multiple memory cells included in the word line selected as the programming target have eight programming states E, PP1, PP2, PP3, PP4, PP5, PP6, and PP7 through the fuzzy operation FOGGY, the second application operation FINE PROGRAM and the second verification operation FINE VERIFY included in the fine operation FINE can be executed at least once. In this case, seven second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 can be used in the second verification operation FINE VERIFY to determine whether the fine operation FINE has been fully executed.

[0130] As mentioned above, in Figure 8 In the fuzzy operation FOGGY, the number of first verification voltages VFO1, VFO2, VFO3, ​​VFO4, VFO5, VFO6, and VFO7 used in the first verification operation FOGGY VERIFY can be set to be the same as the number of second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 used in the second verification operation FINE VERIFY included in the fine operation FINE. In this document, the seven second verification voltages VFI1, VFI2, VFI3, VFI4, VFI5, VFI6, and VFI7 can have levels equal to the seven target threshold voltages used to classify the eight types of programming states E, P1, P2, P3, P4, P5, P6, and P7. The seven first verification voltages VFO1, VFO2, VFO3, ​​VFO4, VFO5, VFO6, and VFO7 can have levels equal to or higher than the seven target threshold voltages used to classify the eight types of programming states E, P1, P2, P3, P4, P5, P6, and P7.

[0131] Figure 9 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram of the page buffer is shown.

[0132] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 The diagram shows the operation of the page buffer.

[0133] Reference Figure 9 It can be seen that it has been made public. Figure 2 The detailed configuration of each PBx among the multiple page buffers PB1 to PBm included in the page buffer group 156 shown is as follows. (See also...) Figure 2 The multiple memory cells can be connected to the multiple page buffers PB1 to PBm included in the page buffer group 156 included in the peripheral circuit 152 via multiple bit lines BL1 to BLm respectively.

[0134] Specifically, each of the multiple page buffers PB1 to PBm according to the embodiment can be connected between any one of the multiple bit lines BL1 to BLm and the sensing node SO. Each of the multiple page buffers PB1 to PBm can include a latch 90, a first connection control unit 91, a second connection control unit 92, a third connection control unit 93, and a fourth connection control unit 94.

[0135] The logic level stored in latch 90 can be determined based on whether verification of each of the multiple bit lines BL1 to BLm is permitted. According to an embodiment, since... Figure 9 Only node QS of latch 90 is shown, and the scenario where verification is permitted is described; therefore, node QS of latch 90 has a level of ground voltage VSS. When verification is not permitted, node QS of latch 90 may have a level of supply voltage VCORE.

[0136] The first connection control unit 91 can electrically connect the sensing nodes SO and CSO to the power supply voltage VCORE terminal in response to the logic level stored in the latch 90 and the first control signals SA_PRECH_N and SA_SENSE.

[0137] The second connection control unit 92 can respond to the second control signals PB_SENSE and SA_CSOC by electrically connecting the bit line BL to the sensing nodes SO and CSO.

[0138] The third connection control unit 93 can electrically connect the sensing nodes SO and CSO to the ground voltage VSS terminal in response to the logic level stored in the latch 90 and the third control signal SA_DISCH.

[0139] The fourth connection control unit 94 can respond to the fourth control signal BLDIS by electrically connecting the bit line BL to the ground voltage VSS terminal.

[0140] The programming operation control unit 43 can generate the first control signal SA_PRECH_N and SA_SENSE, the second control signal PB_SENSE and SA_CSOC, the third control signal SA_DISCH and the fourth control signal BLDIS, and transmit the generated signals to the programming and verification circuit 41.

[0141] Reference Figures 2 to 5 , Figure 9 and Figure 10 The programming operation control unit 43 can control the programming and verification circuit 41 to correctly adjust the activation time and level of the first control signals SA_PRECH_N and SA_SENSE, the second control signals PB_SENSE and SA_CSOC, the third control signal SA_DISCH and the fourth control signal BLDIS, and set the level of the voltage applied to the bit line BL selected as the verification target during the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY to be different from the level of the voltage applied to the bit line BL selected as the verification target during the second verification operation FINE VERIFY included in the fine operation FINE. For example, the programming operation control unit 43 can correctly adjust the activation time and level of the first control signals SA_PRECH_N and SA_SENSE, the second control signals PB_SENSE and SA_CSOC, the third control signal SA_DISCH and the fourth control signal BLDIS, and set the level of the voltage applied to the bit line BL selected as the verification target during the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY to be lower than the level of the voltage applied to the bit line BL selected as the verification target during the second verification operation FINE VERIFY included in the fine operation FINE.

[0142] Specifically, during each of the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY and the second verification operation FINE VERIFY included in the fine operation FINE, the programming operation control unit 43 can activate the first control signals SA_PRECH_N and SA_SENSE with a logic high level, and electrically connect the sensing nodes SO and CSO to the power supply voltage VCORE terminal through the first connection control unit 91, thereby applying the power supply voltage VCORE to the sensing nodes SO and CSO. During each of the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY and the second verification operation FINE VERIFY included in the fine operation FINE, the programming operation control unit 43 can deactivate the third control signal SA_DISCH with a logic low level and not electrically connect the sensing nodes SO and CSO to the ground voltage VSS terminal through the third connection control unit 93. During each of the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY and the second verification operation FINE VERIFY included in the fine operation FINE, the programming operation control unit 43 can disable the fourth control signal BLDIS with a logic low level and not electrically connect the bit line BL to the ground voltage VSS terminal via the fourth connection control unit 94. During the first verification operation FOGGY VERIFY included in the fuzzy operation FOGGY, the programming operation control unit 43 can activate the second control signals PB_SENSE and SA_CSOC with a first potential level LEVEL1 and electrically connect the sensing nodes SO and CSO to the bit line BL via the second connection control unit 92, thereby controlling the programming and verification circuit 41 to apply the first sensing voltage to the bit line BL. During the second verification operation FINE VERIFY included in the fine operation FINE, the programming operation control unit 43 can activate the second control signals PB_SENSE and SA_CSOC at a second potential level LEVEL2, which is higher than the first potential level LEVEL1, and electrically connect the sensing nodes SO and CSO to the bit line BL through the second connection control unit 92, thereby controlling the programming and verification circuit 41 to apply a second sensing voltage with a potential level higher than the first sensing voltage to the bit line BL.

[0143] According to embodiments of this disclosure, data can be stored in a non-volatile memory device through a programming operation that includes two different types of application operations and two different types of verification operations. Therefore, cell distribution can be effectively improved even when the amount of current consumed during the programming operation is minimized.

[0144] The effects obtainable from this disclosure are not limited to those described herein. Those skilled in the art to which this disclosure pertains will readily understand other effects not described herein, given the foregoing detailed description.

[0145] Although this disclosure has been illustrated and described with reference to specific embodiments and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that, as those skilled in the art will recognize from this disclosure, it can be implemented in various ways through substitutions, alterations, and modifications without departing from the spirit and / or scope of this disclosure and the appended claims.

[0146] For example, the arrangement and type of logic gates and transistors described in the foregoing embodiments can be implemented in different ways depending on the polarity of the input signal. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A non-volatile memory device, comprising: A memory cell array comprising multiple memory cells connected between multiple word lines and multiple bit lines; Peripheral circuit: Perform a fuzzing operation, the fuzzing operation including a first application operation of applying a first application voltage to a selected word line among the plurality of word lines and a first verification operation of applying a first verification voltage with a level equal to or higher than a target threshold voltage to the selected word line, and Perform fine-grained operations, the fine-grained operations including a second application operation of applying a second applied voltage to the selected word line and a second verification operation of applying a second verification voltage at a level equal to the target threshold voltage; as well as Control logic circuit: Whether the fuzzing operation is fully performed is determined based on whether the number of memory cells whose respective threshold voltages are higher than the first verification voltage is equal to or greater than a first predetermined number, as a result of the first verification operation. Whether to fully perform the fine operation is determined based on whether the number of memory cells whose respective threshold voltage is lower than the second verification voltage is less than or equal to a second predetermined number, as a result of the second verification operation.

2. The non-volatile memory device according to claim 1, The peripheral circuitry repeatedly performs the fuzzing operation until the fuzzing operation is determined to be fully executed. After the fuzzy operation is determined to be fully executed, the peripheral circuit repeats the fine operation until the fine operation is determined to be fully executed.

3. The non-volatile memory device according to claim 2, When the number of memory cells whose respective threshold voltages are higher than the first verification voltage is less than the first predetermined number, the peripheral circuit repeatedly performs the fuzzing operation, and When the number of memory cells whose respective threshold voltages are higher than the first verification voltage is equal to or greater than the first predetermined number, the peripheral circuit performs the fine operation.

4. The non-volatile memory device according to claim 3, When the number of memory cells whose respective threshold voltages are lower than the second verification voltage is greater than the second predetermined number, the peripheral circuit repeatedly performs the fine-tuning operation, and When the number of memory cells whose respective threshold voltage is lower than the second verification voltage is less than or equal to the second predetermined number, the peripheral circuit terminates the fine operation.

5. The non-volatile memory device according to claim 1, wherein the peripheral circuitry further includes: During the first verification operation, a first sensing voltage is applied to the bit line, and During the second verification operation, a second sensing voltage higher than the first sensing voltage is applied to the bit line.

6. The non-volatile memory device of claim 5, wherein the peripheral circuitry includes a plurality of page buffers respectively connected to the plurality of memory cells via the plurality of bit lines, and each page buffer includes: A latch having a logic level stored in the latch and determined based on whether programming operations are allowed on each of the plurality of bit lines; A first connection control unit, in response to the logic level stored in the latch and a first control signal, electrically connects the sensing node to the power supply voltage terminal; as well as The second connection control unit, in response to the second control signal, electrically connects each of the plurality of bit lines to the sensing node.

7. The non-volatile memory device of claim 6, wherein each of the plurality of page buffers: During each of the first and second verification operations, a power supply voltage is applied to the sensing node by activating the first control signal and electrically connecting the sensing node to the power supply voltage terminal via the first connection control unit. During the first verification operation, the first sensing voltage is applied to the bit line by activating the second control signal at a first potential level and electrically connecting the sensing node to the bit line via the second connection control unit. During the second verification operation, the second sensing voltage is applied to the bit line by activating the second control signal at a second potential level higher than the first potential level and electrically connecting the sensing node to the bit line via the second connection control unit.

8. A method of operating a non-volatile memory device, the method comprising: Perform a fuzzing operation, the fuzzing operation including a first application operation of applying a first application voltage to a selected word line among a plurality of word lines and a first verification operation of applying a first verification voltage with a level equal to or higher than a target threshold voltage to the selected word line; The execution of the first determination is the result of the first verification operation. The first determination determines whether the fuzzing operation should be fully executed based on whether the number of memory cells whose respective threshold voltages are higher than the first verification voltage is equal to or greater than a first predetermined number. Perform fine-grained operations, the fine-grained operations including a second application operation of applying a second applied voltage to the selected word line and a second verification operation of applying a second verification voltage at a level equal to the target threshold voltage; and The second determination is performed as a result of the second verification operation, and the second determination determines whether the fine operation is fully performed based on whether the number of memory cells whose respective threshold voltages are lower than the second verification voltage is less than or equal to a second predetermined number.

9. The operating method according to claim 8, The fuzzing operation is repeated until it is determined to be fully executed; and After the fuzzy operation is determined to be fully executed, the fine operation is repeated until the fine operation is determined to be fully executed.

10. The method of operation according to claim 9, wherein performing the first determination includes: When the number of memory cells whose respective threshold voltage is higher than the first verification voltage is less than the first predetermined number, it is determined that the fuzzing operation has not been fully performed. and When the number of memory cells whose respective threshold voltages are higher than the first verification voltage is equal to or greater than the first predetermined number, it is determined that the fuzzing operation is to be fully performed.

11. The method of operation according to claim 10, wherein performing the second determination includes: When the number of memory cells whose respective threshold voltages are lower than the second verification voltage is greater than the second predetermined number, it is determined that the fine operation has not been fully performed; and When the number of memory cells whose respective threshold voltages are lower than the second verification voltage is less than or equal to the second predetermined number, it is determined that the fine operation is fully executed.

12. The operating method according to claim 8, further comprising: During the first verification operation, a first sensing voltage is applied to the bit line; and During the second verification operation, a second sensing voltage higher than the first sensing voltage is applied to the bit line.

13. A method of operating a non-volatile memory device, the non-volatile memory device comprising rows of cells, the method comprising: Perform fuzzy programming on the row; A fuzz verification operation is performed to verify the fuzz programming operation by applying a fuzz verification voltage equal to or higher than the target threshold voltage to the row and applying a fuzz sensing voltage to the column of each cell. When the fuzzing operation is verified as successful, a fine programming operation is performed on the row. and A fine-verification operation to verify the fine programming operation is performed by applying a fine-verification voltage equal to the target threshold voltage to the row and a fine-sensing voltage higher than the blur sensing voltage to the column. When the number of units whose respective threshold voltages are higher than the fuzzy verification voltage is greater than the first threshold, the fuzzy programming operation is verified as successful, and The fine programming operation is verified as successful when the number of units whose respective threshold voltages are lower than the fuzzy verification voltage is less than the second threshold.

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