Register circuit module, integrated circuit chip and operating method thereof

Abstract

The present disclosure provides a register circuit module, an integrated circuit chip and an operating method thereof. The integrated circuit chip comprises the register circuit module. The register circuit module comprises a register unit and a gate unit. The register unit comprises a register and an AND gate. The register comprises a clock terminal for inputting a clock signal, a data input terminal for inputting a function data signal, a scan enable terminal for inputting a scan enable signal and a data output terminal for outputting an output signal corresponding to the function data signal. The AND gate comprises a first input terminal, a second input terminal and a first output terminal. The first input terminal of the AND gate is connected with the data output terminal of the register. The gate unit comprises a NOR gate. The NOR gate comprises a third input terminal and a second output terminal. The third input terminal of the NOR gate acquires the scan enable signal of the register. The second input terminal of the AND gate is connected with the second output terminal of the NOR gate. The present disclosure can effectively optimize the power consumption and area of the chip and reduce the cost on the basis of meeting the performance of the chip.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a register circuit module, an integrated circuit chip and an operating method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the integration of chips has been greatly improved, and chips with sub-micron elements have been developed. At present, due to the rapid development of mobile Internet and the increasing maturity of system-on-chip design technology, the market and consumers have higher performance and power consumption requirements for embedded system products. Therefore, the balance between low power consumption and high performance of chips is more important. SUMMARY

[0003] At least one embodiment of the present disclosure provides a register circuit module, comprising: a register unit comprising a flip-flop and an AND gate, wherein the flip-flop comprises a clock terminal, a data input terminal, a scan enable terminal and a data output terminal, the clock terminal is configured to input a clock signal, the data input terminal is configured to input a functional data signal, the scan enable terminal is configured to input a scan enable signal, the data output terminal is configured to output an output signal corresponding to the functional data signal, the AND gate comprises a first input terminal, a second input terminal and a first output terminal, and the first input terminal of the AND gate is connected with the data output terminal of the flip-flop; a gating unit comprising a NOR gate, wherein the NOR gate comprises a third input terminal and a second output terminal, the third input terminal of the NOR gate is configured to obtain the scan enable signal of the flip-flop, and the second input terminal of the AND gate is connected with the second output terminal of the NOR gate.

[0004] For example, in the register circuit module provided by at least one embodiment of the present disclosure, the register unit is an N-bit register unit, and N is an integer greater than or equal to 2; the second input terminal of the AND gate of each register unit in the N-bit register unit is connected with the second output terminal of the NOR gate, respectively.

[0005] For example, in the register circuit module provided by at least one embodiment of the present disclosure, the clock terminals of the flip-flops of each register unit in the N-bit register unit share one clock signal, and / or the scan enable terminals of the flip-flops of each register unit in the N-bit register unit share one scan enable signal.

[0006] For example, the register circuit module provided by at least one embodiment of the present disclosure further comprises a function enable control terminal, wherein the function enable control terminal is configured to provide a function enable control signal to instruct the flip-flop to output the output signal in a functional mode.

[0007] For example, in the register circuit module provided in at least one embodiment of the present disclosure, at least two of the flip-flop, the AND gate and the gating unit are configured to be integrated into one circuit.

[0008] At least one embodiment of the present disclosure provides an integrated circuit chip, comprising at least one register circuit module group, wherein the register circuit module group comprises at least one register circuit module as described in any of the above.

[0009] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the integrated circuit chip comprises two or more register circuit modules, and clock signals of flip-flops of two register circuit modules interacting with each other in the two or more register circuit modules correspond to different clock sources.

[0010] For example, the integrated circuit chip provided in at least one embodiment of the present disclosure further comprises a delay synchronizer, wherein the delay synchronizer is configured to perform delay configuration on at least one of the two register circuit modules interacting with each other, so as to synchronize the two register circuit modules.

[0011] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the register circuit module further comprises a function enable control end configured to provide a function enable control signal to instruct the flip-flop to output the output signal in a function mode.

[0012] For example, the integrated circuit chip provided in at least one embodiment of the present disclosure further comprises an address decoder, wherein the address decoder is configured to obtain an address signal corresponding to the register circuit module group and output a corresponding decoding signal to the function enable control end of each register circuit module in the register circuit module group by decoding the address signal.

[0013] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the integrated circuit chip comprises M register circuit module groups and M is an integer greater than or equal to 2, and each register circuit module in each register circuit module group comprises a register unit of the same bit number.

[0014] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the register unit of the register circuit module is an N-bit register unit, and N is an integer greater than or equal to 2.

[0015] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the register circuit module group further comprises a buffer, the buffer comprising a buffer input end and a buffer output end, the buffer input end being connected with the address decoder to obtain the decoding signal, and the buffer output end being connected with the function enable control end of the register circuit module to transmit the decoding signal to the function enable control end.

[0016] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the register circuit module group comprises P register circuit modules, and the integrated circuit chip further comprises at least P OR gates, P being a positive integer, the OR gate comprising Q fourth input ends and a third output end, Q being equal to N*M, the Q fourth input ends being respectively connected with the first output end of the AND gate of a corresponding register cell in the N register cells of a corresponding register circuit module in a corresponding register circuit module group in the M register circuit module groups, so that the third output end of the OR gate outputs register data.

[0017] For example, in the integrated circuit chip provided in at least one embodiment of the present disclosure, the flip-flop further comprises a scan input end and a scan output end, the scan input end being configured to receive a scan input signal for scanning, and the scan output end being configured to output a scan output signal corresponding to the scan input signal.

[0018] At least one embodiment of the present disclosure further provides an operation method of an integrated circuit chip, comprising: providing a register circuit module, wherein the register circuit module comprises a register cell and a gating cell, the register cell comprising a flip-flop and an AND gate, the flip-flop comprising a clock end, a data input end, a scan enable end and a data output end, the clock end being configured to input a clock signal, the data input end being configured to input a function data signal for a function mode, the scan enable end being configured to input a scan enable signal for a scan mode, and the data output end being configured to output an output signal corresponding to the function data signal, the AND gate comprising a first input end, a second input end and a first output end, the first input end of the AND gate being connected with the data output end of the flip-flop, and the gating cell comprising an NOR gate, the NOR gate comprising a third input end and a second output end, the third input end of the NOR gate being configured to obtain the scan enable signal of the flip-flop, and the second input end of the AND gate being connected with the second output end of the NOR gate; setting the scan enable signal of the flip-flop, so that the register circuit module is in the function mode or the scan mode; inputting a function data signal to the data input end of the flip-flop, and providing the clock signal of the flip-flop, so that the integrated circuit chip works in the function mode. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present disclosure, and for those ordinary skilled in the field, other drawings can also be obtained from these drawings without creative labor.

[0020] Figure 1 The structural schematic diagram of the register circuit module provided by some embodiments of the present disclosure is shown in the figure.

[0021] Figure 2 The structural schematic diagram of the integrated circuit chip provided by some embodiments of the present disclosure is shown in the figure.

[0022] Figure 3 The structural schematic diagram of the integrated circuit chip provided by some embodiments of the present disclosure is shown in the figure.

[0023] Figure 4 The structural schematic diagram of the integrated circuit chip provided by some embodiments of the present disclosure is shown in the figure.

[0024] Figure 5 The flow chart of the operation method of the integrated circuit chip provided by some embodiments of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments only constitute some embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those ordinary skilled in the art without creative labor fall within the protection scope of the present disclosure.

[0026] Unless otherwise defined, all the terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those ordinary skilled in the art to which the present disclosure belongs. It should also be understood that the terms such as those defined in the general dictionary should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an idealized or excessively formalized sense, unless the embodiments of the present disclosure explicitly define them.

[0027] The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "one", "a", or "the" do not denote a quantity restriction, but mean that at least one exists. Similarly, the terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" do not necessarily mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect.

[0028] Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in order. Instead, various steps can be processed in reverse order or simultaneously. Meanwhile, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0029] As chip design develops to the deep sub-micron era, power consumption becomes the most important design goal of high-performance chips, and all designs must be completed around a specific low-power consumption target. For example, in the test state, the power consumption in the currently widely used design based on scan chains is generally several times higher than that in the normal working state. Such high power consumption far exceeds the design target of the chip, thereby bringing considerable difficulties to the design and test process. Therefore, high-performance very large scale chips need to consider the demand for low power consumption. In addition, how to save wiring or winding resources and how to reduce circuit area are also the focus of researchers.

[0030] At least one embodiment of the present disclosure provides a register circuit module, which includes a register unit and a gate unit; the register unit includes a register and an AND gate, the register includes a clock terminal, a data input terminal, a scan enable terminal, and a data output terminal, the clock terminal is configured to input a clock signal, the data input terminal is configured to input a functional data signal, the scan enable terminal is configured to input a scan enable signal, the data output terminal is configured to output an output signal corresponding to the functional data signal, and the AND gate includes a first input terminal, a second input terminal, and a first output terminal, the first input terminal of the AND gate is connected with the data output terminal of the register; the gate unit includes a NOR gate, the NOR gate includes a third input terminal and a second output terminal, the third input terminal of the NOR gate is configured to obtain the scan enable signal of the register, and the second input terminal of the AND gate is connected with the second output terminal of the NOR gate.

[0031] At least one embodiment of the present disclosure also provides an integrated circuit chip, which includes at least one register circuit module group, and the register circuit module group includes at least one register circuit module as described above.

[0032] The register circuit module or integrated circuit chip of the above-mentioned embodiments of the present disclosure can effectively optimize the power consumption and area of the chip, reduce the cost, and improve the engineering development efficiency on the basis of meeting the performance of the chip through the cooperation of the AND gate of the register unit and the NAND gate of the gating unit.

[0033] The embodiments of the present disclosure and examples thereof will be described in detail below with reference to the accompanying drawings.

[0034] Figure 1 The structural diagram of the register circuit module provided by some embodiments of the present disclosure is shown.

[0035] For example, as shown in Figure 1 The register circuit module 100 provided by some embodiments of the present disclosure includes a register unit 110 and a gating unit 120. The register unit 110 includes a flip-flop 111 and an AND gate 112, and the gating unit 120 includes a NAND gate 121.

[0036] For example, as shown in Figure 1 The flip-flop 111 of the register unit 110 includes a clock end 101 (for example, the CLK end of the flip-flop 111 in Figure 1 ), a data input end 102 (for example, the D end of the flip-flop 111 in Figure 1 ), a scan enable end 103 (for example, the SE end of the flip-flop 111 in Figure 1 ), and a data output end 104 (for example, the Q end of the flip-flop 111). For example, the clock end 101 is configured to input a clock signal (for example, the clock signal CLK), the data input end 102 is configured to input a functional data signal (for example, the data signal D0 or D 15 ), the scan enable end 103 is configured to input a scan enable signal (for example, the scan enable signal SE), and the data output end 104 is configured to output an output signal corresponding to the functional data signal. For example, the AND gate 112 of the register unit 110 includes a first input end 105, a second input end 106, and a first output end 107, and the first input end 105 of the AND gate 112 is connected with the data output end 104 of the flip-flop 111.

[0037] For example, as shown in Figure 1As shown, the NOR gate 121 of the gating unit 120 includes a third input end 201 and a second output end 202, and the third input end 201 of the NOR gate 121 is configured to obtain the scan enable signal SE of the flip-flop 111, and the second input end 106 of the AND gate 112 is connected with the second output end 202 of the NOR gate 121. The first output end 107 of the AND gate 112 of the register unit 110 outputs the register unit output data (for example, Q0 or Q 15 ) according to the signal inputted by the first input end 105 (for example, the output signal outputted by the data output end 104) and the signal inputted by the second input end 106 (for example, the signal outputted by the second output end 202 of the NOR gate 121).

[0038] For example, as shown in Figure 1 , the gating unit 120 is a Q-gating (that is, QG as shown in Figure 1 , also known as Q gating or Q gate), which is signal connected with the Q end of the corresponding flip-flop.

[0039] The register circuit module or integrated circuit chip of the above-mentioned embodiments of the present disclosure can not only make the performance of the chip outstanding, but also reduce the power consumption of the chip, save the wiring resources of the chip, and reduce the cost of the chip through the cooperation of the AND gate logic of the register unit and the NOR gate logic of the gating unit.

[0040] In some examples, the register unit 110 of the register circuit module 100 is an N-bit register unit, that is, the register circuit module 100 includes N register units 110, and N is an integer greater than or equal to 2. The register circuit module of the embodiments of the present disclosure adopts a multi-bit register unit, which can improve the integration of the circuit and reduce unnecessary resources and workload.

[0041] For example, as shown in Figure 1 , the register circuit module 100 includes a 2-bit register unit (that is, a 2-bit register unit), that is Figure 1 , the register circuit module 100 in the example includes two register units 110, for example, one of which is denoted as register unit 110a, and the other is denoted as register unit 110b. Of course, this is only exemplary and is not a limitation of the present disclosure. The number of N can be one or more than three, which can be freely adjusted according to actual conditions, and the embodiments of the present disclosure do not make exhaustive and tedious descriptions.

[0042] The register unit of the embodiments of the present disclosure can be implemented as a single-bit register or a multi-bit register, which is highly versatile and has a wide application prospect.

[0043] In some examples, the N register units 110 of the register circuit module 100 are all identical in structure. Of course, this is merely exemplary and not a limitation of the present disclosure.

[0044] In some examples, the second input end 106 of the AND gate 112 of each of the N register units 110 of the register circuit module 100 is respectively connected to the second output end 202 of the NAND gate 121 of the register circuit module 100. For example, as shown in FIG. 1, the second input end 106 of the AND gate 112 of the register unit 110a in the register circuit module 100 and the second input end 106 of the AND gate 112 of the register unit 110b in the register circuit module 100 are both connected to the second output end 202 of the NAND gate 121. Figure 1

[0045] In some examples, the clock end 101 of the flip-flop 111 of each of the N register units 110 of the register circuit module 100 shares one clock signal.

[0046] For example, as shown in FIG. 1, the clock end 101 of the flip-flop 111 of the register unit 110a in the register circuit module 100 and the clock end 101 of the flip-flop 111 of the register unit 110b in the register circuit module 100 share one clock signal CLK. Figure 1

[0047] Thus, the embodiments of the present disclosure can improve the synchronization of each flip-flop in the register circuit module, can meet the timing requirements of the register, is simple to operate, and saves resources.

[0048] Of course, this is merely exemplary and not a limitation of the present disclosure. For example, the clock end 101 of the flip-flop 111 of each of the N register units 110 in the register circuit module 100 of the embodiments of the present disclosure can also have a corresponding clock signal, and the embodiments of the present disclosure do not limit and elaborate on this.

[0049] In some examples, the scan enable end 103 of the flip-flop 111 of each of the N register units 110 of the register circuit module 100 shares one scan enable signal.

[0050] For example, as shown in FIG. 1, the scan enable end 103 of the flip-flop 111 of the register unit 110a in the register circuit module 100 and the scan enable end 103 of the flip-flop 111 of the register unit 110b in the register circuit module 100 share one scan enable signal SE. Of course, this is merely exemplary and not a limitation of the present disclosure. Figure 1

[0051] ​​​Therefore, the embodiment of the present disclosure can realize the synchronous control of the scan of the chip circuit, is simple to operate, and saves resources.

[0052] In some examples, the register circuit module 100 can further include a function enable control end (not shown) configured to provide a function enable control signal to instruct the flip-flop 111 to output the output signal in the function mode. Figure 2

[0053] The register circuit module 100 of the embodiment of the present disclosure can be applied to the scan mode and the function mode of the chip, and thus, not only the additional test function can be realized, but also the basic function can be well completed.

[0054] In some examples, at least two of the flip-flop 111, the AND gate 112, and the gating unit 120 are integrated into one circuit. In this way, the integration degree of the register circuit module and the chip can be improved, and the area of the circuit and the chip can be reduced.

[0055] For example, the flip-flop 111, the AND gate 112, and the gating unit 120 are integrated into one circuit. Of course, this is merely an example that the flip-flop 111 and the AND gate 112 are integrated into one circuit, or the embodiment of the present disclosure can also integrate only the AND gate 112 and the gating unit 120 into one circuit, and the embodiment of the present disclosure does not limit this, which can be freely adjusted according to the actual situation, and thus, details are not described herein.

[0056] Figure 1 The structural schematic diagram of the integrated circuit chip provided by some embodiments of the present disclosure is shown.

[0057] For example, in some examples, the integrated circuit chip provided by some embodiments of the present disclosure includes at least one register circuit module group, and each register circuit module group includes at least one register circuit module, for example, the register circuit module can adopt the register circuit module 100 described above, that is, the register circuit module 100 shown in Figure 2 The technical effects of the integrated circuit chip can be referred to the description of the register circuit module 100 above, and details are not described herein.

[0058] In some examples, the integrated circuit chip includes M register circuit module groups and M is an integer greater than or equal to 2. In this way, the physical layout of the chip of the embodiment of the present disclosure is better, resources can be saved, operation is simple, and cost is reduced.

[0059] For example, as shown in Figure 2 ​As shown, the integrated circuit chip 2000 includes two register circuit module groups 2100, and each register circuit module group 2100 includes two register circuit modules 100. Of course, this is merely exemplary and not limiting of the present disclosure. For example, the number of register circuit module groups 2100 in the integrated circuit chip 2000 may be one or more than three (for example, the integrated circuit chip 2000 shown below includes 256 register circuit module groups 2100), and the number of register circuit modules 100 in a register circuit module group 2100 may also be one or more than three. These can be freely adjusted according to actual conditions, and the embodiments of the present disclosure do not provide an exhaustive list or detailed description of these.

[0060] In some examples, each register circuit module 100 in each register circuit module group 2100 of the M register circuit module groups 2100 of the integrated circuit chip 2000 includes register units 110 with the same number of bits. For example, Figure 1 Each register circuit module 100 in each register circuit module group 2100 is as follows Figure 3 Of course, this is merely exemplary and does not limit the embodiments of the present disclosure. For example, in the embodiments of the present disclosure, the number of register units 110 of each register circuit module 100 in each register circuit module group 2100 may be different (for example, the number of register units 110 of the first register circuit module 100 in one register circuit module group 2100 is different from the number of register units 110 of the second register circuit module 100). Alternatively, the number of register units 110 of the register circuit modules 100 in different register circuit module groups 2100 in the embodiments of the present disclosure may be different (for example, the number of register units 110 of each register circuit module 100 in one register circuit module group 2100 is different from the number of register units 110 of each register circuit module 100 in another register circuit module group 2100). The embodiments of the present disclosure are not limited to this, and it can be freely adjusted according to actual conditions, and will not be exhaustively listed or detailed here.

[0061] It should be noted that the drawings of the present disclosure are all simple schematic block diagrams of integrated circuit chips. The module composition and line connection relationship of the integrated circuit chips shown in the drawings are only a simple and intuitive schematic diagram, but they do not constitute a limitation of the circuit of the embodiments of the present disclosure. For example, the scan enable end of the trigger in the embodiments of the present disclosure is not limited to multiple triggers sharing one as shown in the drawings. It can also be other methods such as a multiplexer. As long as the basic function of the scan enable end can be achieved, technical personnel in this field should read and understand the technical solutions of the embodiments of the present disclosure in combination with the drawings and text descriptions. Since this is not the focus of the embodiments of the present disclosure that needs to be described, it will not be elaborated here.

[0062] Figure 1 A schematic structural diagram of an integrated circuit chip provided in some embodiments of the present disclosure.

[0063] In some examples, the integrated circuit chip 2000 includes more than two register circuit modules 100. For example, Figure 3 and Figure 3 As shown, the clock sources corresponding to the clock signals of the triggers 111 of two register circuit modules 100 interacting with each other in the two or more register circuit modules 100 in the integrated circuit chip 2000 are different. Figure 3 As shown, the clock signals corresponding to the two different clock sources are clock signal clk1 and clock signal clk2 respectively.

[0064] For example, Figure 3 As shown, the integrated circuit chip 2000 further includes a delay synchronizer 200, which is configured to delay at least one of the two register circuit modules 100 interacting with each other so as to synchronize the two register circuit modules 100. Figure 3 As shown, the integrated circuit chip 2000 further includes an address decoder 300. Since the address decoder 300 is not Figure 3 The example needs to explain the key points. Figure 4 The address decoder 300 in the example can be referred to the description of the address decoder 300 below, which will not be repeated here.

[0065] The integrated circuit chips of the above embodiments of the present disclosure can be applied to cross-clock domain design scenarios. They can not only effectively optimize chip power consumption and area, but also achieve a glitch-free effect when crossing clock domains, and have broad application prospects.

[0066] Figure 4 A schematic structural diagram of an integrated circuit chip provided in some other embodiments of the present disclosure.

[0067] For example, Figure 4As shown, each register circuit module 100 in the register circuit module group 2100 of the integrated circuit chip 200 includes 4 register units, i.e. Figure 4 The register circuit module 100 in the example includes 4 register units 110 (i.e. N=4).

[0068] For example, in the example, the register circuit module 100 includes 4 register units 110 (i.e. N=4). Figure 4 In the register circuit module 100 in the example, the data input ends of the respective flip-flops 111 are D0, D1, D2 and D3 ends respectively, the respective flip-flops 111 share a clock end CLK, the respective flip-flops 111 share a scan enable end SE, and the data output ends of the respective flip-flops 111 are Q0, Q1, Q2 and Q3 ends respectively. Of course, this is merely exemplary and is not a limitation on the embodiments of the present disclosure.

[0069] For example, as shown in Figure 4 The register circuit module 100 of the integrated circuit chip 2000 further includes a function enable control end 130 (e.g. a function enable control end En as shown in Figure 4 The function enable control end 130 is configured to provide a function enable control signal to instruct the flip-flops 111 of the register circuit module 100 to output the output signal in the function mode.

[0070] In some examples, the register circuit module group 2100 includes P register circuit modules 100, and P is a positive integer. In some examples, the integrated circuit chip 2000 further includes at least P OR gates 500, e.g. Figure 1 The integrated circuit chip 2000 in the example includes 2 OR gates 500, i.e. P equals 2.

[0071] For example, in the example of Figure 4 and Figure 4 The AND gate 112 in the register circuit module 100 of the integrated circuit chip 2000 can be one hot AND logic (also referred to as one hot and) and the OR gate 500 in the integrated circuit chip 2000 can be one hot OR logic (also referred to as one hot or). For example, one hot means to select one path of data to pass through in multiple paths of data (e.g. 256 paths of data in the example). Figure 4 For example, one hot AND logic means to select only one path of data to pass through in multiple paths of data (e.g. 256 paths of data in the example) through AND gate logic, and one hot OR logic selects only one path of data to pass through in multiple paths of data through OR gate logic. Figure 4

[0072] ​The chip of the integrated circuit of the above-mentioned embodiment of the present disclosure can not only achieve the effect of selecting the output register data by using the multiplexer, but also avoid increasing the wiring resources of the chip, moderately reduce the power consumption of the chip, and achieve higher integration and lower cost of the chip by cooperating with the one-hot and and one-hot or logic.

[0073] It should be noted that, since the above-mentioned manner of selecting the output register data by using the multiplexer is not the focus of the embodiment of the present disclosure, in order to ensure that the description of the embodiment of the present disclosure is clear and concise, the embodiment of the present disclosure will not repeat the related content of selecting the output register data by using the multiplexer.

[0074] For example, as shown in Figure 4 The integrated circuit chip 2000 further includes an address decoder 300, which is configured to obtain an address signal corresponding to the register circuit module group 2100 (for example, Add=0 or Add=255 as shown in Figure 4 The address decoder 300 is configured to decode the address signal and output a corresponding decoding signal to the function enable control end EN of each register circuit module 100 in the register circuit module group 2100.

[0075] In some examples, the address decoder 300 of the integrated circuit chip 2000 is configured to input a digital quantity (i.e., an address signal) and select one valid from a plurality of output ends according to the input digital quantity. For example, the address decoder 300 inputs an 8-bit digital quantity, the variation range of the 8-bit digital quantity is 00000000B-11111111B (B represents a binary number), and the output is 256 output ends (i.e., output decoding signals). According to the input quantity, only one of the 256 output ends is valid, for example, the selected valid signal (for example, the valid signal is 1) is the decoding signal transmitted to each register circuit module 100 in the register circuit module group 2100.

[0076] In some examples, the number of address signals obtained by the address decoder 300 is determined by the width of the address bus. For example, if the width of the address bus is 8 bits, there are 8 address buses (for example, Figure 1 As shown in Add[7:0]), and the addressing capability is 256. Therefore, the number of address signals of the address decoder 300 is 256, and the number of corresponding register circuit module groups 2100 in the integrated circuit chip 2000 is also 256 (i.e., M=256). Of course, this is only an example and is not a limitation of the present disclosure. For example, the width of the address bus can also be 16 bits or 32 bits, and the embodiment of the present disclosure does not exhaustively and repeatedly describe this.

[0077] The embodiment of the present disclosure can realize the cooperation design of one-hot AND and one-hot OR logic by adopting an address decoder to cooperate with an AND gate and an OR gate logic, can not only achieve the effect of selecting output register data by using a multiplexer, but also can avoid increasing the wiring resources of a chip, can moderately reduce the power consumption of the chip, and can achieve higher integration and lower cost of the chip.

[0078] It should be noted that the above-mentioned embodiments of the present disclosure divide and describe the integrated circuit chip 2000 according to register circuit module groups, register circuit modules, register units, and the like, however, it is clear to those skilled in the art that the integrated circuit chip 2000 of the embodiments of the present disclosure is not limited by the specific division, and the integrated circuit chip 2000 of the embodiments of the present disclosure can also be described by using other division methods, or can be without explicit division, which will not be described here.

[0079] In some examples, as shown in Figure 4 and Figure 4 If the scan enable signal SE of the scan enable end 103 is valid (for example, SE is 1), that is, the register unit 110 is in a scan mode, the first output end 107 of the register unit 110 can output 0 by the NAND gate 121 of the gating unit 120, because the second output end 202 of the NAND gate 121 outputs 0. If the scan enable signal SE of the scan enable end 103 is invalid (for example, SE is 0), that is, the register unit 110 is in a functional mode, the first output end 107 of the register unit 110 can output corresponding data (for example, when the other input end of the NAND gate 121 inputs 0).

[0080] In some examples, the embodiments of the present disclosure can realize the selection of one piece of data from multiple pieces of data (for example, 256 pieces of data) by the cooperation of the address decoder 300, the AND gate 112, and the OR gate 500. For example, as shown in Figure 4 of the 256 register circuit module groups 2100 of the integrated circuit chip 2000, the first output end 107 of the register unit 110 of only one of the 256 register circuit module groups 2100 inputs 1, and the first output end 107 of the register unit 110 of the other 255 register circuit module groups 2100 outputs 0, and the data output by the first output end 107 of the register unit 110 of the only one of the 256 register circuit module groups 2100 is equal to the output signal of the flip-flop 111 of the register unit 110, so that the final data (that is, the register data below) output by the OR gate 500 is the output signal of the flip-flop 111 of the register unit 110. Of course, this is only an example, and is not a limitation of the present disclosure.

[0081] For example, in some examples, the OR gate 500 of the integrated circuit chip 2000 includes Q fourth input terminals and a third output terminal, Q equals to N*M. For example, as shown in Figure 1 the OR gate 500 includes 1024 (i.e. 4*256) fourth input terminals 510 and one third output terminal 520.

[0082] For example, as shown in Figure 4 and Figure 4 the Q fourth input terminals 510 of the OR gate 500 of the integrated circuit chip 2000 are respectively connected with the first output terminals of the AND gates 112 of the corresponding register circuit modules 100 in the corresponding register circuit module groups 2100 in the M register circuit module groups 2100 of the integrated circuit chip 2000, so that the third output terminal of the OR gate 500 outputs the register data (for example, the register data O0 in Figure 1 ).

[0083] For example, as shown in Figure 4 and Figure 4 the fourth input terminals 510 of one of the OR gates 500 of the integrated circuit chip 2000 can input the data Q7, Q6, Q5, Q4, Q7’, Q6’, Q5’, Q4’ outputted by the first output terminals of the respective AND gates 112, and the fourth input terminals 510 of another of the OR gates 500 of the integrated circuit chip 2000 can input the data Q3, Q2, Q1, Q0, Q3’, Q2’, Q1’, Q0’ outputted by the first output terminals of the respective AND gates 112. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0084] For example, as shown in Figure 4 the register circuit module groups 2100 of the integrated circuit chip 2000 further include a buffer 400, the buffer 400 includes a buffer input terminal 410 and a buffer output terminal 420, the buffer input terminal 410 is connected with the address decoder 300 to obtain the corresponding decoding signal, and the buffer output terminal 420 is connected with the function enable control terminal 130 of the register circuit module 100 to transmit the corresponding decoding signal (for example, the valid signal) to the function enable control terminal 130. The integrated circuit chip of the embodiments of the present disclosure can make the whole circuit more stable and reduce the possibility of circuit error caused by signal mutation interference and the like by setting the buffer.

[0085] It should be noted that, Figure 4 the integrated circuit chip 2000 is a simple schematic block diagram, Figure 4 the module composition and the line connection relationship of the integrated circuit chip 2000 shown in the figure are only a simple and intuitive schematic diagram, and due to the size limitation of the drawing paper, Figure 5All the numbers of the register circuit module groups 2100 are not completely shown in the figure, but this is not a limitation of the embodiments of the present disclosure, and those skilled in the art should read and understand the technical solutions of the embodiments of the present disclosure in combination with the figures and the description, which will not be repeated here.

[0086] In some examples, the flip-flop 111 of the register unit 110 further includes a scan input end (not shown) and a scan output end (not shown), the scan input end is configured to receive a scan input signal for scanning, and the scan output end is configured to output a scan output signal corresponding to the scan input signal. For example, when the integrated circuit chip is in a scan mode, a test vector input through the scan input end can be used to implement, for example, a scan shift operation.

[0087] It should be noted that in the embodiments of the present disclosure, the integrated circuit chip 2000 can further include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific configuration of each module is not limited.

[0088] Each module in the above embodiments can be configured as software, hardware, firmware or any combination of the above, which performs a specific function. For example, these modules can correspond to a dedicated integrated circuit, can correspond to pure software code, and can also correspond to a software and hardware combined module.

[0089] Figure 1 The flowchart of the operation method of the integrated circuit chip provided by some embodiments of the present disclosure.

[0090] For example, as shown in Figure 4 , Figure 5 and Figure 5 , the operation method of the integrated circuit chip 2000 includes steps S11-S13.

[0091] Step S11, providing a register circuit module 100 for the integrated circuit 2000, wherein the register circuit module 100 comprises a register unit 110 and a gating unit 120; the register unit 110 comprises a flip-flop 111 and an AND gate 112; the flip-flop 111 comprises a clock terminal 101, a data input terminal 102, a scan enable terminal 103, and a data output terminal 104, the clock terminal 101 is configured to input a clock signal, the data input terminal 102 is configured to input a function data signal for a function mode, the scan enable terminal 103 is configured to input a scan enable signal for a scan mode, and the data output terminal 104 is configured to output an output signal corresponding to the function data signal; the AND gate 112 comprises a first input terminal 105, a second input terminal 106, and a first output terminal 107, the first input terminal 105 of the AND gate 112 is connected with the data output terminal 104 of the flip-flop 111, and the gating unit 120 comprises a NOR gate 121, the NOR gate 121 comprises a third input terminal 201 and a second output terminal 106, the third input terminal 201 of the NOR gate 121 is configured to obtain the scan enable signal of the flip-flop 111, and the second input terminal 106 of the AND gate 112 is connected with the second output terminal 106 of the NOR gate 121.

[0092] Step S12, setting the scan enable signal of the flip-flop 111, so that the register circuit module 100 is in the function mode or the scan mode.

[0093] Step S13, inputting the function data signal to the data input terminal 102 of the flip-flop 111, and providing the clock signal of the flip-flop 111 to make the integrated circuit chip 2000 work in the function mode.

[0094] It should be noted that the above series of operations not only include processes executed in time sequence in the order described herein, but also include processes executed in parallel or separately, rather than in time sequence. Embodiments of the present disclosure do not limit and elaborate on the order of steps of this flow.

[0095] The above refers to ​ The specific process of the operation method of the integrated circuit chip 2000 according to the embodiments of the present disclosure is described. Since the processing of each step included in the method corresponds to the structure or configuration of the integrated circuit chip described above, in order to avoid redundancy, the details are not described. However, those skilled in the art can understand that any technical details described with respect to the structure or configuration of the integrated circuit chip can be applied to each step included in the method.

[0096] It should be noted that in the embodiments of the present disclosure, the specific process and technical effects of the operation method of the integrated circuit chip 2000 can refer to the related description of the register circuit module 100 and the integrated circuit chip 2000 above, which will not be elaborated here.

[0097] The following points need to be explained:

[0098] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0099] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0100] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A register circuit module, comprising: A register unit, comprising a flip-flop and an AND gate, wherein the flip-flop comprises a clock terminal, a data input terminal, a scan enable terminal, and a data output terminal, the clock terminal being configured to input a clock signal, the data input terminal being configured to input a functional data signal, the scan enable terminal being configured to input a scan enable signal, and the data output terminal being configured to output an output signal corresponding to the functional data signal, the AND gate comprising a first input terminal, a second input terminal, and a first output terminal, the first input terminal of the AND gate being connected to the data output terminal of the flip-flop; A gating unit, comprising an NOR gate, wherein the NOR gate comprises a third input terminal and a second output terminal, the third input terminal of the NOR gate is configured to obtain the scan enable signal of the trigger, and the second input terminal of the AND gate is connected to the second output terminal of the NOR gate.

2. The register circuit module according to claim 1, wherein: The register unit is an N-bit register unit, where N is an integer greater than or equal to 2; The second input terminal of the AND gate of each register unit in the N-bit register unit is connected to the second output terminal of the NOR gate respectively.

3. The register circuit module according to claim 2, wherein: The clock terminal of the trigger of each register unit in the N-bit register unit shares one of the clock signals, and / or the scan enable terminal of the trigger of each register unit in the N-bit register unit shares one of the scan enable signals.

4. The register circuit module according to claim 1, further comprising a function enable control terminal, wherein: The function enable control terminal is configured to provide a function enable control signal to instruct the trigger to output the output signal in a function mode.

5. The register circuit module according to any one of claims 1 to 4, wherein: At least two of the trigger, the AND gate, and the gate control unit are configured to be integrated into one circuit.

6. An integrated circuit chip comprising at least one register circuit module group, wherein: The register circuit module group includes at least one register circuit module according to any one of claims 1 to 5.

7. The integrated circuit chip according to claim 6, wherein: The integrated circuit chip includes two or more register circuit modules. The clock sources corresponding to the clock signals of the triggers of two interacting register circuit modules among the two or more register circuit modules are different.

8. The integrated circuit chip according to claim 7, further comprising a delay synchronizer, wherein: The delay synchronizer is configured to perform delay configuration on at least one of the two register circuit modules interacting with each other, so as to synchronize the two register circuit modules.

9. The integrated circuit chip according to claim 6, wherein: The register circuit module also includes a function enable control terminal, The function enable control terminal is configured to provide a function enable control signal to instruct the trigger to output the output signal in a function mode.

10. The integrated circuit chip according to claim 9, further comprising an address decoder, wherein The address decoder is configured to obtain an address signal corresponding to the register circuit module group and decode the address signal to output a corresponding decoding signal to a function enable control terminal of each register circuit module in the register circuit module group.

11. The integrated circuit chip according to claim 10, wherein: The integrated circuit chip includes M register circuit module groups, where M is an integer greater than or equal to 2. Each register circuit module in each register circuit module group of the M register circuit module groups includes register units with the same number of bits.

12. The integrated circuit chip according to claim 11, wherein: The register unit of the register circuit module is an N-bit register unit, where N is an integer greater than or equal to 2.

13. The integrated circuit chip according to claim 12, wherein: The register circuit module group further includes a buffer, The buffer includes a buffer input end and a buffer output end, the buffer input end is connected to the address decoder to obtain the decoding signal, and the buffer output end is connected to the function enable control end of the register circuit module to transmit the decoding signal to the function enable control end.

14. The integrated circuit chip according to claim 11, wherein: The register circuit module group includes P register circuit modules, and the integrated circuit chip further includes at least P OR gates, where P is a positive integer. The OR gate includes Q fourth input terminals and a third output terminal, where Q is equal to N*M. The Q fourth input terminals are respectively connected to the first output terminal of the AND gate corresponding to a register unit in the N-bit register unit of the corresponding register circuit module in the corresponding register circuit module group in the M register circuit module groups, so that the third output terminal of the OR gate outputs register data.

15. The integrated circuit chip according to claim 6, wherein: The trigger further includes a scan input terminal and a scan output terminal, wherein the scan input terminal is configured to receive a scan input signal for scanning, and the scan output terminal is configured to output a scan output signal corresponding to the scan input signal.

16. A method for operating an integrated circuit chip, comprising: A register circuit module is provided, wherein the register circuit module includes a register unit and a gating unit, the register unit includes a flip-flop and an AND gate, the flip-flop includes a clock terminal, a data input terminal, a scan enable terminal, and a data output terminal, the clock terminal is configured to input a clock signal, the data input terminal is configured to input a functional data signal for a functional mode, the scan enable terminal is configured to input a scan enable signal for a scan mode, and the data output terminal is configured to output an output signal corresponding to the functional data signal, the AND gate includes a first input terminal, a second input terminal, and a first output terminal, the first input terminal of the AND gate is connected to the data output terminal of the flip-flop, the gating unit includes a NOR gate, the NOR gate includes a third input terminal and a second output terminal, the third input terminal of the NOR gate is configured to obtain the scan enable signal of the flip-flop, and the second input terminal of the AND gate is connected to the second output terminal of the NOR gate; Setting the scan enable signal of the trigger so that the register circuit module is in the functional mode or the scan mode; A functional data signal is input to the data input terminal of the trigger, and the clock signal of the trigger is provided to enable the integrated circuit chip to operate in the functional mode.

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