Semiconductor device manufacturing methods

Abstract

This application discloses a method for manufacturing a semiconductor device. The method includes providing a first wafer with a device structure formed on its front side; sequentially performing back-side thinning, back-side ion implantation, laser annealing, and back-side metal layer deposition on the first wafer to obtain a second wafer; sequentially dicing and mounting the second wafer to obtain a plurality of semiconductor devices; and performing thermal annealing on the plurality of semiconductor devices. This method can avoid oxidation of the back-side metal layer during thermal annealing.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device that combines the advantages of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a bipolar transistor. It combines the advantages of MOSFETs (easy to drive and simple to control) with the advantages of power transistors (low on-state voltage, high on-state current, and low losses), making it one of the core electronic components in modern power electronic circuits. IGBTs are widely used in various sectors of the national economy, including communications, energy, transportation, industry, medicine, home appliances, and aerospace. The application of IGBTs plays a crucial role in improving the performance of power electronic systems.

[0003] In existing IGBT manufacturing processes, thermal annealing is typically performed after the back metal layer is formed to improve ohmic contact and ensure a good electrical connection between the back metal layer and the back silicon material. However, during thermal annealing, the back metal layer is at risk of oxidation, which can affect the ohmic contact between the back metal layer and the back silicon material. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor device that can prevent the back metal layer from being oxidized during thermal annealing.

[0005] This application provides a method for manufacturing a semiconductor device, comprising:

[0006] Provide a first wafer on the front side having a device structure formed thereon;

[0007] The first wafer is subjected to back-side thinning, back-side ion implantation, laser annealing, and back-side metal layer deposition in sequence to obtain the second wafer;

[0008] The second wafer is sequentially diced and mounted to obtain several semiconductor devices;

[0009] The semiconductor devices are subjected to thermal annealing.

[0010] In the semiconductor device manufacturing method provided in this application, the thermal annealing process performed on the plurality of semiconductor devices includes:

[0011] Several of the semiconductor devices were subjected to low-temperature annealing in a nitrogen atmosphere.

[0012] In the semiconductor device manufacturing method provided in this application, the annealing temperature of the low-temperature annealing process is 380°C to 400°C.

[0013] In the semiconductor device manufacturing method provided in this application, the annealing time for the low-temperature annealing is 30 minutes.

[0014] In the method for manufacturing a semiconductor device provided in this application, after performing thermal annealing on the plurality of semiconductor devices, the method further includes:

[0015] Several semiconductor devices after thermal annealing are pretreated to obtain several target semiconductor devices.

[0016] In the semiconductor device manufacturing method provided in this application, the pretreatment of several semiconductor devices after thermal annealing to obtain several target semiconductor devices includes:

[0017] Several semiconductor devices after thermal annealing are sequentially subjected to bonding, encapsulation, curing and electroplating processes to obtain several target semiconductor devices.

[0018] In the semiconductor device manufacturing method provided in this application, the back-side ion implantation includes back-side boron ion implantation and / or back-side phosphorus ion implantation.

[0019] In the semiconductor device manufacturing method provided in this application, the depth of the back-side ion implantation is 1µm to 2µm.

[0020] In the semiconductor device manufacturing method provided in this application, the laser wavelength used in the laser annealing is 500nm to 600nm.

[0021] In the semiconductor device manufacturing method provided in this application, the material of the back metal layer includes at least one of Ti, Ni, Ag, Au, and Al.

[0022] In summary, the semiconductor device manufacturing method provided in this application includes providing a first wafer with a device structure formed on its front side; sequentially performing back-side thinning, back-side ion implantation, laser annealing, and back-side metal layer deposition on the first wafer to obtain a second wafer; sequentially performing dicing and mounting on the second wafer to obtain a plurality of semiconductor devices; and performing thermal annealing on the plurality of semiconductor devices. This solution eliminates the thermal annealing process after back-side metal layer deposition, moving this process to after mounting in the packaging process, thereby avoiding oxidation of the back-side metal layer during thermal annealing. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the first process of a semiconductor device manufacturing method provided in an embodiment of this application.

[0025] Figure 2 This is a second process diagram of a method for manufacturing a semiconductor device according to an embodiment of this application.

[0026] Figure 3 This is a schematic diagram of the third process of the semiconductor device manufacturing method provided in the embodiments of this application. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0029] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0030] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0031] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise stated, "several" means two or more.

[0032] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0033] In the existing IGBT manufacturing process, thermal annealing is usually performed after the back metal layer is formed to improve ohmic contact and enable the back metal layer to form a good electrical connection with the back silicon material.

[0034] However, during thermal annealing, the back metal layer carries a certain risk of oxidation, and the process places high demands on the purity of the gas and the equipment itself. Furthermore, because thermal annealing anneals the entire wafer, temperature variations exist within the equipment, leading to differences in annealing temperatures even within the same batch of wafers. This affects the consistency of the contact resistance between the IGBT's back metal layer and the back silicon material, ultimately impacting the consistency of the IGBT's critical saturation voltage (Vce).

[0035] Based on this, this application provides a method for manufacturing a semiconductor device, such as... Figure 1 As shown, the specific process of manufacturing this semiconductor device can be as follows:

[0036] 101. Provide a first wafer on which a device structure is formed on the front side.

[0037] In some embodiments, the first wafer may be a semiconductor substrate. In another embodiment, the first wafer may include a semiconductor substrate, a buried layer, and an epitaxial layer stacked sequentially from bottom to top.

[0038] In practice, a buried layer can be formed by ion implantation of a first conductivity type onto the upper surface of a semiconductor substrate. For example, Sb ion implantation can be performed on the upper surface of the semiconductor substrate to obtain a buried layer. There are various methods for forming the epitaxial layer, such as physical vapor deposition, chemical vapor deposition, or other suitable methods. The buried layer can have a first conductivity type, and the epitaxial layer can have a second conductivity type. It should be noted that the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

[0039] The semiconductor substrate can be made of materials such as single-crystal silicon, silicon carbide, gallium arsenide, indium phosphide, or germanium-silicon. It can also be a germanium-silicon substrate, a group III-V compound substrate, a silicon carbide substrate, or a stacked structure thereof, or a silicon-on-insulator structure. It can also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. In this embodiment, the semiconductor substrate is made of single-crystal silicon.

[0040] It is understood that this device structure may include source region, base region, gate structure, dielectric layer, and front metal layer, etc. It should be noted that this device structure includes, but is not limited to, the devices mentioned above; it may also include other devices, which will not be elaborated upon here.

[0041] It is understandable that the front side of the first wafer refers to the side where the device structure is formed, while the back side refers to the side opposite to the front side.

[0042] 102. The first wafer is subjected to back-side thinning, back-side ion implantation, laser annealing, and back-side metal layer deposition in sequence to obtain the second wafer.

[0043] In some embodiments, back-side thinning can specifically involve grinding the back side of the first wafer with a diamond grinding wheel, thereby reducing the thickness of the first wafer to the desired thickness.

[0044] Specifically, back-side ion implantation can be performed using an ion implanter to implant boron ions and / or phosphorus ions onto the back side of the first wafer. It should be noted that, in this embodiment, the depth of back-side ion implantation is 1µm to 2µm.

[0045] It is understandable that when using an ion implanter to perform back-side boron ion implantation and / or back-side phosphorus ion implantation on the back side of the first wafer, it will damage the lattice on the back side of the first wafer. Laser annealing is necessary to repair the lattice on the surface of the back side of the first wafer and activate the implanted boron and / or phosphorus ions.

[0046] Choosing an appropriate laser wavelength can control the laser annealing depth of the first wafer. Therefore, to ensure the laser annealing depth is controlled within 1µm to 2µm, allowing for ideal repair of dopant ion implantation damage and sufficient activation of the implanted ions to form a high-implantation-efficiency back-side collector junction, the laser wavelength used in this embodiment is 500nm to 600nm. Preferably, the laser wavelength used is 532nm.

[0047] In some embodiments, the back metal layer deposition can specifically be performed by metal sputtering. The material of the back metal layer may include at least one of Ti, Ni, Ag, Au, and Al.

[0048] 103. The second wafer is diced and mounted sequentially to obtain several semiconductor devices.

[0049] As can be understood, dicing separates the semiconductor devices on a second wafer, dividing the second wafer into several individual semiconductor devices. Surface mounting, on the other hand, uses adhesives such as solder paste to bond the semiconductor devices to the frame.

[0050] 104. Perform thermal annealing on several semiconductor devices.

[0051] Specifically, several semiconductor devices can be subjected to low-temperature annealing in a nitrogen atmosphere.

[0052] In this embodiment, since the thermal annealing process is moved to after die mounting in the packaging process, all semiconductor devices are now completely covered with solder paste, eliminating the possibility of contact with oxidizing gases and thus preventing the back metal layer from oxidizing during thermal annealing. Furthermore, after dicing and die mounting, the second wafer is separated into several individual semiconductor devices, resulting in more uniform heating. This leads to better consistency in the contact resistance between the back metal layer and the back wafer, and consequently, higher consistency in the critical saturation voltage (Vce) of the semiconductor devices.

[0053] Furthermore, the post-mount heat annealing process is compatible with the subsequent heat treatment process in the encapsulation process. Only the heat treatment process menu needs to be adjusted according to specific circumstances, without incurring additional process costs. This heat annealing process uses an annealing temperature between 380°C and 400°C and can be performed with a certain amount of protective gas, although the purity requirements for the gas are relatively low. In some embodiments, the annealing time is 30 minutes.

[0054] It is understandable that there are various types of solder paste. In specific implementations, the melting point of the solder paste can be adjusted through doping processes to form solder pastes with different melting points. It should be noted that the solder paste used in this embodiment is a high-temperature solder paste, the melting point of which is above the annealing temperature of the aforementioned thermal annealing process. That is, the melting point of this solder paste is greater than 400°C.

[0055] In some embodiments, to protect the chip from damage caused by physical, chemical, or other environmental factors and to enhance the chip's heat dissipation performance, the chip's input or output ports are brought out. After step 104, the following may be included:

[0056] 105. Several semiconductor devices after thermal annealing are pretreated to obtain several target semiconductor devices.

[0057] Specifically, step 105 may involve sequentially performing bonding, encapsulation, curing, and electroplating processes on several semiconductor devices after thermal annealing to obtain several target semiconductor devices. It should be noted that the specific processes of bonding, encapsulation, curing, and electroplating can be implemented using existing technologies and will not be elaborated upon here.

[0058] In summary, the semiconductor device manufacturing method provided in this application includes providing a first wafer with a device structure formed on its front side; sequentially performing back-side thinning, back-side ion implantation, laser annealing, and back-side metal layer deposition on the first wafer to obtain a second wafer; sequentially performing dicing and die bonding on the second wafer to obtain a plurality of semiconductor devices; and performing thermal annealing on the plurality of semiconductor devices. This solution moves the thermal annealing process after die bonding in the packaging process. At this point, the plurality of semiconductor devices are completely covered by solder paste, eliminating the conditions for contact with oxidizing gases, thereby preventing the back-side metal layer from being oxidized during the thermal annealing process.

[0059] The manufacturing method of the semiconductor device provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a first wafer on the front side having a device structure formed thereon; The first wafer is subjected to back-side thinning, back-side ion implantation, laser annealing and back-side metal layer deposition in sequence to obtain a second wafer. The back-side ion implantation includes back-side boron ion implantation and / or back-side phosphorus ion implantation. The depth of the back-side ion implantation is 1um to 2um. The laser wavelength used for laser annealing is 500nm to 600nm. The second wafer is sequentially diced and mounted to obtain several semiconductor devices; In a nitrogen atmosphere, several of the semiconductor devices are subjected to low-temperature annealing. The low-temperature annealing is performed after the semiconductor device is mounted and the back metal layer is covered with solder paste. The annealing temperature of the low-temperature annealing is 380°C to 400°C and the annealing time is 30 minutes.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After performing thermal annealing on the plurality of semiconductor devices, the process further includes: Several semiconductor devices after thermal annealing are pretreated to obtain several target semiconductor devices.

3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The process of pre-processing the semiconductor devices after thermal annealing to obtain a number of target semiconductor devices includes: Several semiconductor devices after thermal annealing are sequentially subjected to bonding, encapsulation, curing and electroplating processes to obtain several target semiconductor devices.

4. The method for manufacturing a semiconductor device according to any one of claims 1-3, characterized in that, The material of the back metal layer includes at least one of Ti, Ni, Ag, Au, and Al.

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