Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, comprising: providing a substrate, the substrate being provided with a UTM layer, the UTM layer at least comprising an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer comprising at least two dielectric layers formed in steps; etching the interlayer dielectric layer in steps, each etching step etching only one dielectric layer, and a certain interval time existing between adjacent etching steps. The application differentiates the etching steps of the interlayer dielectric layer, so that a certain interval time exists between the etching steps of each dielectric layer, thereby eliminating the stress between adjacent dielectric layers, releasing the accumulated electric charges between adjacent dielectric layers, reducing or avoiding the arc generation in the etching process of the interlayer dielectric layer, and thereby avoiding the generation of tower-shaped defects.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device manufacturing method. BACKGROUND

[0002] There is always a problem of accidentally suffering from tower defects in the mass production stage of 40nm radio frequency (RF) devices. By comparing the process of 40nm RF devices and 55nm RF devices, it is found that the thickness and deposition method of the interlayer dielectric layer in the back-end-of-line (BEOL) process of the two devices are different. Among them, the interlayer dielectric layer of the 40nm RF device is formed by a two-step deposition process. Therefore, it is suspected that there is charge accumulation at the junction of the two dielectric layers formed by the two-step deposition process, which causes arcing when etching to the junction, changes the environment in the process chamber, and thus forms the divergent tower defects.

[0003] After slicing the wafer with tower defects, it is found that there is a protrusion at the edge of the wafer (Edge) 0.7mm, which is consistent with the position of part of the arcing. Combined with process analysis, it is suspected that the bottom anti-reflection coating (BARC) at the edge of the wafer becomes thicker after edge bead removal (EBR), which causes stress accumulation between the films in the subsequent all-in-one (AIO) etching process of the trench and via and the back-end-of-line (BEOL) process.

[0004] By comparing the process of 40nm RF devices and 55nm RF devices again, it is found that the edge of the wafer used to manufacture 55nm RF devices is smoother, while the edge of the wafer used to manufacture 40nm RF devices is more outside during photoresist (Photo) edge bead removal and electroplated copper (ECP) edge bead removal, and the metal environment in the wafer is closer to the edge. Therefore, the charge accumulated in the ultra thick metal (UTM) layer of the wafer used to manufacture 40nm RF devices is more prone to micro arcing under stress, which is also the reason why tower defects are more likely to occur in the mass production process of 40nm RF devices. SUMMARY

[0005] The purpose of the present application is to provide a semiconductor device manufacturing method, which reduces or avoids the occurrence of arcing in the etching process of the ultra thick metal layer, thereby avoiding the occurrence of tower defects.

[0006] In order to achieve the above object, the present application provides a method for manufacturing a semiconductor device, comprising:

[0007] providing a substrate, wherein a UTM layer is formed on the substrate, the UTM layer at least comprising an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer comprising at least two dielectric layers formed step by step;

[0008] step by step etching the interlayer dielectric layer, each etching step etching only one of the dielectric layers, and a certain interval time existing between adjacent etching steps.

[0009] Optionally, the interval time is 5-20 seconds.

[0010] Optionally, a dry etching process is used to etch the dielectric layers.

[0011] Optionally, a plasma chemical vapor deposition process is used to form the dielectric layers.

[0012] Optionally, charge accumulation exists at the interface of adjacent dielectric layers.

[0013] Optionally, a patterned photoresist layer is further formed on the interlayer dielectric layer.

[0014] Optionally, the forming process of the patterned photoresist layer comprises:

[0015] forming a photoresist layer on the interlayer dielectric layer;

[0016] performing a trimming treatment on the patterned photoresist layer; and

[0017] performing a patterning treatment on the photoresist layer to form a patterned photoresist layer.

[0018] Optionally, the UTM layer further comprises an anti-reflection layer formed between the interlayer dielectric layer and the patterned photoresist layer.

[0019] Optionally, the UTM layer further comprises an etching stop layer formed between the substrate and the interlayer dielectric layer.

[0020] Optionally, the method for manufacturing a semiconductor device is used to manufacture a radio frequency device.

[0021] In summary, the present application provides a semiconductor device manufacturing method, comprising: providing a substrate, the substrate having a UTM layer formed thereon, the UTM layer comprising at least an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer comprising at least two dielectric layers formed in steps; etching the interlayer dielectric layer in steps, each etching step etching only one of the dielectric layers, and a certain interval time existing between adjacent etching steps. The present application differentiates the etching steps of the interlayer dielectric layer, so that a certain interval time exists between the etching steps of each dielectric layer, thereby eliminating the stress between adjacent dielectric layers, releasing the accumulated electric charges between adjacent dielectric layers, reducing or avoiding the electric arc generated in the etching process of the interlayer dielectric layer, and thereby avoiding the generation of tower-shaped defects. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A flow chart of a semiconductor device manufacturing method according to an embodiment of the present application;

[0023] Figures 2 to 5 A structure diagram corresponding to each step of a semiconductor device manufacturing method according to an embodiment of the present application;

[0024] In the drawings, the following notations are used:

[0025] 100 - substrate; 200 - carbon-doped silicon nitride layer; 300 - low dielectric oxide layer; 310 - metal via; 400 - etching stop layer; 500 - interlayer dielectric layer; 510, 520 - dielectric layer; 600 - anti-reflection layer; 700 - patterned photoresist layer. DETAILED DESCRIPTION

[0026] In order to make the purpose, advantages and features of the present application clearer, the following further describes the present application in combination with the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn in proportion, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different proportions are used.

[0027] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0028] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. (See attached document.) Figure 1 The semiconductor device manufacturing method described in this embodiment includes:

[0029] Step S01: Provide a substrate on which a UTM layer is formed, the UTM layer including at least an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer including at least two dielectric layers formed in steps;

[0030] Step S02: Etch the interlayer dielectric layer in steps, with each etching step etching only one dielectric layer, and there is a certain time interval between adjacent etching steps.

[0031] Figures 2 to 5 This is a schematic diagram of the structure corresponding to each step in the semiconductor device manufacturing method described in this embodiment. The following is in conjunction with... Figures 2 to 5 The manufacturing method of the semiconductor device described in this embodiment is explained in detail.

[0032] First, refer toFigure 2 and Figure 3 In step S01, a substrate 100 is provided, wherein an Ultra Thick Metal (UTM) layer is formed on the substrate 100, and the UTM layer comprises at least an interlayer dielectric layer 500 formed on the substrate 100, and the interlayer dielectric layer 500 comprises at least two dielectric layers 510 and 520 formed in steps.

[0033] In this embodiment, the UTM layer further comprises a Nitride Doped Silicon Carbide (NDC) layer 200, a low dielectric oxide layer 300 and an etching stop layer 400 formed between the substrate 100 and the interlayer dielectric layer, and an anti-reflective layer 600 and a patterned photoresist layer 700 formed on the interlayer dielectric layer 500. In other embodiments of the present application, other semiconductor structures can be included between the substrate 100 and the UTM layer, and the present application is not limited in this regard.

[0034] For example, the thickness of the patterned photoresist layer 700 is The thickness of the anti-reflective layer 600 is The thickness of the interlayer dielectric layer 500 is The thickness of the etching stop layer 400 is The thickness of the low dielectric oxide layer 300 is The thickness of the Nitride Doped Silicon Carbide layer 200 is The substrate 100 is a silicon (Si) substrate, the material of the low dielectric oxide layer 300 and the interlayer dielectric layer 500 comprises polyethylene oxide (PEOX), and the material of the etching stop layer 400 comprises silicon nitride (SiN). In other embodiments of the present application, the composition, thickness and material of each film layer in the semiconductor device can be adjusted according to actual needs, and the present application is not limited in this regard. Optionally, the UTM layer further comprises a metal via 310 penetrating through the low dielectric oxide layer 300 and the Nitride Doped Silicon Carbide layer 200.

[0035] Specifically, the process of forming the interlayer dielectric layer 500 and the patterned photoresist layer is as follows.

[0036] First, referring to Figure 2The interlayer dielectric layer 500 is formed by a plasma chemical vapor deposition process. In this embodiment, the dielectric layer 510 and 520 are formed by two deposition steps, and the dielectric layer 510 and 520 are stacked to form the interlayer dielectric layer 500, and there is a charge accumulation at the interface between the dielectric layer 510 and 520. In other embodiments of the present application, the interlayer dielectric layer can be formed by a stack of dielectric layers formed by multiple deposition steps, and the thickness of all the dielectric layers can be the same or not, which is not limited in the present application.

[0037] Next, referring to Figure 3 An anti-reflective layer 600 and a photoresist layer (not shown in the figure) are formed on the interlayer dielectric layer 500; the photoresist layer is subjected to a trimming process; and the photoresist layer is subjected to a patterning process to form a patterned photoresist layer 700. Optionally, the photoresist layer is subjected to an Edge Bead Removal (EBR) process to avoid the photoresist layer at the edge of the wafer from peeling off and causing pollution in the subsequent mechanical handling process.

[0038] Next, referring to Figure 4 and Figure 5 Step S02 is performed to etch the interlayer dielectric layer 500 step by step, and each etching step only etches one dielectric layer, and there is a certain interval time between adjacent etching steps.

[0039] In this embodiment, since the interlayer dielectric layer 500 includes the dielectric layers 510 and 520 formed by multiple deposition steps, the etching process of the interlayer dielectric layer 500 includes: first, referring to Figure 4 the dielectric layer 520 is etched with the patterned photoresist layer 700 as a mask; next, referring to Figure 5 the dielectric layer 510 is etched with the patterned photoresist layer 700 as a mask until the etching stop layer 400 is exposed. It should be noted that after the etching step of the dielectric layer 520 is completed, there is a certain interval time before the etching step of the dielectric layer 510 is performed, to release the charge accumulated at the interface between the dielectric layer 510 and 520, to avoid the Arcing condition in the etching process due to charge accumulation, thereby avoiding the formation of a tower-shaped defect. Optionally, the interval time is 5 sec to 20 sec. Optionally, a dry etching process is used to etch the dielectric layers 510 and 520.

[0040] Meanwhile, during the trimming process of the photoresist layer, the thickness of the anti-reflection layer 600 under the part of the photoresist layer removed by trimming can be changed, thus causing stress change between the film layers in the UTM layer. Stopping a certain interval time between the etching steps of the dielectric layer 520 and the dielectric layer 510 can also release the stress between the dielectric layer 520 and the dielectric layer 510, thus eliminating the negative influence of the stress on the semiconductor device.

[0041] In the embodiment, the method for manufacturing the semiconductor device is used for manufacturing a Radio Frequency (RF) device, especially for the mass production process of a 44nm RF device. In other embodiments of the present application, the method for manufacturing the semiconductor device can be used for manufacturing other semiconductor devices with the same or similar structure, and the present application does not limit this.

[0042] Compared with the prior method for manufacturing the semiconductor device, the method for manufacturing the semiconductor device according to the embodiment differentiates the etching steps of the interlayer dielectric layer according to the deposition process of the interlayer dielectric layer, so that a certain interval time exists between the etching steps of each dielectric layer, thus eliminating the stress between the adjacent dielectric layers, releasing the accumulated charges between the adjacent dielectric layers, reducing or avoiding the arc generated in the etching process of the interlayer dielectric layer, and thus avoiding the generation of the tower-shaped defects.

[0043] In summary, the present application provides a method for manufacturing a semiconductor device, which comprises: providing a substrate, the substrate being provided with a UTM layer, the UTM layer at least comprising an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer comprising at least two dielectric layers formed step by step; and etching the interlayer dielectric layer step by step, each etching step etching only one dielectric layer, and a certain interval time existing between the adjacent etching steps. The present application differentiates the etching steps of the interlayer dielectric layer, so that a certain interval time exists between the etching steps of each dielectric layer, thus eliminating the stress between the adjacent dielectric layers, releasing the accumulated charges between the adjacent dielectric layers, reducing or avoiding the arc generated in the etching process of the interlayer dielectric layer, and thus avoiding the generation of the tower-shaped defects.

[0044] The above merely describes the preferred embodiments of the present application and does not limit the present application in any way. Any person skilled in the art can make any equivalent replacement, modification or change to the technical solutions and technical contents disclosed in the present application without departing from the scope of the technical solutions of the present application, and such still falls within the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a UTM layer is formed, the UTM layer including at least an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer including at least two dielectric layers formed in steps, and charge accumulation exists at the interface between adjacent dielectric layers; The interlayer dielectric layer is etched in steps, with each etching step etching only one dielectric layer, and there is a certain interval between adjacent etching steps, the interval being 5 seconds to 20 seconds.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The dielectric layer is etched using a dry etching process.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The dielectric layer is formed using plasma chemical vapor deposition.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, A patterned photoresist layer is also formed on the interlayer dielectric layer.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The process of forming the patterned photoresist layer includes: A photoresist layer is formed on the interlayer dielectric layer; The photoresist layer is subjected to edge washing treatment; and The photoresist layer is patterned to form a patterned photoresist layer.

6. The method for manufacturing a semiconductor device as described in claim 4 or 5, characterized in that, The UTM layer also includes an anti-reflective layer formed between the interlayer dielectric layer and the patterned photoresist layer.

7. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The UTM layer also includes an etch stop layer formed between the substrate and the interlayer dielectric layer.

8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The method for manufacturing the semiconductor device is used to manufacture radio frequency devices.

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